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Searched refs:HFXO0 (Results 1 – 25 of 75) sorted by relevance

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/hal_silabs-3.6.0/gecko/service/hfxo_manager/src/
Dsl_hfxo_manager_hal_s2.c142 HFXO0->IEN_CLR = HFXO_IEN_RDY | HFXO_IEN_DNSERR | HFXO_IEN_COREBIASOPTERR; in sli_hfxo_manager_init_hardware()
144 HFXO0->IEN_CLR = HFXO_IEN_PRSRDY; in sli_hfxo_manager_init_hardware()
147 HFXO0->IF_CLR = HFXO_IF_RDY | HFXO_IF_DNSERR | HFXO_IEN_COREBIASOPTERR; in sli_hfxo_manager_init_hardware()
149 HFXO0->IF_CLR = HFXO_IF_PRSRDY; in sli_hfxo_manager_init_hardware()
155 HFXO0->IEN_SET = HFXO_IEN_RDY | HFXO_IEN_DNSERR | HFXO_IEN_COREBIASOPTERR; in sli_hfxo_manager_init_hardware()
158 HFXO0->IEN_SET = HFXO_IEN_PRSRDY; in sli_hfxo_manager_init_hardware()
159 HFXO0->CTRL &= ~(_HFXO_CTRL_DISONDEMANDPRS_MASK & HFXO_CTRL_DISONDEMANDPRS_DEFAULT); in sli_hfxo_manager_init_hardware()
160 HFXO0->CTRL |= HFXO_CTRL_PRSSTATUSSEL1_ENS; in sli_hfxo_manager_init_hardware()
196 …ready = (((HFXO0->STATUS & (HFXO_STATUS_RDY | HFXO_STATUS_PRSRDY)) != 0) && !error_flag) ? true : … in sli_hfxo_manager_is_hfxo_ready()
198 ready = (((HFXO0->STATUS & HFXO_STATUS_RDY) != 0) && !error_flag) ? true : false; in sli_hfxo_manager_is_hfxo_ready()
[all …]
/hal_silabs-3.6.0/gecko/service/power_manager/src/
Dsl_power_manager_hal_s2.c369 if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 in EMU_EM23PostsleepHook()
371 || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { in EMU_EM23PostsleepHook()
375 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; in EMU_EM23PostsleepHook()
393 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; in EMU_EM23PostsleepHook()
426 if (((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0 in sli_power_manager_restore_high_freq_accuracy_clk()
428 || (HFXO0->STATUS & _HFXO_STATUS_RDY_MASK) != 0) { in sli_power_manager_restore_high_freq_accuracy_clk()
432 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; in sli_power_manager_restore_high_freq_accuracy_clk()
448 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; in sli_power_manager_restore_high_freq_accuracy_clk()
527 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; in sli_power_manager_restore_states()
/hal_silabs-3.6.0/gecko/emlib/src/
Dem_cmu.c1472 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; in sli_em_cmu_HFXOSetForceEnable()
1566 oscForceEnStatus = (HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) != 0; in CMU_ClockSelectSet()
1567 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN; in CMU_ClockSelectSet()
1625 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; in CMU_ClockSelectSet()
1627 while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { in CMU_ClockSelectSet()
2966 HFXO0->LOCK = HFXO_LOCK_LOCKKEY_UNLOCK; in CMU_HFXOInit()
2969 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND in CMU_HFXOInit()
2974 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; in CMU_HFXOInit()
2975 while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) { in CMU_HFXOInit()
2978 while ((HFXO0->STATUS & HFXO_STATUS_SYNCBUSY) != 0U) { in CMU_HFXOInit()
[all …]
/hal_silabs-3.6.0/gecko/emlib/inc/
Dem_chip.h313 if (chipRev.major == 0x01 && (HFXO0->STATUS & HFXO_STATUS_ENS) == 0U) { in CHIP_Init()
Dsli_em_cmu.h106 if ((HFXO0->CTRL & HFXO_CTRL_DISONDEMAND) == 0) { \
107 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN; \
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c222f352gm40.h898 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
Defr32bg22c222f352gn32.h884 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
Defr32bg22c224f512gm32.h884 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
Defr32bg22c224f512gm40.h898 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
Defr32bg22c224f512gn32.h884 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
Defr32bg22c224f512im32.h884 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
Defr32bg22c224f512im40.h898 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO… macro
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21a010f512im32.h867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21a010f768im32.h867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21a020f1024im32.h869 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21a020f512im32.h869 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21a020f768im32.h869 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21b010f1024im32.h867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21b010f512im32.h867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21b010f768im32.h867 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21b020f1024im32.h869 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21b020f512im32.h869 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Defr32mg21b020f768im32.h869 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro
Drm21z000f1024im32.h865 #define HFXO0 ((HFXO_TypeDef *) HFXO0_BASE) /**< HFXO0 base po… macro

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