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Searched refs:FSRCO_S_BASE (Results 1 – 25 of 69) sorted by relevance

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/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22c222f352gm40.h494 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
607 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
814 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c222f352gn32.h480 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
593 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
800 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c224f512gm32.h480 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
593 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
800 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c224f512gm40.h494 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
607 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
814 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c224f512gn32.h480 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
593 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
800 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c224f512im32.h480 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
593 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
800 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c224f512im40.h494 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
607 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
814 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c112f352gm32.h478 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
591 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
798 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c112f352gm40.h492 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
605 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
812 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
Defr32bg22c222f352gm32.h480 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
593 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
800 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRC…
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21a010f1024im32.h463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21a010f512im32.h463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21a010f768im32.h463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21a020f1024im32.h465 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
578 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
785 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21a020f512im32.h465 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
578 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
785 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21a020f768im32.h465 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
578 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
785 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21b010f1024im32.h463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21b010f512im32.h463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21b010f768im32.h463 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
576 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
783 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21b020f1024im32.h465 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
578 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
785 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21b020f512im32.h465 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
578 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
785 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Defr32mg21b020f768im32.h465 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
578 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
785 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
Drm21z000f1024im32.h461 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
574 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
781 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base …
/hal_silabs-3.6.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27c140f768im32.h536 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
651 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
863 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base poi…
Defr32bg27c140f768im40.h552 #define FSRCO_S_BASE (0x40018000UL) /* FSRCO_S base address */ macro
667 #define FSRCO_BASE (FSRCO_S_BASE) /* FSRCO base address */
879 #define FSRCO_S ((FSRCO_TypeDef *) FSRCO_S_BASE) /**< FSRCO_S base poi…

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