1 /***************************************************************************//**
2 * @file
3 * @brief Energy Management Unit (EMU) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_EMU_H
32 #define EM_EMU_H
33
34 #include "em_device.h"
35 #include "sl_status.h"
36 #if defined(EMU_PRESENT)
37
38 #include <stdbool.h>
39 #include "em_bus.h"
40 #include "sl_common.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /***************************************************************************//**
47 * @addtogroup emu
48 * @{
49 ******************************************************************************/
50
51 /*******************************************************************************
52 ******************************* DEFINES ***********************************
53 ******************************************************************************/
54
55 #if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \
56 && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200)
57 /** Voltage scaling present */
58 #define EMU_VSCALE_PRESENT
59 #if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
60 /** Voltage scaling for EM01 present */
61 #define EMU_VSCALE_EM01_PRESENT
62 #endif
63 #endif
64
65 #if defined(_EMU_DCDCCTRL_MASK)
66 /** DC-DC buck converter present */
67 #define EMU_SERIES1_DCDC_BUCK_PRESENT
68 #endif
69
70 #if defined(_SILICON_LABS_DCDC_FEATURE) \
71 && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BUCK) \
72 || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB))
73 /** DC-DC buck converter present */
74 #define EMU_SERIES2_DCDC_BUCK_PRESENT
75 #endif
76
77 #if defined(_SILICON_LABS_DCDC_FEATURE) \
78 && ((_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOOST) \
79 || (_SILICON_LABS_DCDC_FEATURE == _SILICON_LABS_DCDC_FEATURE_DCDC_BOB))
80 /** DC-DC boost converter present */
81 #define EMU_SERIES2_DCDC_BOOST_PRESENT
82 #endif
83
84 /*******************************************************************************
85 ******************************** ENUMS ************************************
86 ******************************************************************************/
87
88 #if defined(_EMU_EM4CONF_OSC_MASK)
89 /** EM4 duty oscillator. */
90 typedef enum {
91 /** Select ULFRCO as duty oscillator in EM4. */
92 emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
93 /** Select LFXO as duty oscillator in EM4. */
94 emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
95 /** Select LFRCO as duty oscillator in EM4. */
96 emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
97 } EMU_EM4Osc_TypeDef;
98 #endif
99
100 #if defined(_EMU_BUCTRL_PROBE_MASK)
101 /** Backup Power Voltage Probe types. */
102 typedef enum {
103 /** Disable voltage probe. */
104 emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
105 /** Connect probe to VDD_DREG. */
106 emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
107 /** Connect probe to BU_IN. */
108 emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN,
109 /** Connect probe to BU_OUT. */
110 emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT
111 } EMU_Probe_TypeDef;
112 #endif
113
114 #if defined(_EMU_PWRCONF_PWRRES_MASK)
115 /** Backup Power Domain resistor selection. */
116 typedef enum {
117 /** Main power and backup power connected with RES0 series resistance. */
118 emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
119 /** Main power and backup power connected with RES1 series resistance. */
120 emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
121 /** Main power and backup power connected with RES2 series resistance. */
122 emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
123 /** Main power and backup power connected with RES3 series resistance. */
124 emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
125 } EMU_Resistor_TypeDef;
126 #endif
127
128 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
129 /** Backup Power Domain power connection. */
130 typedef enum {
131 /** No connection between main and backup power. */
132 emuPower_None = EMU_BUINACT_PWRCON_NONE,
133 /** Main power and backup power connected through diode,
134 allowing current from backup to main only. */
135 emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
136 /** Main power and backup power connected through diode,
137 allowing current from main to backup only. */
138 emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
139 /** Main power and backup power connected without diode. */
140 emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
141 } EMU_Power_TypeDef;
142 #endif
143
144 #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK)
145 /** Backup Power Domain power connection configuration when not in backup mode selection. */
146 typedef enum {
147 /** No connection. */
148 emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE,
149 /** Allow power from main to backup. */
150 emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU,
151 /** Allow power from backup to main. */
152 emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN,
153 /** Backup and main power are connected. */
154 emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE,
155 } EMU_BUBuInactPwrCon_TypeDef;
156 #endif
157
158 #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK)
159 /** Backup Power Domain power connection configuration in backup mode selection. */
160 typedef enum {
161 /** No connection. */
162 emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE,
163 /** Allow power from main to backup. */
164 emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU,
165 /** Allow power from backup to main. */
166 emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN,
167 /** Backup and main power are connected. */
168 emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE,
169 } EMU_BUBuActPwrCon_TypeDef;
170 #endif
171
172 #if defined(_EMU_BUCTRL_PWRRES_MASK)
173 /** Backup Power Domain resistor selection. */
174 typedef enum {
175 /** Main power and backup power connected with RES0 series resistance. */
176 emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0,
177 /** Main power and backup power connected with RES1 series resistance. */
178 emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1,
179 /** Main power and backup power connected with RES2 series resistance. */
180 emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2,
181 /** Main power and backup power connected with RES3 series resistance. */
182 emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3,
183 } EMU_BUPwrRes_TypeDef;
184 #endif
185
186 #if defined(_EMU_BUCTRL_VOUTRES_MASK)
187 /** Resistance between backup domain power supply and BU_VOUT. */
188 typedef enum {
189 /** BU_VOUT is not connected. */
190 emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS,
191 /** Enable weak switch. */
192 emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK,
193 /** Enable medium switch. */
194 emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED,
195 /** Enable strong switch. */
196 emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG,
197 } EMU_BUVoutRes_TypeDef;
198 #endif
199
200 /** BOD threshold setting selector, active or inactive mode. */
201 typedef enum {
202 /** Configure BOD threshold for active mode. */
203 emuBODMode_Active,
204 /** Configure BOD threshold for inactive mode. */
205 emuBODMode_Inactive,
206 } EMU_BODMode_TypeDef;
207
208 /** EM4 modes. */
209 typedef enum {
210 /** EM4 Shutoff. */
211 emuEM4Shutoff = 0,
212 /** EM4 Hibernate. */
213 emuEM4Hibernate = 1,
214 } EMU_EM4State_TypeDef;
215
216 #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
217 /** EM4 Pin Retention Type. */
218 typedef enum {
219 /** No Retention: Pads enter reset state when entering EM4. */
220 emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
221 /** Retention through EM4: Pads enter reset state when exiting EM4. */
222 emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
223 /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to
224 release pins from retention after EM4 wakeup. */
225 emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
226 } EMU_EM4PinRetention_TypeDef;
227 #endif
228
229 /** Power configurations. DCDC-to-DVDD is currently the only supported mode. */
230 typedef enum {
231 /** DCDC is connected to DVDD. */
232 emuPowerConfig_DcdcToDvdd,
233 } EMU_PowerConfig_TypeDef;
234
235 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
236 /** DCDC operating modes. */
237 typedef enum {
238 /** DCDC regulator bypass. */
239 emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
240 /** DCDC low-noise mode. */
241 emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
242 #if defined(_EMU_DCDCLPEM01CFG_MASK)
243 /** DCDC low-power mode. */
244 emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER,
245 #endif
246 } EMU_DcdcMode_TypeDef;
247
248 /** DCDC operating modes in EM2 or EM3. */
249 typedef enum {
250 /** DCDC mode is low power. */
251 emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER,
252 /** DCDC mode is according to DCDCMODE field. */
253 emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW,
254 } EMU_DcdcModeEM23_TypeDef;
255
256 #endif
257
258 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
259 /** DCDC conduction modes. */
260 typedef enum {
261 /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization
262 features are available in this mode. */
263 emuDcdcConductionMode_ContinuousLN,
264 /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or
265 for EFR32 when its radio is not enabled. */
266 emuDcdcConductionMode_DiscontinuousLN,
267 } EMU_DcdcConductionMode_TypeDef;
268 #endif
269
270 #if defined(_EMU_PWRCTRL_MASK)
271 /** DCDC to DVDD mode analog peripheral power supply select. */
272 typedef enum {
273 /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */
274 emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
275 /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */
276 emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
277 } EMU_DcdcAnaPeripheralPower_TypeDef;
278 #endif
279
280 #if defined(_EMU_DCDCMISCCTRL_MASK)
281 /** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */
282 typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
283
284 /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */
285 #define emuDcdcLnHighEfficiency -1
286
287 /** Default reverse current for fast transient response mode (low noise). */
288 #define emuDcdcLnFastTransient 160
289 #endif
290
291 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
292 /** DCDC Low-noise RCO band select. */
293 typedef enum {
294 /** Set RCO to 3MHz. */
295 emuDcdcLnRcoBand_3MHz = 0,
296 /** Set RCO to 4MHz. */
297 emuDcdcLnRcoBand_4MHz = 1,
298 /** Set RCO to 5MHz. */
299 emuDcdcLnRcoBand_5MHz = 2,
300 /** Set RCO to 6MHz. */
301 emuDcdcLnRcoBand_6MHz = 3,
302 /** Set RCO to 7MHz. */
303 emuDcdcLnRcoBand_7MHz = 4,
304 /** Set RCO to 8MHz. */
305 emuDcdcLnRcoBand_8MHz = 5,
306 /** Set RCO to 9MHz. */
307 emuDcdcLnRcoBand_9MHz = 6,
308 /** Set RCO to 10MHz. */
309 emuDcdcLnRcoBand_10MHz = 7,
310 } EMU_DcdcLnRcoBand_TypeDef;
311
312 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
313 /* Deprecated. */
314 #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz
315 #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz
316 #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz
317 #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz
318 #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz
319 #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz
320 #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz
321 #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz
322 /** @endcond */
323
324 /** DCDC Low Noise Compensator Control register. */
325 typedef enum {
326 /** DCDC capacitor is 1uF. */
327 emuDcdcLnCompCtrl_1u0F,
328 /** DCDC capacitor is 4.7uF. */
329 emuDcdcLnCompCtrl_4u7F,
330 } EMU_DcdcLnCompCtrl_TypeDef;
331 #endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */
332
333 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
334 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
335
336 /** DCDC mode. */
337 typedef enum {
338 emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */
339 emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */
340 } EMU_DcdcMode_TypeDef;
341 #endif
342
343 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
344 /** VREGIN comparator threshold. */
345 typedef enum {
346 emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */
347 emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */
348 emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */
349 emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */
350 } EMU_VreginCmpThreshold_TypeDef;
351
352 /** DCDC Buck Ton max timeout. */
353 typedef enum {
354 #if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \
355 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7))
356 emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */
357 emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */
358 emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */
359 emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */
360 emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */
361 emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */
362 emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */
363 emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */
364 #else
365 emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */
366 emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */
367 emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */
368 emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */
369 emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */
370 emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */
371 emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */
372 emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */
373 emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */
374 emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */
375 emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */
376 emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */
377 emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */
378 emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */
379 emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */
380 emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */
381 emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */
382 emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */
383 emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */
384 emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */
385 emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */
386 emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */
387 emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */
388 emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */
389 emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */
390 emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */
391 emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */
392 emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */
393 emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */
394 emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */
395 emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */
396 emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */
397 #endif
398 } EMU_DcdcTonMaxTimeout_TypeDef;
399
400 /** DCDC Buck drive speed. */
401 typedef enum {
402 emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
403 emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
404 emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
405 emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
406 } EMU_DcdcDriveSpeed_TypeDef;
407
408 /** DCDC Buck peak current setting. */
409 typedef enum {
410 #if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA)
411 emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA. */
412 #endif
413 #if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD5MA)
414 emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_LOAD5MA, /**< Load 5mA, peak current 90mA. */
415 #endif
416 #if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA)
417 emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA. */
418 #endif
419 #if defined(_DCDC_EM23CTRL0_IPKVAL_LOAD10MA)
420 emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_LOAD10MA, /**< Load 10mA, peak current 150mA. */
421 #endif
422 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA)
423 emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */
424 #endif
425 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA)
426 emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */
427 #endif
428 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA)
429 emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */
430 #endif
431 emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */
432 emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */
433 emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */
434 emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */
435 emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */
436 emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */
437 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA)
438 emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */
439 #endif
440 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA)
441 emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */
442 #endif
443 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA)
444 emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */
445 #endif
446 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA)
447 emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */
448 #endif
449 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA)
450 emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */
451 #endif
452 } EMU_DcdcPeakCurrent_TypeDef;
453 #endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */
454
455 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
456 /** DCDC Boost drive speed. */
457 typedef enum {
458 emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
459 emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
460 emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
461 emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING /**< Recommend no options other than DEFAULT be used here, as there is no benefit. */
462 } EMU_DcdcBoostDriveSpeed_TypeDef;
463
464 /** DCDC Boost EM01 peak current setting. */
465 typedef enum {
466 emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */
467 emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */
468 emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */
469 emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */
470 emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */
471 emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */
472 emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */
473 emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */
474 emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */
475 emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */
476 } EMU_DcdcBoostEM01PeakCurrent_TypeDef;
477
478 /** DCDC Boost Toff max timeout */
479 typedef enum {
480 emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */
481 emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */
482 emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */
483 emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */
484 emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */
485 emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */
486 emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */
487 emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */
488 } EMU_DcdcBoostToffMaxTimeout_TypeDef;
489
490 /** DCDC Boost peak current detection maximum timeout */
491 typedef enum {
492 emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */
493 emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */
494 emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */
495 emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */
496 emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */
497 emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */
498 emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */
499 emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */
500 } EMU_DcdcBoostTonMaxTimeout_TypeDef;
501
502 /** DCDC Boost EM23 peak current setting. */
503 typedef enum {
504 emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */
505 } EMU_DcdcBoostEM23PeakCurrent_TypeDef;
506 #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */
507
508 #if defined(EMU_STATUS_VMONRDY)
509 /** VMON channels. */
510 typedef enum {
511 emuVmonChannel_AVDD,
512 emuVmonChannel_ALTAVDD,
513 emuVmonChannel_DVDD,
514 emuVmonChannel_IOVDD0,
515 #if defined(_EMU_VMONIO1CTRL_EN_MASK)
516 emuVmonChannel_IOVDD1,
517 #endif
518 #if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
519 emuVmonChannel_BUVDD,
520 #endif
521 } EMU_VmonChannel_TypeDef;
522 #endif /* EMU_STATUS_VMONRDY */
523
524 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
525 /** Bias mode configurations. */
526 typedef enum {
527 emuBiasMode_1KHz,
528 emuBiasMode_4KHz,
529 emuBiasMode_Continuous
530 } EMU_BiasMode_TypeDef;
531 #endif
532
533 #if defined(EMU_VSCALE_EM01_PRESENT)
534 /** Supported EM0/1 Voltage Scaling Levels. */
535 typedef enum {
536 /** High-performance voltage level. HF clock can be set to any frequency. */
537 emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
538 /** Low-power optimized voltage level. HF clock must be limited
539 to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage.
540 EM0/1 voltage scaling is applied when core clock frequency is
541 changed from @ref cmu or when calling @ref EMU_EM01Init() when HF
542 clock is already below the limit. */
543 #if defined(_SILICON_LABS_32B_SERIES_2)
544 /** Minimum VSCALE level in EM0/1 is VSCALE1. */
545 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1,
546 #else
547 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0,
548 #endif
549 } EMU_VScaleEM01_TypeDef;
550 #endif
551
552 #if defined(EMU_VSCALE_PRESENT)
553 /** Supported EM2/3 Voltage Scaling Levels. */
554 typedef enum {
555 /** Fast-wakeup voltage level. */
556 emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
557 /** Low-power optimized voltage level. Using this voltage level in EM2 and 3
558 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled
559 up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */
560 emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
561 } EMU_VScaleEM23_TypeDef;
562 #endif
563
564 #if defined(_EMU_CTRL_EM4HVSCALE_MASK)
565 /** Supported EM4H Voltage Scaling Levels */
566 typedef enum {
567 /** Fast-wakeup voltage level. */
568 emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
569 /** Low-power optimized voltage level. Using this voltage level in EM4H
570 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled
571 up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */
572 emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
573 } EMU_VScaleEM4H_TypeDef;
574 #endif
575
576 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
577 /** Peripheral EM2 and 3 retention control. */
578 typedef enum {
579 #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
580 emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */
581 #endif
582 #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
583 emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */
584 #endif
585 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
586 emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */
587 #endif
588 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
589 emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */
590 #endif
591 #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
592 emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */
593 #endif
594 #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
595 emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */
596 #endif
597 #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
598 emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */
599 #endif
600 #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
601 emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */
602 #endif
603 #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
604 emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */
605 #endif
606 emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */
607 #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
608 emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */
609 #endif
610 emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */
611 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
612 emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */
613 #endif
614 emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */
615 emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */
616 emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */
617 #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
618 emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */
619 #endif
620 #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK)
621 emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */
622 #endif
623 #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
624 emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */
625 #endif
626 emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */
627 emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */
628 emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */
629 #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
630 emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */
631 emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */
632 #endif
633 emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */
634
635 emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
636 | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
637 | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
638 | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
639 | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */
640 emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
641 #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
642 | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
643 #endif
644 #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK)
645 | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK
646 #endif
647 #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
648 | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
649 #endif
650 | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
651 #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
652 | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK
653 #endif
654 #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
655 | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK
656 #endif
657 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
658 | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK
659 #endif
660 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
661 | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK
662 #endif
663 #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
664 | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK
665 #endif
666 #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
667 | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK
668 #endif
669 #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
670 | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK
671 #endif
672 #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
673 | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK
674 #endif
675 #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
676 | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK
677 #endif
678 #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
679 | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
680 | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
681 #endif
682 #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
683 | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */
684 #endif
685 | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,
686 emuPeripheralRetention_ALL = emuPeripheralRetention_D1
687 | emuPeripheralRetention_D2
688 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
689 | emuPeripheralRetention_WDOG1
690 #endif
691 | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */
692 } EMU_PeripheralRetention_TypeDef;
693 #endif
694
695 #if defined(_EMU_TEMP_TEMPAVG_MASK)
696 /** Number of samples to use for temperature averaging. */
697 typedef enum {
698 /** 16 samples used for temperature averaging. */
699 emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16,
700 /** 64 samples used for temperature averaging. */
701 emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64,
702 } EMU_TempAvgNum_TypeDef;
703 #endif
704
705 /*******************************************************************************
706 ******************************* STRUCTS ***********************************
707 ******************************************************************************/
708
709 #if defined(EMU_VSCALE_EM01_PRESENT)
710 /** EM0 and 1 initialization structure. Voltage scaling is applied when
711 the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance
712 is always enabled. */
713 typedef struct {
714 bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */
715 } EMU_EM01Init_TypeDef;
716
717 /** Default initialization of EM0 and 1 configuration. */
718 #define EMU_EM01INIT_DEFAULT \
719 { \
720 false /* Do not scale down in EM0/1.*/ \
721 }
722 #endif
723
724 /** EM2 and 3 initialization structure. */
725 typedef struct {
726 bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */
727 #if defined(EMU_VSCALE_PRESENT)
728 EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */
729 #endif
730 } EMU_EM23Init_TypeDef;
731
732 /** Default initialization of EM2 and 3 configuration. */
733 #if defined(EMU_VSCALE_PRESENT)
734 #define EMU_EM23INIT_DEFAULT \
735 { \
736 false, /* Reduced voltage regulator drive strength in EM2/3.*/ \
737 emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \
738 }
739 #else
740 #define EMU_EM23INIT_DEFAULT \
741 { \
742 false, /* Reduced voltage regulator drive strength in EM2/3.*/ \
743 }
744 #endif
745
746 #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
747 /** EM4 initialization structure. */
748 typedef struct {
749 #if defined(_EMU_EM4CONF_MASK)
750 /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */
751 bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */
752 bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */
753 EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */
754 bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */
755 bool vreg; /**< Enable EM4 voltage regulator. */
756 #elif defined(_EMU_EM4CTRL_MASK)
757 /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */
758 bool retainLfxo; /**< Disable LFXO upon EM4 entry. */
759 bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */
760 bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */
761 EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */
762 EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */
763 #endif
764 #if defined(_EMU_CTRL_EM4HVSCALE_MASK)
765 EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */
766 #endif
767 } EMU_EM4Init_TypeDef;
768 #endif
769
770 #if defined(_EMU_EM4CONF_MASK)
771 /** Default initialization of EM4 configuration (Series 0). */
772 #define EMU_EM4INIT_DEFAULT \
773 { \
774 false, /* Do not lock configuration after it's been set. */ \
775 false, /* No reset will be asserted due to BOD in EM4. */ \
776 emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \
777 true, /* Wake up on EM4 BURTC interrupt. */ \
778 true, /* Enable VREG. */ \
779 }
780
781 #elif defined(_EMU_CTRL_EM4HVSCALE_MASK)
782 /** Default initialization of EM4 configuration (Series 1 with VSCALE). */
783 #define EMU_EM4INIT_DEFAULT \
784 { \
785 false, /* Retain LFXO configuration upon EM4 entry. */ \
786 false, /* Retain LFRCO configuration upon EM4 entry. */ \
787 false, /* Retain ULFRCO configuration upon EM4 entry. */ \
788 emuEM4Shutoff, /* Use EM4 shutoff state. */ \
789 emuPinRetentionDisable, /* Do not retain pins in EM4. */ \
790 emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \
791 }
792
793 #elif defined(_EMU_EM4CTRL_MASK)
794 /** Default initialization of EM4 configuration (Series 1 without VSCALE). */
795 #define EMU_EM4INIT_DEFAULT \
796 { \
797 false, /* Retain LFXO configuration upon EM4 entry. */ \
798 false, /* Retain LFRCO configuration upon EM4 entry. */ \
799 false, /* Retain ULFRCO configuration upon EM4 entry. */ \
800 emuEM4Shutoff, /* Use EM4 shutoff state. */ \
801 emuPinRetentionDisable, /* Do not retain pins in EM4. */ \
802 }
803 #endif
804
805 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
806 /** Backup Power Domain Initialization structure. */
807 typedef struct {
808 /* Backup Power Domain power configuration. */
809
810 /** Voltage probe select, selects ADC voltage. */
811 EMU_Probe_TypeDef probe;
812 /** Enable BOD calibration mode. */
813 bool bodCal;
814 /** Enable BU_STAT status pin for active BU mode. */
815 bool statusPinEnable;
816
817 /* Backup Power Domain connection configuration. */
818 /** Power domain resistor. */
819 EMU_Resistor_TypeDef resistor;
820 /** BU_VOUT strong enable. */
821 bool voutStrong;
822 /** BU_VOUT medium enable. */
823 bool voutMed;
824 /** BU_VOUT weak enable. */
825 bool voutWeak;
826 /** Power connection, when not in Backup Mode. */
827 EMU_Power_TypeDef inactivePower;
828 /** Power connection, when in Backup Mode. */
829 EMU_Power_TypeDef activePower;
830 /** Enable backup power domain, and release reset, enable BU_VIN pin. */
831 bool enable;
832 } EMU_BUPDInit_TypeDef;
833
834 /** Default Backup Power Domain configuration. */
835 #define EMU_BUPDINIT_DEFAULT \
836 { \
837 emuProbe_Disable, /* Do not enable voltage probe. */ \
838 false, /* Disable BOD calibration mode. */ \
839 false, /* Disable BU_STAT pin for backup mode indication. */ \
840 \
841 emuRes_Res0, /* RES0 series resistance between main and backup power. */ \
842 false, /* Do not enable strong switch. */ \
843 false, /* Do not enable medium switch. */ \
844 false, /* Do not enable weak switch. */ \
845 \
846 emuPower_None, /* No connection between main and backup power. (inactive mode) */ \
847 emuPower_None, /* No connection between main and backup power. (active mode) */ \
848 true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \
849 }
850 #endif
851
852 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1)
853 /** Backup Power Domain Initialization structure. */
854 typedef struct {
855 bool disMaxComp; /**< Disable MAIN-BU Comparator. */
856 EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */
857 EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */
858 EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */
859 EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */
860 bool buVinProbeEn; /**< Enable BU_VIN probing. */
861 bool staEn; /**< Enable backup mode status export. */
862 bool enable; /**< Enable backup power domain. */
863 } EMU_BUInit_TypeDef;
864
865 /** Default Backup Power Domain configuration. */
866 #define EMU_BUINIT_DEFAULT \
867 { \
868 false, /* MAIN-BU Comparator is not disabled */ \
869 emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \
870 emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \
871 emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \
872 emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \
873 false, /* BU_VIN probe is disabled */ \
874 false, /* Status export is disabled */ \
875 true /* Enable backup mode */ \
876 }
877 #endif
878
879 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
880 /** DCDC Boost regulator initialization structure. */
881 typedef struct {
882 EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */
883 bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */
884 EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */
885 EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */
886 EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */
887 EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */
888 } EMU_DCDCBoostInit_TypeDef;
889
890 /** Default DCDC Boost initialization. */
891 #define EMU_DCDCBOOSTINIT_DEFAULT \
892 { \
893 emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
894 true, /**< disable DCDC boost mode with BOOST_EN=0 */ \
895 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
896 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
897 emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \
898 emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \
899 }
900 #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */
901
902 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
903 /** DCDC regulator initialization structure. */
904 typedef struct {
905 EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */
906 EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */
907 EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */
908 #if defined(_DCDC_CTRL_DCMONLYEN_MASK)
909 bool dcmOnlyEn; /**< DCM only mode enable. */
910 #endif
911 EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */
912 EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */
913 EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */
914 EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */
915 } EMU_DCDCInit_TypeDef;
916
917 /** Default DCDC Buck initialization. */
918 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
919 #define EMU_DCDCINIT_DEFAULT \
920 { \
921 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
922 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
923 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
924 true, /**< Enable DCM only mode. */ \
925 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
926 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
927 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
928 emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \
929 }
930 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) \
931 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) \
932 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5) \
933 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6) \
934 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7) \
935 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)
936 #define EMU_DCDCINIT_DEFAULT \
937 { \
938 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
939 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
940 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
941 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
942 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
943 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
944 emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \
945 }
946 #endif
947 #endif /* SERIES2_DCDC_BUCK_PRESENT */
948
949 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
950 /** DCDC initialization structure. */
951 typedef struct {
952 EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration.
953 @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */
954 EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */
955 uint16_t mVout; /**< Target output voltage (mV). */
956 uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA).
957 This estimate is also used for EM1 optimization;
958 if EM1 current is expected to be higher than EM0,
959 then this parameter should hold the higher EM1 current. */
960 uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA).
961 This estimate is also used for EM3 and 4 optimization;
962 if EM3 or 4 current is expected to be higher than EM2,
963 then this parameter should hold the higher EM3 or 4 current. */
964 uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA).
965 This can be set to the maximum for the power source,
966 for example the maximum for a battery. */
967 EMU_DcdcAnaPeripheralPower_TypeDef
968 anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */
969 EMU_DcdcLnReverseCurrentControl_TypeDef
970 reverseCurrentControl; /**< Low-noise reverse current control.
971 NOTE: this parameter uses special encoding:
972 >= 0 is forced CCM mode where the parameter is used as the
973 reverse current threshold in mA.
974 -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */
975 EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */
976 } EMU_DCDCInit_TypeDef;
977
978 /** Default DCDC initialization. */
979 #if defined(_EFM_DEVICE)
980 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
981 #define EMU_DCDCINIT_DEFAULT \
982 { \
983 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
984 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
985 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
986 5, /* Nominal EM0/1 load current of less than 5mA. */ \
987 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
988 200, /* Maximum average current of 200mA
989 (assume strong battery or other power source). */ \
990 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
991 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
992 emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \
993 }
994 #elif defined(WGM160PX22KGA2)
995 #define EMU_DCDCINIT_DEFAULT \
996 { \
997 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
998 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
999 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1000 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1001 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1002 200, /* Maximum average current of 200mA
1003 (assume strong battery or other power source). */ \
1004 emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \
1005 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1006 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1007 }
1008 #else
1009 #define EMU_DCDCINIT_DEFAULT \
1010 { \
1011 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1012 emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \
1013 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1014 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1015 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1016 200, /* Maximum average current of 200mA
1017 (assume strong battery or other power source). */ \
1018 emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \
1019 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1020 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1021 }
1022 #endif
1023
1024 #else /* EFR32 device. */
1025 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1026 #define EMU_DCDCINIT_DEFAULT \
1027 { \
1028 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1029 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1030 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1031 15, /* Nominal EM0/1 load current of less than 15mA. */ \
1032 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1033 200, /* Maximum average current of 200mA
1034 (assume strong battery or other power source). */ \
1035 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1036 160, /* Maximum reverse current of 160mA. */ \
1037 emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \
1038 }
1039 #else
1040 #define EMU_DCDCINIT_DEFAULT \
1041 { \
1042 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1043 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1044 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1045 15, /* Nominal EM0/1 load current of less than 15mA. */ \
1046 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1047 200, /* Maximum average current of 200mA
1048 (assume strong battery or other power source). */ \
1049 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1050 160, /* Maximum reverse current of 160mA. */ \
1051 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1052 }
1053 #endif
1054 #endif
1055 #endif
1056
1057 #if defined(EMU_STATUS_VMONRDY)
1058 /** VMON initialization structure. */
1059 typedef struct {
1060 EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */
1061 int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */
1062 bool riseWakeup; /**< Wake up from EM4H on rising edge. */
1063 bool fallWakeup; /**< Wake up from EM4H on falling edge. */
1064 bool enable; /**< Enable VMON channel. */
1065 bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */
1066 } EMU_VmonInit_TypeDef;
1067
1068 /** Default VMON initialization structure. */
1069 #define EMU_VMONINIT_DEFAULT \
1070 { \
1071 emuVmonChannel_AVDD, /* AVDD VMON channel. */ \
1072 3200, /* 3.2 V threshold. */ \
1073 false, /* Do not wake from EM4H on rising edge. */ \
1074 false, /* Do not wake from EM4H on falling edge. */ \
1075 true, /* Enable VMON channel. */ \
1076 false /* Do not disable IO0 retention */ \
1077 }
1078
1079 /** VMON Hysteresis initialization structure. */
1080 typedef struct {
1081 EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */
1082 int riseThreshold; /**< Rising threshold (mV). */
1083 int fallThreshold; /**< Falling threshold (mV). */
1084 bool riseWakeup; /**< Wake up from EM4H on rising edge. */
1085 bool fallWakeup; /**< Wake up from EM4H on falling edge. */
1086 bool enable; /**< Enable VMON channel. */
1087 } EMU_VmonHystInit_TypeDef;
1088
1089 /** Default VMON Hysteresis initialization structure. */
1090 #define EMU_VMONHYSTINIT_DEFAULT \
1091 { \
1092 emuVmonChannel_AVDD, /* AVDD VMON channel. */ \
1093 3200, /* 3.2 V rise threshold. */ \
1094 3200, /* 3.2 V fall threshold. */ \
1095 false, /* Do not wake from EM4H on rising edge. */ \
1096 false, /* Do not wake from EM4H on falling edge. */ \
1097 true /* Enable VMON channel. */ \
1098 }
1099 #endif /* EMU_STATUS_VMONRDY */
1100
1101 /*******************************************************************************
1102 ***************************** PROTOTYPES **********************************
1103 ******************************************************************************/
1104
1105 #if defined(EMU_VSCALE_EM01_PRESENT)
1106 void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init);
1107 #endif
1108 void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init);
1109 void EMU_EM23PresleepHook(void);
1110 void EMU_EM23PostsleepHook(void);
1111 void EMU_EFPEM23PresleepHook(void);
1112 void EMU_EFPEM23PostsleepHook(void);
1113 void EMU_EnterEM2(bool restore);
1114 void EMU_EnterEM3(bool restore);
1115 void EMU_Save(void);
1116 void EMU_Restore(void);
1117 #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
1118 void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
1119 #endif
1120 void EMU_EM4PresleepHook(void);
1121 void EMU_EFPEM4PresleepHook(void);
1122 void EMU_EnterEM4(void);
1123 void EMU_EnterEM4Wait(void);
1124 #if defined(_EMU_EM4CTRL_MASK)
1125 void EMU_EnterEM4H(void);
1126 void EMU_EnterEM4S(void);
1127 #endif
1128 void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1;
1129 void EMU_RamPowerDown(uint32_t start, uint32_t end);
1130 void EMU_RamPowerUp(void);
1131 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
1132 void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable);
1133 #endif
1134 void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1;
1135 #if defined(EMU_VSCALE_EM01_PRESENT)
1136 #if defined(_SILICON_LABS_32B_SERIES_2)
1137 void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage);
1138 #endif
1139 void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
1140 void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
1141 #endif
1142 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
1143 void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
1144 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
1145 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
1146 #endif
1147 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1)
1148 void EMU_BUInit(const EMU_BUInit_TypeDef *buInit);
1149 #endif
1150 #if defined(_EMU_BUCTRL_DISMAXCOMP_MASK)
1151 void EMU_BUDisMaxCompSet(bool disableMainBuComparator);
1152 #endif
1153 #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK)
1154 void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon);
1155 #endif
1156 #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK)
1157 void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon);
1158 #endif
1159 #if defined(_EMU_BUCTRL_PWRRES_MASK)
1160 void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes);
1161 #endif
1162 #if defined(_EMU_BUCTRL_VOUTRES_MASK)
1163 void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel);
1164 #endif
1165 #if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK)
1166 void EMU_BUBuVinProbeEnSet(bool enable);
1167 #endif
1168 #if defined(_EMU_BUCTRL_STATEN_MASK)
1169 void EMU_BUStatEnSet(bool enable);
1170 #endif
1171 #if defined(_EMU_BUCTRL_EN_MASK)
1172 void EMU_BUEnableSet(bool enable);
1173 #endif
1174
1175 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
1176 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
1177 #endif
1178
1179 #if (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
1180 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT))
1181 sl_status_t EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
1182 #endif
1183
1184 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
1185 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
1186 void EMU_DCDCUpdatedHook(void);
1187 #endif
1188
1189 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
1190 bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit);
1191 void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01);
1192 void EMU_BoostExternalShutdownEnable(bool enable);
1193 #endif
1194
1195 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \
1196 || defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
1197 bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit);
1198 bool EMU_DCDCPowerOff(void);
1199 #endif
1200
1201 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
1202 void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01);
1203 #if defined(_DCDC_PFMXCTRL_IPKVAL_MASK)
1204 void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value);
1205 #endif
1206 #if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK)
1207 void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value);
1208 #endif
1209 #endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */
1210
1211 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
1212 #if defined(EMU_DCDCCTRL_DCDCMODEEM23)
1213 void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23);
1214 #endif
1215 void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet);
1216 bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
1217 void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA);
1218 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
1219 #endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */
1220
1221 #if defined(EMU_STATUS_VMONRDY)
1222 void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit);
1223 void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit);
1224 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
1225 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
1226 #endif
1227 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1228 void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
1229 #endif
1230 #if defined(_EMU_TEMP_TEMP_MASK)
1231 float EMU_TemperatureGet(void);
1232 #endif
1233 #if defined(EMU_CTRL_EFPDIRECTMODEEN)
1234 void EMU_EFPDirectModeEnable(bool enable);
1235 #endif
1236 #if defined(EMU_CTRL_EFPDRVDECOUPLE)
1237 void EMU_EFPDriveDecoupleSet(bool enable);
1238 #endif
1239 #if defined(EMU_CTRL_EFPDRVDVDD)
1240 void EMU_EFPDriveDvddSet(bool enable);
1241 #endif
1242
1243 #if defined(_DCDC_CTRL_MASK)
1244 /***************************************************************************//**
1245 * @brief
1246 * Lock DCDC registers in order to protect them against unintended
1247 * modification.
1248 ******************************************************************************/
EMU_DCDCLock(void)1249 __STATIC_INLINE void EMU_DCDCLock(void)
1250 {
1251 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY;
1252 }
1253 #endif
1254
1255 #if defined(_DCDC_CTRL_MASK)
1256 /***************************************************************************//**
1257 * @brief
1258 * Unlock the DCDC so that writing to locked registers again is possible.
1259 ******************************************************************************/
EMU_DCDCUnlock(void)1260 __STATIC_INLINE void EMU_DCDCUnlock(void)
1261 {
1262 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY;
1263 }
1264 #endif
1265
1266 #if defined(_DCDC_SYNCBUSY_MASK)
1267 /***************************************************************************//**
1268 * @brief
1269 * Wait for the DCDC to complete all synchronization of register changes.
1270 *
1271 * @param[in] mask
1272 * A bitmask corresponding to SYNCBUSY register defined bits indicating
1273 * registers that must complete any ongoing synchronization.
1274 ******************************************************************************/
EMU_DCDCSync(uint32_t mask)1275 __STATIC_INLINE void EMU_DCDCSync(uint32_t mask)
1276 {
1277 while (0UL != (DCDC->SYNCBUSY & mask)) {
1278 /* Wait for previous synchronization to finish */
1279 }
1280 }
1281 #endif
1282
1283 #if defined(_SILICON_LABS_32B_SERIES_1)
1284 /***************************************************************************//**
1285 * @brief
1286 * Check status of the internal LDO regulator.
1287 *
1288 * @return
1289 * Return true if the regulator is on, false if regulator is off.
1290 ******************************************************************************/
EMU_LDOStatusGet(void)1291 __STATIC_INLINE bool EMU_LDOStatusGet(void)
1292 {
1293 if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) {
1294 return true;
1295 } else {
1296 return false;
1297 }
1298 }
1299 #endif
1300
1301 /***************************************************************************//**
1302 * @brief
1303 * Enter energy mode 1 (EM1).
1304 *
1305 * @note
1306 * This function is incompatible with the Power Manager module. When the
1307 * Power Manager module is present, it must be the one deciding at which
1308 * EM level the device sleeps to ensure the application properly works. Using
1309 * both at the same time could lead to undefined behavior in the application.
1310 ******************************************************************************/
EMU_EnterEM1(void)1311 __STATIC_INLINE void EMU_EnterEM1(void)
1312 {
1313 /* Enter sleep mode. */
1314 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
1315 __WFI();
1316 }
1317
1318 #if defined(EMU_VSCALE_EM01_PRESENT)
1319 /***************************************************************************//**
1320 * @brief
1321 * Wait for voltage scaling to complete.
1322 ******************************************************************************/
EMU_VScaleWait(void)1323 __STATIC_INLINE void EMU_VScaleWait(void)
1324 {
1325 #if defined(_SILICON_LABS_32B_SERIES_1)
1326 if (EMU_LDOStatusGet() == false) {
1327 /* Skip waiting if the LDO regulator is turned off. */
1328 return;
1329 }
1330 #endif
1331
1332 while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) {
1333 }
1334 }
1335 #endif
1336
1337 #if defined(EMU_VSCALE_EM01_PRESENT)
1338 /***************************************************************************//**
1339 * @brief
1340 * Get current voltage scaling level.
1341 *
1342 * @return
1343 * Current voltage scaling level.
1344 ******************************************************************************/
EMU_VScaleGet(void)1345 __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void)
1346 {
1347 EMU_VScaleWait();
1348 return (EMU_VScaleEM01_TypeDef)((uint32_t)
1349 ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
1350 >> _EMU_STATUS_VSCALE_SHIFT));
1351 }
1352 #endif
1353
1354 #if defined(_EMU_STATUS_VMONRDY_MASK)
1355 /***************************************************************************//**
1356 * @brief
1357 * Get the status of the voltage monitor (VMON).
1358 *
1359 * @return
1360 * Status of the VMON. True if all the enabled channels are ready, false if
1361 * one or more of the enabled channels are not ready.
1362 ******************************************************************************/
EMU_VmonStatusGet(void)1363 __STATIC_INLINE bool EMU_VmonStatusGet(void)
1364 {
1365 return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U;
1366 }
1367 #endif /* _EMU_STATUS_VMONRDY_MASK */
1368
1369 #if defined(_EMU_IF_MASK)
1370 /***************************************************************************//**
1371 * @brief
1372 * Clear one or more pending EMU interrupts.
1373 *
1374 * @param[in] flags
1375 * Pending EMU interrupt sources to clear. Use one or more valid
1376 * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn).
1377 ******************************************************************************/
EMU_IntClear(uint32_t flags)1378 __STATIC_INLINE void EMU_IntClear(uint32_t flags)
1379 {
1380 #if defined(EMU_HAS_SET_CLEAR)
1381 EMU->IF_CLR = flags;
1382 #else
1383 EMU->IFC = flags;
1384 #endif
1385 }
1386
1387 /***************************************************************************//**
1388 * @brief
1389 * Disable one or more EMU interrupts.
1390 *
1391 * @param[in] flags
1392 * EMU interrupt sources to disable. Use one or more valid
1393 * interrupt flags for the EMU module (EMU_IEN_nnn).
1394 ******************************************************************************/
EMU_IntDisable(uint32_t flags)1395 __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
1396 {
1397 #if defined(EMU_HAS_SET_CLEAR)
1398 EMU->IEN_CLR = flags;
1399 #else
1400 EMU->IEN &= ~flags;
1401 #endif
1402 }
1403
1404 /***************************************************************************//**
1405 * @brief
1406 * Enable one or more EMU interrupts.
1407 *
1408 * @note
1409 * Depending on the use, a pending interrupt may already be set prior to
1410 * enabling the interrupt. To ignore a pending interrupt, consider using
1411 * @ref EMU_IntClear() prior to enabling the interrupt.
1412 *
1413 * @param[in] flags
1414 * EMU interrupt sources to enable. Use one or more valid
1415 * interrupt flags for the EMU module (EMU_IEN_nnn).
1416 ******************************************************************************/
EMU_IntEnable(uint32_t flags)1417 __STATIC_INLINE void EMU_IntEnable(uint32_t flags)
1418 {
1419 #if defined(EMU_HAS_SET_CLEAR)
1420 EMU->IEN_SET = flags;
1421 #else
1422 EMU->IEN |= flags;
1423 #endif
1424 }
1425
1426 #if defined(EMU_CTRL_EFPDRVDVDD)
1427 /***************************************************************************//**
1428 * @brief
1429 * Disable one or more EFP interrupts.
1430 *
1431 * @param[in] flags
1432 * EFP interrupt sources to disable. Use one or more valid
1433 * interrupt flags for the EFP module (EFPIENnnn).
1434 ******************************************************************************/
EMU_EFPIntDisable(uint32_t flags)1435 __STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags)
1436 {
1437 EMU->EFPIEN_CLR = flags;
1438 }
1439
1440 /***************************************************************************//**
1441 * @brief
1442 * Enable one or more EFP interrupts.
1443 *
1444 * @param[in] flags
1445 * EFP interrupt sources to enable. Use one or more valid
1446 * interrupt flags for the EFP module (EFPIENnnn).
1447 ******************************************************************************/
EMU_EFPIntEnable(uint32_t flags)1448 __STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags)
1449 {
1450 EMU->EFPIEN_SET = flags;
1451 }
1452
1453 /***************************************************************************//**
1454 * @brief
1455 * Get pending EMU EFP interrupt flags.
1456 *
1457 * @note
1458 * Event bits are not cleared by the use of this function.
1459 *
1460 * @return
1461 * EMU EFP interrupt sources pending. .
1462 ******************************************************************************/
EMU_EFPIntGet(void)1463 __STATIC_INLINE uint32_t EMU_EFPIntGet(void)
1464 {
1465 return EMU->EFPIF;
1466 }
1467
1468 /***************************************************************************//**
1469 * @brief
1470 * Get enabled and pending EMU EFP interrupt flags.
1471 * Useful for handling more interrupt sources in the same interrupt handler.
1472 *
1473 * @note
1474 * Interrupt flags are not cleared by the use of this function.
1475 *
1476 * @return
1477 * Pending and enabled EMU EFP interrupt sources
1478 * Return value is the bitwise AND of
1479 * - the enabled interrupt sources in EMU_EFPIEN and
1480 * - the pending interrupt flags EMU_EFPIF.
1481 ******************************************************************************/
EMU_EFPIntGetEnabled(void)1482 __STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void)
1483 {
1484 uint32_t ien;
1485
1486 ien = EMU->EFPIEN;
1487 return EMU->EFPIF & ien;
1488 }
1489
1490 /***************************************************************************//**
1491 * @brief
1492 * Set one or more pending EMU EFP interrupts.
1493 *
1494 * @param[in] flags
1495 * EMU EFP interrupt sources to set to pending. Use one or more valid
1496 * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn).
1497 ******************************************************************************/
EMU_EFPIntSet(uint32_t flags)1498 __STATIC_INLINE void EMU_EFPIntSet(uint32_t flags)
1499 {
1500 EMU->EFPIF_SET = flags;
1501 }
1502
1503 /***************************************************************************//**
1504 * @brief
1505 * Clear one or more pending EMU EFP interrupts.
1506 *
1507 * @param[in] flags
1508 * Pending EMU EFP interrupt sources to clear. Use one or more valid
1509 * interrupt flags for the EMU EFP module.
1510 ******************************************************************************/
EMU_EFPIntClear(uint32_t flags)1511 __STATIC_INLINE void EMU_EFPIntClear(uint32_t flags)
1512 {
1513 EMU->EFPIF_CLR = flags;
1514 }
1515 #endif
1516
1517 /***************************************************************************//**
1518 * @brief
1519 * Get pending EMU interrupt flags.
1520 *
1521 * @note
1522 * Event bits are not cleared by the use of this function.
1523 *
1524 * @return
1525 * EMU interrupt sources pending. Returns one or more valid
1526 * interrupt flags for the EMU module (EMU_IF_nnn).
1527 ******************************************************************************/
EMU_IntGet(void)1528 __STATIC_INLINE uint32_t EMU_IntGet(void)
1529 {
1530 return EMU->IF;
1531 }
1532
1533 /***************************************************************************//**
1534 * @brief
1535 * Get enabled and pending EMU interrupt flags.
1536 * Useful for handling more interrupt sources in the same interrupt handler.
1537 *
1538 * @note
1539 * Interrupt flags are not cleared by the use of this function.
1540 *
1541 * @return
1542 * Pending and enabled EMU interrupt sources
1543 * Return value is the bitwise AND of
1544 * - the enabled interrupt sources in EMU_IEN and
1545 * - the pending interrupt flags EMU_IF.
1546 ******************************************************************************/
EMU_IntGetEnabled(void)1547 __STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
1548 {
1549 uint32_t ien;
1550
1551 ien = EMU->IEN;
1552 return EMU->IF & ien;
1553 }
1554
1555 /***************************************************************************//**
1556 * @brief
1557 * Set one or more pending EMU interrupts.
1558 *
1559 * @param[in] flags
1560 * EMU interrupt sources to set to pending. Use one or more valid
1561 * interrupt flags for the EMU module (EMU_IFS_nnn).
1562 ******************************************************************************/
EMU_IntSet(uint32_t flags)1563 __STATIC_INLINE void EMU_IntSet(uint32_t flags)
1564 {
1565 #if defined(EMU_HAS_SET_CLEAR)
1566 EMU->IF_SET = flags;
1567 #else
1568 EMU->IFS = flags;
1569 #endif
1570 }
1571 #endif /* _EMU_IF_MASK */
1572
1573 #if defined(_EMU_EM4CONF_LOCKCONF_MASK)
1574 /***************************************************************************//**
1575 * @brief
1576 * Enable or disable EM4 lock configuration.
1577 * @param[in] enable
1578 * If true, locks down EM4 configuration.
1579 ******************************************************************************/
EMU_EM4Lock(bool enable)1580 __STATIC_INLINE void EMU_EM4Lock(bool enable)
1581 {
1582 BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
1583 }
1584 #endif
1585
1586 #if defined(_EMU_STATUS_BURDY_MASK)
1587 /***************************************************************************//**
1588 * @brief
1589 * Halts until backup power functionality is ready.
1590 ******************************************************************************/
EMU_BUReady(void)1591 __STATIC_INLINE void EMU_BUReady(void)
1592 {
1593 while (!(EMU->STATUS & EMU_STATUS_BURDY))
1594 ;
1595 }
1596 #endif
1597
1598 #if defined(_EMU_ROUTE_BUVINPEN_MASK)
1599 /***************************************************************************//**
1600 * @brief
1601 * Disable BU_VIN support.
1602 * @param[in] enable
1603 * If true, enables BU_VIN input pin support, if false disables it.
1604 ******************************************************************************/
EMU_BUPinEnable(bool enable)1605 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
1606 {
1607 BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
1608 }
1609 #endif
1610
1611 /***************************************************************************//**
1612 * @brief
1613 * Lock EMU registers in order to protect them against unintended
1614 * modification.
1615 *
1616 * @note
1617 * If locking EMU registers, they must be unlocked prior to using any
1618 * EMU API functions modifying EMU registers, excluding interrupt control
1619 * and regulator control if the architecture has a EMU_PWRCTRL register.
1620 * An exception to this is the energy mode entering API (EMU_EnterEMn()),
1621 * which can be used when the EMU registers are locked.
1622 ******************************************************************************/
EMU_Lock(void)1623 __STATIC_INLINE void EMU_Lock(void)
1624 {
1625 EMU->LOCK = 0x0;
1626 }
1627
1628 /***************************************************************************//**
1629 * @brief
1630 * Unlock the EMU so that writing to locked registers again is possible.
1631 ******************************************************************************/
EMU_Unlock(void)1632 __STATIC_INLINE void EMU_Unlock(void)
1633 {
1634 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
1635 }
1636
1637 #if defined(_EMU_PWRLOCK_MASK)
1638 /***************************************************************************//**
1639 * @brief
1640 * Lock the EMU regulator control registers in order to protect against
1641 * unintended modification.
1642 ******************************************************************************/
EMU_PowerLock(void)1643 __STATIC_INLINE void EMU_PowerLock(void)
1644 {
1645 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
1646 }
1647
1648 /***************************************************************************//**
1649 * @brief
1650 * Unlock the EMU power control registers so that writing to
1651 * locked registers again is possible.
1652 ******************************************************************************/
EMU_PowerUnlock(void)1653 __STATIC_INLINE void EMU_PowerUnlock(void)
1654 {
1655 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
1656 }
1657 #endif
1658
1659 #if defined(_EMU_CTRL_EM2BLOCK_MASK)
1660 /***************************************************************************//**
1661 * @brief
1662 * Block entering EM2 or higher number energy modes.
1663 ******************************************************************************/
EMU_EM2Block(void)1664 __STATIC_INLINE void EMU_EM2Block(void)
1665 {
1666 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
1667 }
1668
1669 /***************************************************************************//**
1670 * @brief
1671 * Unblock entering EM2 or higher number energy modes.
1672 ******************************************************************************/
EMU_EM2UnBlock(void)1673 __STATIC_INLINE void EMU_EM2UnBlock(void)
1674 {
1675 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
1676 }
1677 #endif
1678
1679 #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
1680 /***************************************************************************//**
1681 * @brief
1682 * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained
1683 * through EM4 entry and wakeup. The pin state is released by calling this function.
1684 * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset),
1685 * and when initialization is done, this function can release pins and return control
1686 * to the peripherals or GPIO.
1687 ******************************************************************************/
EMU_UnlatchPinRetention(void)1688 __STATIC_INLINE void EMU_UnlatchPinRetention(void)
1689 {
1690 EMU->CMD = EMU_CMD_EM4UNLATCH;
1691 }
1692 #endif
1693
1694 #if defined(_EMU_TEMP_TEMP_MASK)
1695 /** Zero degrees Celcius in Kelvin */
1696 #define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f)
1697 /***************************************************************************//**
1698 * @brief
1699 * Temperature measurement ready status
1700 *
1701 * @return
1702 * True if temperature measurement is ready
1703 ******************************************************************************/
EMU_TemperatureReady(void)1704 __STATIC_INLINE bool EMU_TemperatureReady(void)
1705 {
1706 #if defined(EMU_STATUS_FIRSTTEMPDONE)
1707 return (0UL != (EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE));
1708 #else
1709 return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u);
1710 #endif
1711 }
1712
1713 #if defined(_EMU_TEMP_TEMPAVG_MASK)
1714 /***************************************************************************//**
1715 * @brief
1716 * Get averaged temperature in degrees Celsius.
1717 *
1718 * @note
1719 * An averaged temperature measurement must first be requested by calling
1720 * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag
1721 * to go high.
1722 *
1723 * @return
1724 * Averaged temperature
1725 ******************************************************************************/
EMU_TemperatureAvgGet(void)1726 __STATIC_INLINE float EMU_TemperatureAvgGet(void)
1727 {
1728 uint32_t tmp = ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK)
1729 >> _EMU_TEMP_TEMPAVG_SHIFT);
1730 return (float)tmp / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN;
1731 }
1732
1733 /***************************************************************************//**
1734 * @brief
1735 * Request averaged temperature.
1736 *
1737 * @note
1738 * EMU must be unlocked by calling @ref EMU_Unlock() before this function
1739 * can be called.
1740 *
1741 * @param[in] numSamples
1742 * Number of temperature samples to average
1743 ******************************************************************************/
EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples)1744 __STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples)
1745 {
1746 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, (unsigned int)numSamples);
1747 EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT;
1748 }
1749
1750 #endif //defined(_EMU_TEMP_TEMPAVG_MASK)
1751 #endif //defined(_EMU_TEMP_TEMP_MASK)
1752
1753 /** @} (end addtogroup emu) */
1754
1755 #ifdef __cplusplus
1756 }
1757 #endif
1758
1759 #endif /* defined( EMU_PRESENT ) */
1760 #endif /* EM_EMU_H */
1761
