1 /***************************************************************************//**
2 * @file
3 * @brief Energy Management Unit (EMU) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_EMU_H
32 #define EM_EMU_H
33
34 #include "em_device.h"
35 #if defined(EMU_PRESENT)
36
37 #include <stdbool.h>
38 #include "em_bus.h"
39 #include "sl_common.h"
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /***************************************************************************//**
46 * @addtogroup emu
47 * @{
48 ******************************************************************************/
49
50 /*******************************************************************************
51 ******************************* DEFINES ***********************************
52 ******************************************************************************/
53 #if (defined(_EMU_STATUS_VSCALE_MASK) || defined(_EMU_CTRL_EM23VSCALE_MASK)) \
54 && !defined(_SILICON_LABS_GECKO_INTERNAL_SDID_200)
55 /** Voltage scaling present */
56 #define EMU_VSCALE_PRESENT
57 #if !defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
58 /** Voltage scaling for EM01 present */
59 #define EMU_VSCALE_EM01_PRESENT
60 #endif
61 #endif
62
63 #if defined(_EMU_DCDCCTRL_MASK)
64 /** DC-DC buck converter present */
65 #define EMU_SERIES1_DCDC_BUCK_PRESENT
66 #endif
67
68 #if defined(_SILICON_LABS_DCDC_FEATURE) \
69 && ((_SILICON_LABS_DCDC_FEATURE == 1) \
70 || (_SILICON_LABS_DCDC_FEATURE == 3))
71 /** DC-DC buck converter present */
72 #define EMU_SERIES2_DCDC_BUCK_PRESENT
73 #endif
74
75 #if defined(_SILICON_LABS_DCDC_FEATURE) \
76 && ((_SILICON_LABS_DCDC_FEATURE == 2) \
77 || (_SILICON_LABS_DCDC_FEATURE == 3))
78 /** DC-DC boost converter present */
79 #define EMU_SERIES2_DCDC_BOOST_PRESENT
80 #endif
81
82 /*******************************************************************************
83 ******************************** ENUMS ************************************
84 ******************************************************************************/
85
86 #if defined(_EMU_EM4CONF_OSC_MASK)
87 /** EM4 duty oscillator. */
88 typedef enum {
89 /** Select ULFRCO as duty oscillator in EM4. */
90 emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO,
91 /** Select LFXO as duty oscillator in EM4. */
92 emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO,
93 /** Select LFRCO as duty oscillator in EM4. */
94 emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO
95 } EMU_EM4Osc_TypeDef;
96 #endif
97
98 #if defined(_EMU_BUCTRL_PROBE_MASK)
99 /** Backup Power Voltage Probe types. */
100 typedef enum {
101 /** Disable voltage probe. */
102 emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE,
103 /** Connect probe to VDD_DREG. */
104 emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG,
105 /** Connect probe to BU_IN. */
106 emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN,
107 /** Connect probe to BU_OUT. */
108 emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT
109 } EMU_Probe_TypeDef;
110 #endif
111
112 #if defined(_EMU_PWRCONF_PWRRES_MASK)
113 /** Backup Power Domain resistor selection. */
114 typedef enum {
115 /** Main power and backup power connected with RES0 series resistance. */
116 emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0,
117 /** Main power and backup power connected with RES1 series resistance. */
118 emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1,
119 /** Main power and backup power connected with RES2 series resistance. */
120 emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2,
121 /** Main power and backup power connected with RES3 series resistance. */
122 emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3,
123 } EMU_Resistor_TypeDef;
124 #endif
125
126 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
127 /** Backup Power Domain power connection. */
128 typedef enum {
129 /** No connection between main and backup power. */
130 emuPower_None = EMU_BUINACT_PWRCON_NONE,
131 /** Main power and backup power connected through diode,
132 allowing current from backup to main only. */
133 emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN,
134 /** Main power and backup power connected through diode,
135 allowing current from main to backup only. */
136 emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU,
137 /** Main power and backup power connected without diode. */
138 emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE,
139 } EMU_Power_TypeDef;
140 #endif
141
142 #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK)
143 /** Backup Power Domain power connection configuration when not in backup mode selection. */
144 typedef enum {
145 /** No connection. */
146 emuBuBuInactPwrCon_None = EMU_BUCTRL_BUINACTPWRCON_NONE,
147 /** Allow power from main to backup. */
148 emuBuBuInactPwrCon_MainBu = EMU_BUCTRL_BUINACTPWRCON_MAINBU,
149 /** Allow power from backup to main. */
150 emuBuBuInactPwrCon_BuMain = EMU_BUCTRL_BUINACTPWRCON_BUMAIN,
151 /** Backup and main power are connected. */
152 emuBuBuInactPwrCon_NoDiode = EMU_BUCTRL_BUINACTPWRCON_NODIODE,
153 } EMU_BUBuInactPwrCon_TypeDef;
154 #endif
155
156 #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK)
157 /** Backup Power Domain power connection configuration in backup mode selection. */
158 typedef enum {
159 /** No connection. */
160 emuBuBuActPwrCon_None = EMU_BUCTRL_BUACTPWRCON_NONE,
161 /** Allow power from main to backup. */
162 emuBuBuActPwrCon_MainBu = EMU_BUCTRL_BUACTPWRCON_MAINBU,
163 /** Allow power from backup to main. */
164 emuBuBuActPwrCon_BuMain = EMU_BUCTRL_BUACTPWRCON_BUMAIN,
165 /** Backup and main power are connected. */
166 emuBuBuActPwrCon_NoDiode = EMU_BUCTRL_BUACTPWRCON_NODIODE,
167 } EMU_BUBuActPwrCon_TypeDef;
168 #endif
169
170 #if defined(_EMU_BUCTRL_PWRRES_MASK)
171 /** Backup Power Domain resistor selection. */
172 typedef enum {
173 /** Main power and backup power connected with RES0 series resistance. */
174 emuBuPwrRes_Res0 = EMU_BUCTRL_PWRRES_RES0,
175 /** Main power and backup power connected with RES1 series resistance. */
176 emuBuPwrRes_Res1 = EMU_BUCTRL_PWRRES_RES1,
177 /** Main power and backup power connected with RES2 series resistance. */
178 emuBuPwrRes_Res2 = EMU_BUCTRL_PWRRES_RES2,
179 /** Main power and backup power connected with RES3 series resistance. */
180 emuBuPwrRes_Res3 = EMU_BUCTRL_PWRRES_RES3,
181 } EMU_BUPwrRes_TypeDef;
182 #endif
183
184 #if defined(_EMU_BUCTRL_VOUTRES_MASK)
185 /** Resistance between backup domain power supply and BU_VOUT. */
186 typedef enum {
187 /** BU_VOUT is not connected. */
188 emuBuVoutRes_Dis = EMU_BUCTRL_VOUTRES_DIS,
189 /** Enable weak switch. */
190 emuBuVoutRes_Weak = EMU_BUCTRL_VOUTRES_WEAK,
191 /** Enable medium switch. */
192 emuBuVoutRes_Med = EMU_BUCTRL_VOUTRES_MED,
193 /** Enable strong switch. */
194 emuBuVoutRes_Strong = EMU_BUCTRL_VOUTRES_STRONG,
195 } EMU_BUVoutRes_TypeDef;
196 #endif
197
198 /** BOD threshold setting selector, active or inactive mode. */
199 typedef enum {
200 /** Configure BOD threshold for active mode. */
201 emuBODMode_Active,
202 /** Configure BOD threshold for inactive mode. */
203 emuBODMode_Inactive,
204 } EMU_BODMode_TypeDef;
205
206 /** EM4 modes. */
207 typedef enum {
208 /** EM4 Shutoff. */
209 emuEM4Shutoff = 0,
210 /** EM4 Hibernate. */
211 emuEM4Hibernate = 1,
212 } EMU_EM4State_TypeDef;
213
214 #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
215 /** EM4 Pin Retention Type. */
216 typedef enum {
217 /** No Retention: Pads enter reset state when entering EM4. */
218 emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE,
219 /** Retention through EM4: Pads enter reset state when exiting EM4. */
220 emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT,
221 /** Retention through EM4 and wakeup: call @ref EMU_UnlatchPinRetention() to
222 release pins from retention after EM4 wakeup. */
223 emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH,
224 } EMU_EM4PinRetention_TypeDef;
225 #endif
226
227 /** Power configurations. DCDC-to-DVDD is currently the only supported mode. */
228 typedef enum {
229 /** DCDC is connected to DVDD. */
230 emuPowerConfig_DcdcToDvdd,
231 } EMU_PowerConfig_TypeDef;
232
233 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
234 /** DCDC operating modes. */
235 typedef enum {
236 /** DCDC regulator bypass. */
237 emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS,
238 /** DCDC low-noise mode. */
239 emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE,
240 #if defined(_EMU_DCDCLPEM01CFG_MASK)
241 /** DCDC low-power mode. */
242 emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER,
243 #endif
244 } EMU_DcdcMode_TypeDef;
245
246 /** DCDC operating modes in EM2 or EM3. */
247 typedef enum {
248 /** DCDC mode is low power. */
249 emuDcdcModeEM23_LowPower = EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER,
250 /** DCDC mode is according to DCDCMODE field. */
251 emuDcdcModeEM23_Sw = EMU_DCDCCTRL_DCDCMODEEM23_EM23SW,
252 } EMU_DcdcModeEM23_TypeDef;
253
254 #endif
255
256 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
257 /** DCDC conduction modes. */
258 typedef enum {
259 /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization
260 features are available in this mode. */
261 emuDcdcConductionMode_ContinuousLN,
262 /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or
263 for EFR32 when its radio is not enabled. */
264 emuDcdcConductionMode_DiscontinuousLN,
265 } EMU_DcdcConductionMode_TypeDef;
266 #endif
267
268 #if defined(_EMU_PWRCTRL_MASK)
269 /** DCDC to DVDD mode analog peripheral power supply select. */
270 typedef enum {
271 /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */
272 emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD,
273 /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */
274 emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD
275 } EMU_DcdcAnaPeripheralPower_TypeDef;
276 #endif
277
278 #if defined(_EMU_DCDCMISCCTRL_MASK)
279 /** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */
280 typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef;
281
282 /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */
283 #define emuDcdcLnHighEfficiency -1
284
285 /** Default reverse current for fast transient response mode (low noise). */
286 #define emuDcdcLnFastTransient 160
287 #endif
288
289 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
290 /** DCDC Low-noise RCO band select. */
291 typedef enum {
292 /** Set RCO to 3MHz. */
293 emuDcdcLnRcoBand_3MHz = 0,
294 /** Set RCO to 4MHz. */
295 emuDcdcLnRcoBand_4MHz = 1,
296 /** Set RCO to 5MHz. */
297 emuDcdcLnRcoBand_5MHz = 2,
298 /** Set RCO to 6MHz. */
299 emuDcdcLnRcoBand_6MHz = 3,
300 /** Set RCO to 7MHz. */
301 emuDcdcLnRcoBand_7MHz = 4,
302 /** Set RCO to 8MHz. */
303 emuDcdcLnRcoBand_8MHz = 5,
304 /** Set RCO to 9MHz. */
305 emuDcdcLnRcoBand_9MHz = 6,
306 /** Set RCO to 10MHz. */
307 emuDcdcLnRcoBand_10MHz = 7,
308 } EMU_DcdcLnRcoBand_TypeDef;
309
310 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
311 /* Deprecated. */
312 #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz
313 #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz
314 #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz
315 #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz
316 #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz
317 #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz
318 #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz
319 #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz
320 /** @endcond */
321
322 /** DCDC Low Noise Compensator Control register. */
323 typedef enum {
324 /** DCDC capacitor is 1uF. */
325 emuDcdcLnCompCtrl_1u0F,
326 /** DCDC capacitor is 4.7uF. */
327 emuDcdcLnCompCtrl_4u7F,
328 } EMU_DcdcLnCompCtrl_TypeDef;
329 #endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */
330
331 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
332 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
333 /** DCDC mode. */
334 typedef enum {
335 emuDcdcMode_Bypass = _DCDC_CTRL_MODE_BYPASS, /**< DCDC regulator bypass. */
336 emuDcdcMode_Regulation = _DCDC_CTRL_MODE_DCDCREGULATION /**< DCDC regulator on. */
337 } EMU_DcdcMode_TypeDef;
338 #endif
339
340 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
341 /** VREGIN comparator threshold. */
342 typedef enum {
343 emuVreginCmpThreshold_2v0 = 0, /**< Comparator threshold is 2.0V. */
344 emuVreginCmpThreshold_2v1 = 1, /**< Comparator threshold is 2.1V. */
345 emuVreginCmpThreshold_2v2 = 2, /**< Comparator threshold is 2.2V. */
346 emuVreginCmpThreshold_2v3 = 3 /**< Comparator threshold is 2.3V. */
347 } EMU_VreginCmpThreshold_TypeDef;
348
349 /** DCDC Buck Ton max timeout. */
350 typedef enum {
351 #if (defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2) \
352 || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7))
353 emuDcdcTonMaxTimeout_Off = _DCDC_CTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */
354 emuDcdcTonMaxTimeout_0P35us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */
355 emuDcdcTonMaxTimeout_0P63us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */
356 emuDcdcTonMaxTimeout_0P91us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */
357 emuDcdcTonMaxTimeout_1P19us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */
358 emuDcdcTonMaxTimeout_1P47us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */
359 emuDcdcTonMaxTimeout_1P75us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */
360 emuDcdcTonMaxTimeout_2P03us = _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us /**< Ton max is 2.03us. */
361 #else
362 emuDcdcTonMaxTimeout_Off = 0, /**< Ton max off. */
363 emuDcdcTonMaxTimeout_0P14us = 1, /**< Ton max is 0.14us. */
364 emuDcdcTonMaxTimeout_0P21us = 2, /**< Ton max is 0.21us. */
365 emuDcdcTonMaxTimeout_0P28us = 3, /**< Ton max is 0.28us. */
366 emuDcdcTonMaxTimeout_0P35us = 4, /**< Ton max is 0.35us. */
367 emuDcdcTonMaxTimeout_0P42us = 5, /**< Ton max is 0.42us. */
368 emuDcdcTonMaxTimeout_0P49us = 6, /**< Ton max is 0.49us. */
369 emuDcdcTonMaxTimeout_0P56us = 7, /**< Ton max is 0.56us. */
370 emuDcdcTonMaxTimeout_0P63us = 8, /**< Ton max is 0.63us. */
371 emuDcdcTonMaxTimeout_0P70us = 9, /**< Ton max is 0.70us. */
372 emuDcdcTonMaxTimeout_0P77us = 10, /**< Ton max is 0.77us. */
373 emuDcdcTonMaxTimeout_0P84us = 11, /**< Ton max is 0.84us. */
374 emuDcdcTonMaxTimeout_0P91us = 12, /**< Ton max is 0.91us. */
375 emuDcdcTonMaxTimeout_0P98us = 13, /**< Ton max is 0.98us. */
376 emuDcdcTonMaxTimeout_1P05us = 14, /**< Ton max is 1.05us. */
377 emuDcdcTonMaxTimeout_1P12us = 15, /**< Ton max is 1.12us. */
378 emuDcdcTonMaxTimeout_1P19us = 16, /**< Ton max is 1.19us. */
379 emuDcdcTonMaxTimeout_1P26us = 17, /**< Ton max is 1.26us. */
380 emuDcdcTonMaxTimeout_1P33us = 18, /**< Ton max is 1.33us. */
381 emuDcdcTonMaxTimeout_1P40us = 19, /**< Ton max is 1.40us. */
382 emuDcdcTonMaxTimeout_1P47us = 20, /**< Ton max is 1.47us. */
383 emuDcdcTonMaxTimeout_1P54us = 21, /**< Ton max is 1.54us. */
384 emuDcdcTonMaxTimeout_1P61us = 22, /**< Ton max is 1.61us. */
385 emuDcdcTonMaxTimeout_1P68us = 23, /**< Ton max is 1.68us. */
386 emuDcdcTonMaxTimeout_1P75us = 24, /**< Ton max is 1.75us. */
387 emuDcdcTonMaxTimeout_1P82us = 25, /**< Ton max is 1.82us. */
388 emuDcdcTonMaxTimeout_1P89us = 26, /**< Ton max is 1.89us. */
389 emuDcdcTonMaxTimeout_1P96us = 27, /**< Ton max is 1.96us. */
390 emuDcdcTonMaxTimeout_2P03us = 28, /**< Ton max is 2.03us. */
391 emuDcdcTonMaxTimeout_2P10us = 29, /**< Ton max is 2.10us. */
392 emuDcdcTonMaxTimeout_2P17us = 30, /**< Ton max is 2.17us. */
393 emuDcdcTonMaxTimeout_2P24us = 31 /**< Ton max is 2.24us. */
394 #endif
395 } EMU_DcdcTonMaxTimeout_TypeDef;
396
397 /** DCDC Buck drive speed. */
398 typedef enum {
399 emuDcdcDriveSpeed_BestEmi = _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI, /**< Lowest efficiency, lowest EMI. */
400 emuDcdcDriveSpeed_Default = _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING, /**< Default efficiency, acceptable EMI level. */
401 emuDcdcDriveSpeed_Intermediate = _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE, /**< Small increase in efficiency from the default setting. */
402 emuDcdcDriveSpeed_BestEfficiency = _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY /**< Highest efficiency, highest EMI. Small increase in efficiency from INTERMEDIATE setting. */
403 } EMU_DcdcDriveSpeed_TypeDef;
404
405 /** DCDC Buck peak current setting. */
406 typedef enum {
407 #if defined(_DCDC_EM23CTRL0_IPKVAL_Load5mA)
408 emuDcdcPeakCurrent_Load5mA = _DCDC_EM23CTRL0_IPKVAL_Load5mA, /**< Load 5mA, peak current 90mA */
409 #endif
410 #if defined(_DCDC_EM23CTRL0_IPKVAL_Load10mA)
411 emuDcdcPeakCurrent_Load10mA = _DCDC_EM23CTRL0_IPKVAL_Load10mA, /**< Load 10mA, peak current 150mA */
412 #endif
413 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load28mA)
414 emuDcdcPeakCurrent_Load28mA = _DCDC_EM01CTRL0_IPKVAL_Load28mA, /**< Load 28mA, peak current 70mA. */
415 #endif
416 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load32mA)
417 emuDcdcPeakCurrent_Load32mA = _DCDC_EM01CTRL0_IPKVAL_Load32mA, /**< Load 32mA, peak current 80mA. */
418 #endif
419 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load36mA)
420 emuDcdcPeakCurrent_Load36mA = _DCDC_EM01CTRL0_IPKVAL_Load36mA, /**< Load 36mA, peak current 90mA. */
421 #endif
422 emuDcdcPeakCurrent_Load40mA = _DCDC_EM01CTRL0_IPKVAL_Load40mA, /**< Load 40mA, peak current 100mA. */
423 emuDcdcPeakCurrent_Load44mA = _DCDC_EM01CTRL0_IPKVAL_Load44mA, /**< Load 44mA, peak current 110mA. */
424 emuDcdcPeakCurrent_Load48mA = _DCDC_EM01CTRL0_IPKVAL_Load48mA, /**< Load 48mA, peak current 120mA. */
425 emuDcdcPeakCurrent_Load52mA = _DCDC_EM01CTRL0_IPKVAL_Load52mA, /**< Load 52mA, peak current 130mA. */
426 emuDcdcPeakCurrent_Load56mA = _DCDC_EM01CTRL0_IPKVAL_Load56mA, /**< Load 56mA, peak current 140mA. */
427 emuDcdcPeakCurrent_Load60mA = _DCDC_EM01CTRL0_IPKVAL_Load60mA, /**< Load 60mA, peak current 150mA. */
428 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load64mA)
429 emuDcdcPeakCurrent_Load64mA = _DCDC_EM01CTRL0_IPKVAL_Load64mA, /**< Load 64mA, peak current 160mA. */
430 #endif
431 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load68mA)
432 emuDcdcPeakCurrent_Load68mA = _DCDC_EM01CTRL0_IPKVAL_Load68mA, /**< Load 68mA, peak current 170mA. */
433 #endif
434 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load72mA)
435 emuDcdcPeakCurrent_Load72mA = _DCDC_EM01CTRL0_IPKVAL_Load72mA, /**< Load 72mA, peak current 180mA. */
436 #endif
437 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load76mA)
438 emuDcdcPeakCurrent_Load76mA = _DCDC_EM01CTRL0_IPKVAL_Load76mA, /**< Load 76mA, peak current 190mA. */
439 #endif
440 #if defined(_DCDC_EM01CTRL0_IPKVAL_Load80mA)
441 emuDcdcPeakCurrent_Load80mA = _DCDC_EM01CTRL0_IPKVAL_Load80mA /**< Load 80mA, peak current 200mA. */
442 #endif
443 } EMU_DcdcPeakCurrent_TypeDef;
444 #endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */
445
446 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
447 /** DCDC Boost drive speed. */
448 typedef enum {
449 emuDcdcBoostDriveSpeed_BestEmi = _DCDC_BSTEM01CTRL_DRVSPEED_BEST_EMI, /**< Lowest efficiency, lowest EMI. */
450 emuDcdcBoostDriveSpeed_Default = _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING, /**< Default efficiency, acceptable EMI level. */
451 emuDcdcBoostDriveSpeed_Intermediate = _DCDC_BSTEM01CTRL_DRVSPEED_INTERMEDIATE, /**< Small increase in efficiency from the default setting. */
452 emuDcdcBoostDriveSpeed_BestEfficiency = _DCDC_BSTEM01CTRL_DRVSPEED_BEST_EFFICIENCY /**< Highest efficiency, highest EMI. Small increase in efficiency from INTERMEDIATE setting. */
453 } EMU_DcdcBoostDriveSpeed_TypeDef;
454
455 /** DCDC Boost EM01 peak current setting. */
456 typedef enum {
457 emuDcdcBoostEM01PeakCurrent_Load10mA = _DCDC_BSTEM01CTRL_IPKVAL_Load10mA, /**< Load 10mA */
458 emuDcdcBoostEM01PeakCurrent_Load11mA = _DCDC_BSTEM01CTRL_IPKVAL_Load11mA, /**< Load 11mA */
459 emuDcdcBoostEM01PeakCurrent_Load13mA = _DCDC_BSTEM01CTRL_IPKVAL_Load13mA, /**< Load 13mA */
460 emuDcdcBoostEM01PeakCurrent_Load15mA = _DCDC_BSTEM01CTRL_IPKVAL_Load15mA, /**< Load 15mA */
461 emuDcdcBoostEM01PeakCurrent_Load16mA = _DCDC_BSTEM01CTRL_IPKVAL_Load16mA, /**< Load 16mA */
462 emuDcdcBoostEM01PeakCurrent_Load18mA = _DCDC_BSTEM01CTRL_IPKVAL_Load18mA, /**< Load 18mA */
463 emuDcdcBoostEM01PeakCurrent_Load20mA = _DCDC_BSTEM01CTRL_IPKVAL_Load20mA, /**< Load 20mA */
464 emuDcdcBoostEM01PeakCurrent_Load21mA = _DCDC_BSTEM01CTRL_IPKVAL_Load21mA, /**< Load 21mA */
465 emuDcdcBoostEM01PeakCurrent_Load23mA = _DCDC_BSTEM01CTRL_IPKVAL_Load23mA, /**< Load 23mA */
466 emuDcdcBoostEM01PeakCurrent_Load25mA = _DCDC_BSTEM01CTRL_IPKVAL_Load25mA, /**< Load 25mA */
467 } EMU_DcdcBoostEM01PeakCurrent_TypeDef;
468
469 /** DCDC Boost Toff max timeout */
470 typedef enum {
471 emuDcdcBoostToffMaxTimeout_Off = _DCDC_BSTCTRL_BSTTOFFMAX_OFF, /**< Toff max off. */
472 emuDcdcBoostToffMaxTimeout_0P35us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us, /**< Toff max is 0.35us. */
473 emuDcdcBoostToffMaxTimeout_0P63us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us, /**< Toff max is 0.63us. */
474 emuDcdcBoostToffMaxTimeout_0P91us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us, /**< Toff max is 0.91us. */
475 emuDcdcBoostToffMaxTimeout_1P19us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us, /**< Toff max is 1.19us. */
476 emuDcdcBoostToffMaxTimeout_1P47us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us, /**< Toff max is 1.47us. */
477 emuDcdcBoostToffMaxTimeout_1P75us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us, /**< Toff max is 1.75us. */
478 emuDcdcBoostToffMaxTimeout_2P03us = _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us, /**< Toff max is 2.03us. */
479 } EMU_DcdcBoostToffMaxTimeout_TypeDef;
480
481 /** DCDC Boost peak current detection maximum timeout */
482 typedef enum {
483 emuDcdcBoostTonMaxTimeout_Off = _DCDC_BSTCTRL_IPKTMAXCTRL_OFF, /**< Ton max off. */
484 emuDcdcBoostTonMaxTimeout_0P35us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us, /**< Ton max is 0.35us. */
485 emuDcdcBoostTonMaxTimeout_0P63us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us, /**< Ton max is 0.63us. */
486 emuDcdcBoostTonMaxTimeout_0P91us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us, /**< Ton max is 0.91us. */
487 emuDcdcBoostTonMaxTimeout_1P19us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us, /**< Ton max is 1.19us. */
488 emuDcdcBoostTonMaxTimeout_1P47us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us, /**< Ton max is 1.47us. */
489 emuDcdcBoostTonMaxTimeout_1P75us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us, /**< Ton max is 1.75us. */
490 emuDcdcBoostTonMaxTimeout_2P03us = _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us, /**< Ton max is 2.03us. */
491 } EMU_DcdcBoostTonMaxTimeout_TypeDef;
492
493 /** DCDC Boost EM23 peak current setting. */
494 typedef enum {
495 emuDcdcBoostEM23PeakCurrent_Load10mA = _DCDC_BSTEM23CTRL_IPKVAL_Load10mA, /**< Load 10mA */
496 } EMU_DcdcBoostEM23PeakCurrent_TypeDef;
497 #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT) */
498
499 #if defined(EMU_STATUS_VMONRDY)
500 /** VMON channels. */
501 typedef enum {
502 emuVmonChannel_AVDD,
503 emuVmonChannel_ALTAVDD,
504 emuVmonChannel_DVDD,
505 emuVmonChannel_IOVDD0,
506 #if defined(_EMU_VMONIO1CTRL_EN_MASK)
507 emuVmonChannel_IOVDD1,
508 #endif
509 #if defined(_EMU_VMONBUVDDCTRL_EN_MASK)
510 emuVmonChannel_BUVDD,
511 #endif
512 } EMU_VmonChannel_TypeDef;
513 #endif /* EMU_STATUS_VMONRDY */
514
515 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
516 /** Bias mode configurations. */
517 typedef enum {
518 emuBiasMode_1KHz,
519 emuBiasMode_4KHz,
520 emuBiasMode_Continuous
521 } EMU_BiasMode_TypeDef;
522 #endif
523
524 #if defined(EMU_VSCALE_EM01_PRESENT)
525 /** Supported EM0/1 Voltage Scaling Levels. */
526 typedef enum {
527 /** High-performance voltage level. HF clock can be set to any frequency. */
528 emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2,
529 /** Low-power optimized voltage level. HF clock must be limited
530 to CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage.
531 EM0/1 voltage scaling is applied when core clock frequency is
532 changed from @ref cmu or when calling @ref EMU_EM01Init() when HF
533 clock is already below the limit. */
534 #if defined(_SILICON_LABS_32B_SERIES_2)
535 /** Minimum VSCALE level in EM0/1 is VSCALE1. */
536 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE1,
537 #else
538 emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0,
539 #endif
540 } EMU_VScaleEM01_TypeDef;
541 #endif
542
543 #if defined(EMU_VSCALE_PRESENT)
544 /** Supported EM2/3 Voltage Scaling Levels. */
545 typedef enum {
546 /** Fast-wakeup voltage level. */
547 emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2,
548 /** Low-power optimized voltage level. Using this voltage level in EM2 and 3
549 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled
550 up to emuVScaleEM01_HighPerformance on EM2 or 3 exit. */
551 emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0,
552 } EMU_VScaleEM23_TypeDef;
553 #endif
554
555 #if defined(_EMU_CTRL_EM4HVSCALE_MASK)
556 /** Supported EM4H Voltage Scaling Levels */
557 typedef enum {
558 /** Fast-wakeup voltage level. */
559 emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2,
560 /** Low-power optimized voltage level. Using this voltage level in EM4H
561 adds approximately 30 us to wakeup time if EM0 and 1 voltage must be scaled
562 up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */
563 emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0,
564 } EMU_VScaleEM4H_TypeDef;
565 #endif
566
567 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
568 /** Peripheral EM2 and 3 retention control. */
569 typedef enum {
570 #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
571 emuPeripheralRetention_USB = _EMU_EM23PERNORETAINCTRL_USBDIS_MASK, /**< Select USB retention control. */
572 #endif
573 #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
574 emuPeripheralRetention_RTC = _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK, /**< Select RTC retention control. */
575 #endif
576 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
577 emuPeripheralRetention_ACMP3 = _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK, /**< Select ACMP3 retention control. */
578 #endif
579 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
580 emuPeripheralRetention_ACMP2 = _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK, /**< Select ACMP2 retention control. */
581 #endif
582 #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
583 emuPeripheralRetention_ADC1 = _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK, /**< Select ADC1 retention control. */
584 #endif
585 #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
586 emuPeripheralRetention_I2C2 = _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK, /**< Select I2C2 retention control. */
587 #endif
588 #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
589 emuPeripheralRetention_LETIMER1 = _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK, /**< Select LETIMER1 retention control. */
590 #endif
591 #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
592 emuPeripheralRetention_LCD = _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK, /**< Select LCD retention control. */
593 #endif
594 #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
595 emuPeripheralRetention_LEUART1 = _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK, /**< Select LEUART1 retention control. */
596 #endif
597 emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /**< Select LEUART0 retention control. */
598 #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
599 emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /**< Select CSEN retention control. */
600 #endif
601 emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /**< Select LESENSE0 retention control. */
602 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
603 emuPeripheralRetention_WDOG1 = _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK, /**< Select WDOG1 retention control. */
604 #endif
605 emuPeripheralRetention_WDOG0 = _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK, /**< Select WDOG0 retention control. */
606 emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /**< Select LETIMER0 retention control. */
607 emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /**< Select ADC0 retention control. */
608 #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
609 emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /**< Select IDAC0 retention control. */
610 #endif
611 #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK)
612 emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK, /**< Select VDAC0 retention control. */
613 #endif
614 #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
615 emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /**< Select I2C1 retention control. */
616 #endif
617 emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /**< Select I2C0 retention control. */
618 emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /**< Select ACMP1 retention control. */
619 emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /**< Select ACMP0 retention control. */
620 #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
621 emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /**< Select PCNT2 retention control. */
622 emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /**< Select PCNT1 retention control. */
623 #endif
624 emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /**< Select PCNT0 retention control. */
625
626 emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK
627 | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK
628 | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK
629 | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK
630 | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/**< Select all peripherals in domain 1. */
631 emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK
632 #if defined(_EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK)
633 | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK
634 #endif
635 #if defined(_EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK)
636 | _EMU_EM23PERNORETAINCTRL_VDAC0DIS_MASK
637 #endif
638 #if defined(_EMU_EM23PERNORETAINCTRL_CSENDIS_MASK)
639 | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK
640 #endif
641 | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK
642 #if defined(_EMU_EM23PERNORETAINCTRL_USBDIS_MASK)
643 | _EMU_EM23PERNORETAINCTRL_USBDIS_MASK
644 #endif
645 #if defined(_EMU_EM23PERNORETAINCTRL_RTCDIS_MASK)
646 | _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK
647 #endif
648 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK)
649 | _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK
650 #endif
651 #if defined(_EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK)
652 | _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK
653 #endif
654 #if defined(_EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK)
655 | _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK
656 #endif
657 #if defined(_EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK)
658 | _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK
659 #endif
660 #if defined(_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK)
661 | _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK
662 #endif
663 #if defined(_EMU_EM23PERNORETAINCTRL_LCDDIS_MASK)
664 | _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK
665 #endif
666 #if defined(_EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK)
667 | _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK
668 #endif
669 #if defined(_EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK)
670 | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK
671 | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK
672 #endif
673 #if defined(_EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK)
674 | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK /**< Select all peripherals in domain 2. */
675 #endif
676 | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK,
677 emuPeripheralRetention_ALL = emuPeripheralRetention_D1
678 | emuPeripheralRetention_D2
679 #if defined(_EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK)
680 | emuPeripheralRetention_WDOG1
681 #endif
682 | emuPeripheralRetention_WDOG0, /**< Select all peripherals with retention control. */
683 } EMU_PeripheralRetention_TypeDef;
684 #endif
685
686 #if defined(_EMU_TEMP_TEMPAVG_MASK)
687 /** Number of samples to use for temperature averaging. */
688 typedef enum {
689 /** 16 samples used for temperature averaging. */
690 emuTempAvgNum_16 = _EMU_CTRL_TEMPAVGNUM_N16,
691 /** 64 samples used for temperature averaging. */
692 emuTempAvgNum_64 = _EMU_CTRL_TEMPAVGNUM_N64,
693 } EMU_TempAvgNum_TypeDef;
694 #endif
695
696 /*******************************************************************************
697 ******************************* STRUCTS ***********************************
698 ******************************************************************************/
699
700 #if defined(EMU_VSCALE_EM01_PRESENT)
701 /** EM0 and 1 initialization structure. Voltage scaling is applied when
702 the core clock frequency is changed from @ref cmu. EM0 and 1 emuVScaleEM01_HighPerformance
703 is always enabled. */
704 typedef struct {
705 bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status. */
706 } EMU_EM01Init_TypeDef;
707
708 /** Default initialization of EM0 and 1 configuration. */
709 #define EMU_EM01INIT_DEFAULT \
710 { \
711 false /* Do not scale down in EM0/1.*/ \
712 }
713 #endif
714
715 /** EM2 and 3 initialization structure. */
716 typedef struct {
717 bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3. */
718 #if defined(EMU_VSCALE_PRESENT)
719 EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level. */
720 #endif
721 } EMU_EM23Init_TypeDef;
722
723 /** Default initialization of EM2 and 3 configuration. */
724 #if defined(EMU_VSCALE_PRESENT)
725 #define EMU_EM23INIT_DEFAULT \
726 { \
727 false, /* Reduced voltage regulator drive strength in EM2/3.*/ \
728 emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3. */ \
729 }
730 #else
731 #define EMU_EM23INIT_DEFAULT \
732 { \
733 false, /* Reduced voltage regulator drive strength in EM2/3.*/ \
734 }
735 #endif
736
737 #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
738 /** EM4 initialization structure. */
739 typedef struct {
740 #if defined(_EMU_EM4CONF_MASK)
741 /* Initialization parameters for platforms with EMU->EM4CONF register (Series 0). */
742 bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator. */
743 bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4. */
744 EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator. */
745 bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt. */
746 bool vreg; /**< Enable EM4 voltage regulator. */
747 #elif defined(_EMU_EM4CTRL_MASK)
748 /* Initialization parameters for platforms with EMU->EM4CTRL register (Series 1). */
749 bool retainLfxo; /**< Disable LFXO upon EM4 entry. */
750 bool retainLfrco; /**< Disable LFRCO upon EM4 entry. */
751 bool retainUlfrco; /**< Disable ULFRCO upon EM4 entry. */
752 EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state. */
753 EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode. */
754 #endif
755 #if defined(_EMU_CTRL_EM4HVSCALE_MASK)
756 EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level. */
757 #endif
758 } EMU_EM4Init_TypeDef;
759 #endif
760
761 #if defined(_EMU_EM4CONF_MASK)
762 /** Default initialization of EM4 configuration (Series 0). */
763 #define EMU_EM4INIT_DEFAULT \
764 { \
765 false, /* Do not lock configuration after it's been set. */ \
766 false, /* No reset will be asserted due to BOD in EM4. */ \
767 emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator. */ \
768 true, /* Wake up on EM4 BURTC interrupt. */ \
769 true, /* Enable VREG. */ \
770 }
771
772 #elif defined(_EMU_CTRL_EM4HVSCALE_MASK)
773 /** Default initialization of EM4 configuration (Series 1 with VSCALE). */
774 #define EMU_EM4INIT_DEFAULT \
775 { \
776 false, /* Retain LFXO configuration upon EM4 entry. */ \
777 false, /* Retain LFRCO configuration upon EM4 entry. */ \
778 false, /* Retain ULFRCO configuration upon EM4 entry. */ \
779 emuEM4Shutoff, /* Use EM4 shutoff state. */ \
780 emuPinRetentionDisable, /* Do not retain pins in EM4. */ \
781 emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H. */ \
782 }
783
784 #elif defined(_EMU_EM4CTRL_MASK)
785 /** Default initialization of EM4 configuration (Series 1 without VSCALE). */
786 #define EMU_EM4INIT_DEFAULT \
787 { \
788 false, /* Retain LFXO configuration upon EM4 entry. */ \
789 false, /* Retain LFRCO configuration upon EM4 entry. */ \
790 false, /* Retain ULFRCO configuration upon EM4 entry. */ \
791 emuEM4Shutoff, /* Use EM4 shutoff state. */ \
792 emuPinRetentionDisable, /* Do not retain pins in EM4. */ \
793 }
794 #endif
795
796 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
797 /** Backup Power Domain Initialization structure. */
798 typedef struct {
799 /* Backup Power Domain power configuration. */
800
801 /** Voltage probe select, selects ADC voltage. */
802 EMU_Probe_TypeDef probe;
803 /** Enable BOD calibration mode. */
804 bool bodCal;
805 /** Enable BU_STAT status pin for active BU mode. */
806 bool statusPinEnable;
807
808 /* Backup Power Domain connection configuration. */
809 /** Power domain resistor. */
810 EMU_Resistor_TypeDef resistor;
811 /** BU_VOUT strong enable. */
812 bool voutStrong;
813 /** BU_VOUT medium enable. */
814 bool voutMed;
815 /** BU_VOUT weak enable. */
816 bool voutWeak;
817 /** Power connection, when not in Backup Mode. */
818 EMU_Power_TypeDef inactivePower;
819 /** Power connection, when in Backup Mode. */
820 EMU_Power_TypeDef activePower;
821 /** Enable backup power domain, and release reset, enable BU_VIN pin. */
822 bool enable;
823 } EMU_BUPDInit_TypeDef;
824
825 /** Default Backup Power Domain configuration. */
826 #define EMU_BUPDINIT_DEFAULT \
827 { \
828 emuProbe_Disable, /* Do not enable voltage probe. */ \
829 false, /* Disable BOD calibration mode. */ \
830 false, /* Disable BU_STAT pin for backup mode indication. */ \
831 \
832 emuRes_Res0, /* RES0 series resistance between main and backup power. */ \
833 false, /* Do not enable strong switch. */ \
834 false, /* Do not enable medium switch. */ \
835 false, /* Do not enable weak switch. */ \
836 \
837 emuPower_None, /* No connection between main and backup power. (inactive mode) */ \
838 emuPower_None, /* No connection between main and backup power. (active mode) */ \
839 true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset. */ \
840 }
841 #endif
842
843 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1)
844 /** Backup Power Domain Initialization structure. */
845 typedef struct {
846 bool disMaxComp; /**< Disable MAIN-BU Comparator. */
847 EMU_BUBuInactPwrCon_TypeDef inactivePwrCon; /**< Power connection configuration when not in backup mode. */
848 EMU_BUBuActPwrCon_TypeDef activePwrCon; /**< Power connection configuration when in backup mode. */
849 EMU_BUPwrRes_TypeDef pwrRes; /**< Power domain resistor. */
850 EMU_BUVoutRes_TypeDef voutRes; /**< BU_VOUT resistor select. */
851 bool buVinProbeEn; /**< Enable BU_VIN probing. */
852 bool staEn; /**< Enable backup mode status export. */
853 bool enable; /**< Enable backup power domain. */
854 } EMU_BUInit_TypeDef;
855
856 /** Default Backup Power Domain configuration. */
857 #define EMU_BUINIT_DEFAULT \
858 { \
859 false, /* MAIN-BU Comparator is not disabled */ \
860 emuBuBuInactPwrCon_None, /* No power connection wen not in backup mode */ \
861 emuBuBuActPwrCon_None, /* No power connection when in backup mode */ \
862 emuBuPwrRes_Res0, /* RES0 series resistance between main and backup power. */ \
863 emuBuVoutRes_Dis, /* Vout resistor is set to not connected */ \
864 false, /* BU_VIN probe is disabled */ \
865 false, /* Status export is disabled */ \
866 true /* Enable backup mode */ \
867 }
868 #endif
869
870 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
871 /** DCDC Boost regulator initialization structure. */
872 typedef struct {
873 EMU_DcdcBoostTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */
874 bool externalShutdownEn; /**< true = disable DCDC boost mode with BOOST_EN=0 */
875 EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */
876 EMU_DcdcBoostDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */
877 EMU_DcdcBoostEM01PeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */
878 EMU_DcdcBoostEM23PeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */
879 } EMU_DCDCBoostInit_TypeDef;
880
881 /** Default DCDC Boost initialization. */
882 #define EMU_DCDCBOOSTINIT_DEFAULT \
883 { \
884 emuDcdcBoostTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
885 true, /**< disable DCDC boost mode with BOOST_EN=0 */ \
886 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
887 emuDcdcBoostDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
888 emuDcdcBoostEM01PeakCurrent_Load25mA, /**< Default peak current in EM0/1. */ \
889 emuDcdcBoostEM23PeakCurrent_Load10mA /**< Default peak current in EM2/3. */ \
890 }
891 #endif /* EMU_SERIES2_DCDC_BOOST_PRESENT */
892
893 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
894 /** DCDC regulator initialization structure. */
895 typedef struct {
896 EMU_DcdcMode_TypeDef mode; /**< DCDC mode. */
897 EMU_VreginCmpThreshold_TypeDef cmpThreshold; /**< VREGIN comparator threshold. */
898 EMU_DcdcTonMaxTimeout_TypeDef tonMax; /**< Ton max timeout control. */
899 #if defined(_DCDC_CTRL_DCMONLYEN_MASK)
900 bool dcmOnlyEn; /**< DCM only mode enable. */
901 #endif
902 EMU_DcdcDriveSpeed_TypeDef driveSpeedEM01; /**< DCDC drive speed in EM0/1. */
903 EMU_DcdcDriveSpeed_TypeDef driveSpeedEM23; /**< DCDC drive speed in EM2/3. */
904 EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01; /**< EM0/1 peak current setting. */
905 EMU_DcdcPeakCurrent_TypeDef peakCurrentEM23; /**< EM2/3 peak current setting. */
906 } EMU_DCDCInit_TypeDef;
907
908 /** Default DCDC Buck initialization. */
909 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
910 #define EMU_DCDCINIT_DEFAULT \
911 { \
912 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
913 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
914 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
915 true, /**< Enable DCM only mode. */ \
916 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
917 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
918 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
919 emuDcdcPeakCurrent_Load36mA /**< Default peak current in EM2/3. */ \
920 }
921 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)
922 #define EMU_DCDCINIT_DEFAULT \
923 { \
924 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
925 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
926 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
927 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
928 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
929 emuDcdcPeakCurrent_Load36mA, /**< Default peak current in EM0/1. */ \
930 emuDcdcPeakCurrent_Load36mA /**< Default peak current in EM2/3. */ \
931 }
932 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4) || defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
933 #define EMU_DCDCINIT_DEFAULT \
934 { \
935 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
936 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
937 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
938 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
939 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
940 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
941 emuDcdcPeakCurrent_Load36mA /**< Default peak current in EM2/3. */ \
942 }
943 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)
944 #define EMU_DCDCINIT_DEFAULT \
945 { \
946 emuDcdcMode_Regulation, /**< DCDC regulator on. */ \
947 emuVreginCmpThreshold_2v3, /**< 2.3V VREGIN comparator threshold. */ \
948 emuDcdcTonMaxTimeout_1P19us, /**< Ton max is 1.19us. */ \
949 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM0/1. */ \
950 emuDcdcDriveSpeed_Default, /**< Default efficiency in EM2/3. */ \
951 emuDcdcPeakCurrent_Load60mA, /**< Default peak current in EM0/1. */ \
952 emuDcdcPeakCurrent_Load5mA /**< Default peak current in EM2/3. */ \
953 }
954 #endif
955 #endif /* SERIES2_DCDC_BBUCK_PRESENT */
956
957 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
958 /** DCDC initialization structure. */
959 typedef struct {
960 EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration.
961 @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */
962 EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1. */
963 uint16_t mVout; /**< Target output voltage (mV). */
964 uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1. (mA).
965 This estimate is also used for EM1 optimization;
966 if EM1 current is expected to be higher than EM0,
967 then this parameter should hold the higher EM1 current. */
968 uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA).
969 This estimate is also used for EM3 and 4 optimization;
970 if EM3 or 4 current is expected to be higher than EM2,
971 then this parameter should hold the higher EM3 or 4 current. */
972 uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA).
973 This can be set to the maximum for the power source,
974 for example the maximum for a battery. */
975 EMU_DcdcAnaPeripheralPower_TypeDef
976 anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode. */
977 EMU_DcdcLnReverseCurrentControl_TypeDef
978 reverseCurrentControl; /**< Low-noise reverse current control.
979 NOTE: this parameter uses special encoding:
980 >= 0 is forced CCM mode where the parameter is used as the
981 reverse current threshold in mA.
982 -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only). */
983 EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */
984 } EMU_DCDCInit_TypeDef;
985
986 /** Default DCDC initialization. */
987 #if defined(_EFM_DEVICE)
988 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
989 #define EMU_DCDCINIT_DEFAULT \
990 { \
991 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
992 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
993 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
994 5, /* Nominal EM0/1 load current of less than 5mA. */ \
995 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
996 200, /* Maximum average current of 200mA
997 (assume strong battery or other power source). */ \
998 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
999 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1000 emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \
1001 }
1002 #elif defined(WGM160PX22KGA2)
1003 #define EMU_DCDCINIT_DEFAULT \
1004 { \
1005 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1006 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1007 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1008 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1009 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1010 200, /* Maximum average current of 200mA
1011 (assume strong battery or other power source). */ \
1012 emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \
1013 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1014 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1015 }
1016 #else
1017 #define EMU_DCDCINIT_DEFAULT \
1018 { \
1019 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1020 emuDcdcMode_LowPower, /* Low-power mode in EM0. */ \
1021 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1022 5, /* Nominal EM0/1 load current of less than 5mA. */ \
1023 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1024 200, /* Maximum average current of 200mA
1025 (assume strong battery or other power source). */ \
1026 emuDcdcAnaPeripheralPower_AVDD,/* Select AVDD as analog power supply). */ \
1027 emuDcdcLnHighEfficiency, /* Use high-efficiency mode. */ \
1028 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1029 }
1030 #endif
1031
1032 #else /* EFR32 device. */
1033 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1034 #define EMU_DCDCINIT_DEFAULT \
1035 { \
1036 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1037 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1038 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1039 15, /* Nominal EM0/1 load current of less than 15mA. */ \
1040 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1041 200, /* Maximum average current of 200mA
1042 (assume strong battery or other power source). */ \
1043 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1044 160, /* Maximum reverse current of 160mA. */ \
1045 emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor. */ \
1046 }
1047 #else
1048 #define EMU_DCDCINIT_DEFAULT \
1049 { \
1050 emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD. */ \
1051 emuDcdcMode_LowNoise, /* Low-noise mode in EM0. */ \
1052 1800, /* Nominal output voltage for DVDD mode, 1.8V. */ \
1053 15, /* Nominal EM0/1 load current of less than 15mA. */ \
1054 10, /* Nominal EM2/3/4 load current less than 10uA. */ \
1055 200, /* Maximum average current of 200mA
1056 (assume strong battery or other power source). */ \
1057 emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power). */ \
1058 160, /* Maximum reverse current of 160mA. */ \
1059 emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor. */ \
1060 }
1061 #endif
1062 #endif
1063 #endif
1064
1065 #if defined(EMU_STATUS_VMONRDY)
1066 /** VMON initialization structure. */
1067 typedef struct {
1068 EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */
1069 int threshold; /**< Trigger threshold (mV). Supported range is 1620 mV to 3400 mV. */
1070 bool riseWakeup; /**< Wake up from EM4H on rising edge. */
1071 bool fallWakeup; /**< Wake up from EM4H on falling edge. */
1072 bool enable; /**< Enable VMON channel. */
1073 bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only). */
1074 } EMU_VmonInit_TypeDef;
1075
1076 /** Default VMON initialization structure. */
1077 #define EMU_VMONINIT_DEFAULT \
1078 { \
1079 emuVmonChannel_AVDD, /* AVDD VMON channel. */ \
1080 3200, /* 3.2 V threshold. */ \
1081 false, /* Do not wake from EM4H on rising edge. */ \
1082 false, /* Do not wake from EM4H on falling edge. */ \
1083 true, /* Enable VMON channel. */ \
1084 false /* Do not disable IO0 retention */ \
1085 }
1086
1087 /** VMON Hysteresis initialization structure. */
1088 typedef struct {
1089 EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure. */
1090 int riseThreshold; /**< Rising threshold (mV). */
1091 int fallThreshold; /**< Falling threshold (mV). */
1092 bool riseWakeup; /**< Wake up from EM4H on rising edge. */
1093 bool fallWakeup; /**< Wake up from EM4H on falling edge. */
1094 bool enable; /**< Enable VMON channel. */
1095 } EMU_VmonHystInit_TypeDef;
1096
1097 /** Default VMON Hysteresis initialization structure. */
1098 #define EMU_VMONHYSTINIT_DEFAULT \
1099 { \
1100 emuVmonChannel_AVDD, /* AVDD VMON channel. */ \
1101 3200, /* 3.2 V rise threshold. */ \
1102 3200, /* 3.2 V fall threshold. */ \
1103 false, /* Do not wake from EM4H on rising edge. */ \
1104 false, /* Do not wake from EM4H on falling edge. */ \
1105 true /* Enable VMON channel. */ \
1106 }
1107 #endif /* EMU_STATUS_VMONRDY */
1108
1109 /*******************************************************************************
1110 ***************************** PROTOTYPES **********************************
1111 ******************************************************************************/
1112
1113 #if defined(EMU_VSCALE_EM01_PRESENT)
1114 void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init);
1115 #endif
1116 void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init);
1117 void EMU_EM23PresleepHook(void);
1118 void EMU_EM23PostsleepHook(void);
1119 void EMU_EFPEM23PresleepHook(void);
1120 void EMU_EFPEM23PostsleepHook(void);
1121 void EMU_EnterEM2(bool restore);
1122 void EMU_EnterEM3(bool restore);
1123 void EMU_Save(void);
1124 void EMU_Restore(void);
1125 #if defined(_EMU_EM4CONF_MASK) || defined(_EMU_EM4CTRL_MASK)
1126 void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init);
1127 #endif
1128 void EMU_EM4PresleepHook(void);
1129 void EMU_EFPEM4PresleepHook(void);
1130 void EMU_EnterEM4(void);
1131 void EMU_EnterEM4Wait(void);
1132 #if defined(_EMU_EM4CTRL_MASK)
1133 void EMU_EnterEM4H(void);
1134 void EMU_EnterEM4S(void);
1135 #endif
1136 void EMU_MemPwrDown(uint32_t blocks) SL_DEPRECATED_API_SDK_4_1;
1137 void EMU_RamPowerDown(uint32_t start, uint32_t end);
1138 void EMU_RamPowerUp(void);
1139 #if defined(_EMU_EM23PERNORETAINCTRL_MASK)
1140 void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable);
1141 #endif
1142 void EMU_UpdateOscConfig(void) SL_DEPRECATED_API_SDK_4_1;
1143 #if defined(EMU_VSCALE_EM01_PRESENT)
1144 #if defined(_SILICON_LABS_32B_SERIES_2)
1145 void EMU_EFPEM01VScale(EMU_VScaleEM01_TypeDef voltage);
1146 #endif
1147 void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait);
1148 void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait);
1149 #endif
1150 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0)
1151 void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit);
1152 void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value);
1153 void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value);
1154 #endif
1155 #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_1)
1156 void EMU_BUInit(const EMU_BUInit_TypeDef *buInit);
1157 #endif
1158 #if defined(_EMU_BUCTRL_DISMAXCOMP_MASK)
1159 void EMU_BUDisMaxCompSet(bool disableMainBuComparator);
1160 #endif
1161 #if defined(_EMU_BUCTRL_BUINACTPWRCON_MASK)
1162 void EMU_BUBuInactPwrConSet(EMU_BUBuInactPwrCon_TypeDef inactPwrCon);
1163 #endif
1164 #if defined(_EMU_BUCTRL_BUACTPWRCON_MASK)
1165 void EMU_BUBuActPwrConSet(EMU_BUBuActPwrCon_TypeDef actPwrCon);
1166 #endif
1167 #if defined(_EMU_BUCTRL_PWRRES_MASK)
1168 void EMU_BUPwrResSet(EMU_BUPwrRes_TypeDef pwrRes);
1169 #endif
1170 #if defined(_EMU_BUCTRL_VOUTRES_MASK)
1171 void EMU_BUVoutResSet(EMU_BUVoutRes_TypeDef resistorSel);
1172 #endif
1173 #if defined(_EMU_BUCTRL_BUVINPROBEEN_MASK)
1174 void EMU_BUBuVinProbeEnSet(bool enable);
1175 #endif
1176 #if defined(_EMU_BUCTRL_STATEN_MASK)
1177 void EMU_BUStatEnSet(bool enable);
1178 #endif
1179 #if defined(_EMU_BUCTRL_EN_MASK)
1180 void EMU_BUEnableSet(bool enable);
1181 #endif
1182
1183 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \
1184 || (defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
1185 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT))
1186 void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode);
1187 #endif
1188
1189 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT) \
1190 || defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
1191 void EMU_DCDCUpdatedHook(void);
1192 #endif
1193
1194 #if defined(EMU_SERIES2_DCDC_BOOST_PRESENT)
1195 bool EMU_DCDCBoostInit(const EMU_DCDCBoostInit_TypeDef *dcdcBoostInit);
1196 void EMU_EM01BoostPeakCurrentSet(const EMU_DcdcBoostEM01PeakCurrent_TypeDef boostPeakCurrentEM01);
1197 void EMU_BoostExternalShutdownEnable(bool enable);
1198 #endif
1199
1200 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT) \
1201 || defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
1202 bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit);
1203 bool EMU_DCDCPowerOff(void);
1204 #endif
1205
1206 #if defined(EMU_SERIES2_DCDC_BUCK_PRESENT)
1207 void EMU_EM01PeakCurrentSet(const EMU_DcdcPeakCurrent_TypeDef peakCurrentEM01);
1208 #if defined(_DCDC_PFMXCTRL_IPKVAL_MASK)
1209 void EMU_DCDCSetPFMXModePeakCurrent(uint32_t value);
1210 #endif
1211 #if defined(_DCDC_PFMXCTRL_IPKTMAXCTRL_MASK)
1212 void EMU_DCDCSetPFMXTimeoutMaxCtrl(EMU_DcdcTonMaxTimeout_TypeDef value);
1213 #endif
1214 #endif /* EMU_SERIES2_DCDC_BUCK_PRESENT */
1215
1216 #if defined(EMU_SERIES1_DCDC_BUCK_PRESENT)
1217 #if defined(EMU_DCDCCTRL_DCDCMODEEM23)
1218 void EMU_DCDCModeEM23Set(EMU_DcdcModeEM23_TypeDef dcdcModeEM23);
1219 #endif
1220 void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet);
1221 bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage);
1222 void EMU_DCDCOptimizeSlice(uint32_t em0LoadCurrentmA);
1223 void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band);
1224 #endif /* EMU_SERIES1_DCDC_BUCK_PRESENT */
1225
1226 #if defined(EMU_STATUS_VMONRDY)
1227 void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit);
1228 void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit);
1229 void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable);
1230 bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel);
1231 #endif
1232 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80)
1233 void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode);
1234 #endif
1235 #if defined(_EMU_TEMP_TEMP_MASK)
1236 float EMU_TemperatureGet(void);
1237 #endif
1238 #if defined(EMU_CTRL_EFPDIRECTMODEEN)
1239 void EMU_EFPDirectModeEnable(bool enable);
1240 #endif
1241 #if defined(EMU_CTRL_EFPDRVDECOUPLE)
1242 void EMU_EFPDriveDecoupleSet(bool enable);
1243 #endif
1244 #if defined(EMU_CTRL_EFPDRVDVDD)
1245 void EMU_EFPDriveDvddSet(bool enable);
1246 #endif
1247
1248 #if defined(_DCDC_CTRL_MASK)
1249 /***************************************************************************//**
1250 * @brief
1251 * Lock DCDC registers in order to protect them against unintended
1252 * modification.
1253 ******************************************************************************/
EMU_DCDCLock(void)1254 __STATIC_INLINE void EMU_DCDCLock(void)
1255 {
1256 DCDC->LOCK = ~DCDC_LOCK_LOCKKEY_UNLOCKKEY;
1257 }
1258 #endif
1259
1260 #if defined(_DCDC_CTRL_MASK)
1261 /***************************************************************************//**
1262 * @brief
1263 * Unlock the DCDC so that writing to locked registers again is possible.
1264 ******************************************************************************/
EMU_DCDCUnlock(void)1265 __STATIC_INLINE void EMU_DCDCUnlock(void)
1266 {
1267 DCDC->LOCK = DCDC_LOCK_LOCKKEY_UNLOCKKEY;
1268 }
1269 #endif
1270
1271 #if defined(_DCDC_SYNCBUSY_MASK)
1272 /***************************************************************************//**
1273 * @brief
1274 * Wait for the DCDC to complete all synchronization of register changes.
1275 *
1276 * @param[in] mask
1277 * A bitmask corresponding to SYNCBUSY register defined bits indicating
1278 * registers that must complete any ongoing synchronization.
1279 ******************************************************************************/
EMU_DCDCSync(uint32_t mask)1280 __STATIC_INLINE void EMU_DCDCSync(uint32_t mask)
1281 {
1282 while (DCDC->SYNCBUSY & mask) {
1283 /* Wait for previous synchronization to finish */
1284 }
1285 }
1286 #endif
1287
1288 #if defined(_SILICON_LABS_32B_SERIES_1)
1289 /***************************************************************************//**
1290 * @brief
1291 * Check status of the internal LDO regulator.
1292 *
1293 * @return
1294 * Return true if the regulator is on, false if regulator is off.
1295 ******************************************************************************/
EMU_LDOStatusGet(void)1296 __STATIC_INLINE bool EMU_LDOStatusGet(void)
1297 {
1298 if ((*(volatile uint32_t*)0x400E303C & 0x00000040UL) == 0UL) {
1299 return true;
1300 } else {
1301 return false;
1302 }
1303 }
1304 #endif
1305
1306 /***************************************************************************//**
1307 * @brief
1308 * Enter energy mode 1 (EM1).
1309 ******************************************************************************/
EMU_EnterEM1(void)1310 __STATIC_INLINE void EMU_EnterEM1(void)
1311 {
1312 /* Enter sleep mode. */
1313 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
1314 __WFI();
1315 }
1316
1317 #if defined(EMU_VSCALE_EM01_PRESENT)
1318 /***************************************************************************//**
1319 * @brief
1320 * Wait for voltage scaling to complete.
1321 ******************************************************************************/
EMU_VScaleWait(void)1322 __STATIC_INLINE void EMU_VScaleWait(void)
1323 {
1324 #if defined(_SILICON_LABS_32B_SERIES_1)
1325 if (EMU_LDOStatusGet() == false) {
1326 /* Skip waiting if the LDO regulator is turned off. */
1327 return;
1328 }
1329 #endif
1330
1331 while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT) != 0U) {
1332 }
1333 }
1334 #endif
1335
1336 #if defined(EMU_VSCALE_EM01_PRESENT)
1337 /***************************************************************************//**
1338 * @brief
1339 * Get current voltage scaling level.
1340 *
1341 * @return
1342 * Current voltage scaling level.
1343 ******************************************************************************/
EMU_VScaleGet(void)1344 __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void)
1345 {
1346 EMU_VScaleWait();
1347 return (EMU_VScaleEM01_TypeDef)((uint32_t)
1348 ((EMU->STATUS & _EMU_STATUS_VSCALE_MASK)
1349 >> _EMU_STATUS_VSCALE_SHIFT));
1350 }
1351 #endif
1352
1353 #if defined(_EMU_STATUS_VMONRDY_MASK)
1354 /***************************************************************************//**
1355 * @brief
1356 * Get the status of the voltage monitor (VMON).
1357 *
1358 * @return
1359 * Status of the VMON. True if all the enabled channels are ready, false if
1360 * one or more of the enabled channels are not ready.
1361 ******************************************************************************/
EMU_VmonStatusGet(void)1362 __STATIC_INLINE bool EMU_VmonStatusGet(void)
1363 {
1364 return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT) != 0U;
1365 }
1366 #endif /* _EMU_STATUS_VMONRDY_MASK */
1367
1368 #if defined(_EMU_IF_MASK)
1369 /***************************************************************************//**
1370 * @brief
1371 * Clear one or more pending EMU interrupts.
1372 *
1373 * @param[in] flags
1374 * Pending EMU interrupt sources to clear. Use one or more valid
1375 * interrupt flags for the EMU module (EMU_IFC_nnn or EMU_IF_nnn).
1376 ******************************************************************************/
EMU_IntClear(uint32_t flags)1377 __STATIC_INLINE void EMU_IntClear(uint32_t flags)
1378 {
1379 #if defined(EMU_HAS_SET_CLEAR)
1380 EMU->IF_CLR = flags;
1381 #else
1382 EMU->IFC = flags;
1383 #endif
1384 }
1385
1386 /***************************************************************************//**
1387 * @brief
1388 * Disable one or more EMU interrupts.
1389 *
1390 * @param[in] flags
1391 * EMU interrupt sources to disable. Use one or more valid
1392 * interrupt flags for the EMU module (EMU_IEN_nnn).
1393 ******************************************************************************/
EMU_IntDisable(uint32_t flags)1394 __STATIC_INLINE void EMU_IntDisable(uint32_t flags)
1395 {
1396 #if defined(EMU_HAS_SET_CLEAR)
1397 EMU->IEN_CLR = flags;
1398 #else
1399 EMU->IEN &= ~flags;
1400 #endif
1401 }
1402
1403 /***************************************************************************//**
1404 * @brief
1405 * Enable one or more EMU interrupts.
1406 *
1407 * @note
1408 * Depending on the use, a pending interrupt may already be set prior to
1409 * enabling the interrupt. To ignore a pending interrupt, consider using
1410 * @ref EMU_IntClear() prior to enabling the interrupt.
1411 *
1412 * @param[in] flags
1413 * EMU interrupt sources to enable. Use one or more valid
1414 * interrupt flags for the EMU module (EMU_IEN_nnn).
1415 ******************************************************************************/
EMU_IntEnable(uint32_t flags)1416 __STATIC_INLINE void EMU_IntEnable(uint32_t flags)
1417 {
1418 #if defined(EMU_HAS_SET_CLEAR)
1419 EMU->IEN_SET = flags;
1420 #else
1421 EMU->IEN |= flags;
1422 #endif
1423 }
1424
1425 #if defined(EMU_CTRL_EFPDRVDVDD)
1426 /***************************************************************************//**
1427 * @brief
1428 * Disable one or more EFP interrupts.
1429 *
1430 * @param[in] flags
1431 * EFP interrupt sources to disable. Use one or more valid
1432 * interrupt flags for the EFP module (EFPIENnnn).
1433 ******************************************************************************/
EMU_EFPIntDisable(uint32_t flags)1434 __STATIC_INLINE void EMU_EFPIntDisable(uint32_t flags)
1435 {
1436 EMU->EFPIEN_CLR = flags;
1437 }
1438
1439 /***************************************************************************//**
1440 * @brief
1441 * Enable one or more EFP interrupts.
1442 *
1443 * @param[in] flags
1444 * EFP interrupt sources to enable. Use one or more valid
1445 * interrupt flags for the EFP module (EFPIENnnn).
1446 ******************************************************************************/
EMU_EFPIntEnable(uint32_t flags)1447 __STATIC_INLINE void EMU_EFPIntEnable(uint32_t flags)
1448 {
1449 EMU->EFPIEN_SET = flags;
1450 }
1451
1452 /***************************************************************************//**
1453 * @brief
1454 * Get pending EMU EFP interrupt flags.
1455 *
1456 * @note
1457 * Event bits are not cleared by the use of this function.
1458 *
1459 * @return
1460 * EMU EFP interrupt sources pending. .
1461 ******************************************************************************/
EMU_EFPIntGet(void)1462 __STATIC_INLINE uint32_t EMU_EFPIntGet(void)
1463 {
1464 return EMU->EFPIF;
1465 }
1466
1467 /***************************************************************************//**
1468 * @brief
1469 * Get enabled and pending EMU EFP interrupt flags.
1470 * Useful for handling more interrupt sources in the same interrupt handler.
1471 *
1472 * @note
1473 * Interrupt flags are not cleared by the use of this function.
1474 *
1475 * @return
1476 * Pending and enabled EMU EFP interrupt sources
1477 * Return value is the bitwise AND of
1478 * - the enabled interrupt sources in EMU_EFPIEN and
1479 * - the pending interrupt flags EMU_EFPIF.
1480 ******************************************************************************/
EMU_EFPIntGetEnabled(void)1481 __STATIC_INLINE uint32_t EMU_EFPIntGetEnabled(void)
1482 {
1483 uint32_t ien;
1484
1485 ien = EMU->EFPIEN;
1486 return EMU->EFPIF & ien;
1487 }
1488
1489 /***************************************************************************//**
1490 * @brief
1491 * Set one or more pending EMU EFP interrupts.
1492 *
1493 * @param[in] flags
1494 * EMU EFP interrupt sources to set to pending. Use one or more valid
1495 * interrupt flags for the EMU EFP module (EMU_EFPIFSnnn).
1496 ******************************************************************************/
EMU_EFPIntSet(uint32_t flags)1497 __STATIC_INLINE void EMU_EFPIntSet(uint32_t flags)
1498 {
1499 EMU->EFPIF_SET = flags;
1500 }
1501
1502 /***************************************************************************//**
1503 * @brief
1504 * Clear one or more pending EMU EFP interrupts.
1505 *
1506 * @param[in] flags
1507 * Pending EMU EFP interrupt sources to clear. Use one or more valid
1508 * interrupt flags for the EMU EFP module.
1509 ******************************************************************************/
EMU_EFPIntClear(uint32_t flags)1510 __STATIC_INLINE void EMU_EFPIntClear(uint32_t flags)
1511 {
1512 EMU->EFPIF_CLR = flags;
1513 }
1514 #endif
1515
1516 /***************************************************************************//**
1517 * @brief
1518 * Get pending EMU interrupt flags.
1519 *
1520 * @note
1521 * Event bits are not cleared by the use of this function.
1522 *
1523 * @return
1524 * EMU interrupt sources pending. Returns one or more valid
1525 * interrupt flags for the EMU module (EMU_IF_nnn).
1526 ******************************************************************************/
EMU_IntGet(void)1527 __STATIC_INLINE uint32_t EMU_IntGet(void)
1528 {
1529 return EMU->IF;
1530 }
1531
1532 /***************************************************************************//**
1533 * @brief
1534 * Get enabled and pending EMU interrupt flags.
1535 * Useful for handling more interrupt sources in the same interrupt handler.
1536 *
1537 * @note
1538 * Interrupt flags are not cleared by the use of this function.
1539 *
1540 * @return
1541 * Pending and enabled EMU interrupt sources
1542 * Return value is the bitwise AND of
1543 * - the enabled interrupt sources in EMU_IEN and
1544 * - the pending interrupt flags EMU_IF.
1545 ******************************************************************************/
EMU_IntGetEnabled(void)1546 __STATIC_INLINE uint32_t EMU_IntGetEnabled(void)
1547 {
1548 uint32_t ien;
1549
1550 ien = EMU->IEN;
1551 return EMU->IF & ien;
1552 }
1553
1554 /***************************************************************************//**
1555 * @brief
1556 * Set one or more pending EMU interrupts.
1557 *
1558 * @param[in] flags
1559 * EMU interrupt sources to set to pending. Use one or more valid
1560 * interrupt flags for the EMU module (EMU_IFS_nnn).
1561 ******************************************************************************/
EMU_IntSet(uint32_t flags)1562 __STATIC_INLINE void EMU_IntSet(uint32_t flags)
1563 {
1564 #if defined(EMU_HAS_SET_CLEAR)
1565 EMU->IF_SET = flags;
1566 #else
1567 EMU->IFS = flags;
1568 #endif
1569 }
1570 #endif /* _EMU_IF_MASK */
1571
1572 #if defined(_EMU_EM4CONF_LOCKCONF_MASK)
1573 /***************************************************************************//**
1574 * @brief
1575 * Enable or disable EM4 lock configuration.
1576 * @param[in] enable
1577 * If true, locks down EM4 configuration.
1578 ******************************************************************************/
EMU_EM4Lock(bool enable)1579 __STATIC_INLINE void EMU_EM4Lock(bool enable)
1580 {
1581 BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable);
1582 }
1583 #endif
1584
1585 #if defined(_EMU_STATUS_BURDY_MASK)
1586 /***************************************************************************//**
1587 * @brief
1588 * Halts until backup power functionality is ready.
1589 ******************************************************************************/
EMU_BUReady(void)1590 __STATIC_INLINE void EMU_BUReady(void)
1591 {
1592 while (!(EMU->STATUS & EMU_STATUS_BURDY))
1593 ;
1594 }
1595 #endif
1596
1597 #if defined(_EMU_ROUTE_BUVINPEN_MASK)
1598 /***************************************************************************//**
1599 * @brief
1600 * Disable BU_VIN support.
1601 * @param[in] enable
1602 * If true, enables BU_VIN input pin support, if false disables it.
1603 ******************************************************************************/
EMU_BUPinEnable(bool enable)1604 __STATIC_INLINE void EMU_BUPinEnable(bool enable)
1605 {
1606 BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable);
1607 }
1608 #endif
1609
1610 /***************************************************************************//**
1611 * @brief
1612 * Lock EMU registers in order to protect them against unintended
1613 * modification.
1614 *
1615 * @note
1616 * If locking EMU registers, they must be unlocked prior to using any
1617 * EMU API functions modifying EMU registers, excluding interrupt control
1618 * and regulator control if the architecture has a EMU_PWRCTRL register.
1619 * An exception to this is the energy mode entering API (EMU_EnterEMn()),
1620 * which can be used when the EMU registers are locked.
1621 ******************************************************************************/
EMU_Lock(void)1622 __STATIC_INLINE void EMU_Lock(void)
1623 {
1624 EMU->LOCK = 0x0;
1625 }
1626
1627 /***************************************************************************//**
1628 * @brief
1629 * Unlock the EMU so that writing to locked registers again is possible.
1630 ******************************************************************************/
EMU_Unlock(void)1631 __STATIC_INLINE void EMU_Unlock(void)
1632 {
1633 EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK;
1634 }
1635
1636 #if defined(_EMU_PWRLOCK_MASK)
1637 /***************************************************************************//**
1638 * @brief
1639 * Lock the EMU regulator control registers in order to protect against
1640 * unintended modification.
1641 ******************************************************************************/
EMU_PowerLock(void)1642 __STATIC_INLINE void EMU_PowerLock(void)
1643 {
1644 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK;
1645 }
1646
1647 /***************************************************************************//**
1648 * @brief
1649 * Unlock the EMU power control registers so that writing to
1650 * locked registers again is possible.
1651 ******************************************************************************/
EMU_PowerUnlock(void)1652 __STATIC_INLINE void EMU_PowerUnlock(void)
1653 {
1654 EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK;
1655 }
1656 #endif
1657
1658 #if defined(_EMU_CTRL_EM2BLOCK_MASK)
1659 /***************************************************************************//**
1660 * @brief
1661 * Block entering EM2 or higher number energy modes.
1662 ******************************************************************************/
EMU_EM2Block(void)1663 __STATIC_INLINE void EMU_EM2Block(void)
1664 {
1665 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 1U);
1666 }
1667
1668 /***************************************************************************//**
1669 * @brief
1670 * Unblock entering EM2 or higher number energy modes.
1671 ******************************************************************************/
EMU_EM2UnBlock(void)1672 __STATIC_INLINE void EMU_EM2UnBlock(void)
1673 {
1674 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_EM2BLOCK_SHIFT, 0U);
1675 }
1676 #endif
1677
1678 #if defined(_EMU_EM4CTRL_EM4IORETMODE_MASK)
1679 /***************************************************************************//**
1680 * @brief
1681 * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained
1682 * through EM4 entry and wakeup. The pin state is released by calling this function.
1683 * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset),
1684 * and when initialization is done, this function can release pins and return control
1685 * to the peripherals or GPIO.
1686 ******************************************************************************/
EMU_UnlatchPinRetention(void)1687 __STATIC_INLINE void EMU_UnlatchPinRetention(void)
1688 {
1689 EMU->CMD = EMU_CMD_EM4UNLATCH;
1690 }
1691 #endif
1692
1693 #if defined(_EMU_TEMP_TEMP_MASK)
1694 /** Zero degrees Celcius in Kelvin */
1695 #define EMU_TEMP_ZERO_C_IN_KELVIN (273.15f)
1696 /***************************************************************************//**
1697 * @brief
1698 * Temperature measurement ready status
1699 *
1700 * @return
1701 * True if temperature measurement is ready
1702 ******************************************************************************/
EMU_TemperatureReady(void)1703 __STATIC_INLINE bool EMU_TemperatureReady(void)
1704 {
1705 #if defined(EMU_STATUS_FIRSTTEMPDONE)
1706 return EMU->STATUS & EMU_STATUS_FIRSTTEMPDONE;
1707 #else
1708 return !((EMU->TEMP & _EMU_TEMP_TEMP_MASK) == 0u);
1709 #endif
1710 }
1711
1712 #if defined(_EMU_TEMP_TEMPAVG_MASK)
1713 /***************************************************************************//**
1714 * @brief
1715 * Get averaged temperature in degrees Celsius.
1716 *
1717 * @note
1718 * An averaged temperature measurement must first be requested by calling
1719 * @ref EMU_TemperatureAvgRequest() and waiting for the TEMPAVG interrupt flag
1720 * to go high.
1721 *
1722 * @return
1723 * Averaged temperature
1724 ******************************************************************************/
EMU_TemperatureAvgGet(void)1725 __STATIC_INLINE float EMU_TemperatureAvgGet(void)
1726 {
1727 return ((float) ((EMU->TEMP & _EMU_TEMP_TEMPAVG_MASK)
1728 >> _EMU_TEMP_TEMPAVG_SHIFT)
1729 ) / 4.0f - EMU_TEMP_ZERO_C_IN_KELVIN;
1730 }
1731
1732 /***************************************************************************//**
1733 * @brief
1734 * Request averaged temperature.
1735 *
1736 * @note
1737 * EMU must be unlocked by calling @ref EMU_Unlock() before this function
1738 * can be called.
1739 *
1740 * @param[in] numSamples
1741 * Number of temperature samples to average
1742 ******************************************************************************/
EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples)1743 __STATIC_INLINE void EMU_TemperatureAvgRequest(EMU_TempAvgNum_TypeDef numSamples)
1744 {
1745 BUS_RegBitWrite(&EMU->CTRL, _EMU_CTRL_TEMPAVGNUM_SHIFT, numSamples);
1746 EMU->CMD = 1u << _EMU_CMD_TEMPAVGREQ_SHIFT;
1747 }
1748
1749 #endif //defined(_EMU_TEMP_TEMPAVG_MASK)
1750 #endif //defined(_EMU_TEMP_TEMP_MASK)
1751
1752 /** @} (end addtogroup emu) */
1753
1754 #ifdef __cplusplus
1755 }
1756 #endif
1757
1758 #endif /* defined( EMU_PRESENT ) */
1759 #endif /* EM_EMU_H */
1760
