1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 SYSRTC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_SYSRTC_H 31 #define EFR32MG24_SYSRTC_H 32 #define SYSRTC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_SYSRTC SYSRTC 40 * @{ 41 * @brief EFR32MG24 SYSRTC Register Declaration. 42 *****************************************************************************/ 43 44 /** SYSRTC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP VERSION */ 47 __IOM uint32_t EN; /**< Module Enable Register */ 48 __IOM uint32_t SWRST; /**< Software Reset Register */ 49 __IOM uint32_t CFG; /**< Configuration Register */ 50 __IOM uint32_t CMD; /**< Command Register */ 51 __IM uint32_t STATUS; /**< Status register */ 52 __IOM uint32_t CNT; /**< Counter Value Register */ 53 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 54 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 55 uint32_t RESERVED0[3U]; /**< Reserved for future use */ 56 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 57 uint32_t RESERVED2[3U]; /**< Reserved for future use */ 58 __IOM uint32_t GRP0_IF; /**< Group Interrupt Flags */ 59 __IOM uint32_t GRP0_IEN; /**< Group Interrupt Enables */ 60 __IOM uint32_t GRP0_CTRL; /**< Group Control Register */ 61 __IOM uint32_t GRP0_CMP0VALUE; /**< Compare 0 Value Register */ 62 __IOM uint32_t GRP0_CMP1VALUE; /**< Compare 1 Value Register */ 63 __IM uint32_t GRP0_CAP0VALUE; /**< Capture 0 Value Register */ 64 __IM uint32_t GRP0_SYNCBUSY; /**< Synchronization busy Register */ 65 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 66 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 67 uint32_t RESERVED5[7U]; /**< Reserved for future use */ 68 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 69 uint32_t RESERVED7[991U]; /**< Reserved for future use */ 70 __IM uint32_t IPVERSION_SET; /**< IP VERSION */ 71 __IOM uint32_t EN_SET; /**< Module Enable Register */ 72 __IOM uint32_t SWRST_SET; /**< Software Reset Register */ 73 __IOM uint32_t CFG_SET; /**< Configuration Register */ 74 __IOM uint32_t CMD_SET; /**< Command Register */ 75 __IM uint32_t STATUS_SET; /**< Status register */ 76 __IOM uint32_t CNT_SET; /**< Counter Value Register */ 77 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 78 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 79 uint32_t RESERVED8[3U]; /**< Reserved for future use */ 80 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 81 uint32_t RESERVED10[3U]; /**< Reserved for future use */ 82 __IOM uint32_t GRP0_IF_SET; /**< Group Interrupt Flags */ 83 __IOM uint32_t GRP0_IEN_SET; /**< Group Interrupt Enables */ 84 __IOM uint32_t GRP0_CTRL_SET; /**< Group Control Register */ 85 __IOM uint32_t GRP0_CMP0VALUE_SET; /**< Compare 0 Value Register */ 86 __IOM uint32_t GRP0_CMP1VALUE_SET; /**< Compare 1 Value Register */ 87 __IM uint32_t GRP0_CAP0VALUE_SET; /**< Capture 0 Value Register */ 88 __IM uint32_t GRP0_SYNCBUSY_SET; /**< Synchronization busy Register */ 89 uint32_t RESERVED11[1U]; /**< Reserved for future use */ 90 uint32_t RESERVED12[1U]; /**< Reserved for future use */ 91 uint32_t RESERVED13[7U]; /**< Reserved for future use */ 92 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 93 uint32_t RESERVED15[991U]; /**< Reserved for future use */ 94 __IM uint32_t IPVERSION_CLR; /**< IP VERSION */ 95 __IOM uint32_t EN_CLR; /**< Module Enable Register */ 96 __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ 97 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 98 __IOM uint32_t CMD_CLR; /**< Command Register */ 99 __IM uint32_t STATUS_CLR; /**< Status register */ 100 __IOM uint32_t CNT_CLR; /**< Counter Value Register */ 101 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 102 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 103 uint32_t RESERVED16[3U]; /**< Reserved for future use */ 104 uint32_t RESERVED17[1U]; /**< Reserved for future use */ 105 uint32_t RESERVED18[3U]; /**< Reserved for future use */ 106 __IOM uint32_t GRP0_IF_CLR; /**< Group Interrupt Flags */ 107 __IOM uint32_t GRP0_IEN_CLR; /**< Group Interrupt Enables */ 108 __IOM uint32_t GRP0_CTRL_CLR; /**< Group Control Register */ 109 __IOM uint32_t GRP0_CMP0VALUE_CLR; /**< Compare 0 Value Register */ 110 __IOM uint32_t GRP0_CMP1VALUE_CLR; /**< Compare 1 Value Register */ 111 __IM uint32_t GRP0_CAP0VALUE_CLR; /**< Capture 0 Value Register */ 112 __IM uint32_t GRP0_SYNCBUSY_CLR; /**< Synchronization busy Register */ 113 uint32_t RESERVED19[1U]; /**< Reserved for future use */ 114 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 115 uint32_t RESERVED21[7U]; /**< Reserved for future use */ 116 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 117 uint32_t RESERVED23[991U]; /**< Reserved for future use */ 118 __IM uint32_t IPVERSION_TGL; /**< IP VERSION */ 119 __IOM uint32_t EN_TGL; /**< Module Enable Register */ 120 __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ 121 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 122 __IOM uint32_t CMD_TGL; /**< Command Register */ 123 __IM uint32_t STATUS_TGL; /**< Status register */ 124 __IOM uint32_t CNT_TGL; /**< Counter Value Register */ 125 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 126 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 127 uint32_t RESERVED24[3U]; /**< Reserved for future use */ 128 uint32_t RESERVED25[1U]; /**< Reserved for future use */ 129 uint32_t RESERVED26[3U]; /**< Reserved for future use */ 130 __IOM uint32_t GRP0_IF_TGL; /**< Group Interrupt Flags */ 131 __IOM uint32_t GRP0_IEN_TGL; /**< Group Interrupt Enables */ 132 __IOM uint32_t GRP0_CTRL_TGL; /**< Group Control Register */ 133 __IOM uint32_t GRP0_CMP0VALUE_TGL; /**< Compare 0 Value Register */ 134 __IOM uint32_t GRP0_CMP1VALUE_TGL; /**< Compare 1 Value Register */ 135 __IM uint32_t GRP0_CAP0VALUE_TGL; /**< Capture 0 Value Register */ 136 __IM uint32_t GRP0_SYNCBUSY_TGL; /**< Synchronization busy Register */ 137 uint32_t RESERVED27[1U]; /**< Reserved for future use */ 138 uint32_t RESERVED28[1U]; /**< Reserved for future use */ 139 uint32_t RESERVED29[7U]; /**< Reserved for future use */ 140 uint32_t RESERVED30[1U]; /**< Reserved for future use */ 141 } SYSRTC_TypeDef; 142 /** @} End of group EFR32MG24_SYSRTC */ 143 144 /**************************************************************************//** 145 * @addtogroup EFR32MG24_SYSRTC 146 * @{ 147 * @defgroup EFR32MG24_SYSRTC_BitFields SYSRTC Bit Fields 148 * @{ 149 *****************************************************************************/ 150 151 /* Bit fields for SYSRTC IPVERSION */ 152 #define _SYSRTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for SYSRTC_IPVERSION */ 153 #define _SYSRTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_IPVERSION */ 154 #define _SYSRTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for SYSRTC_IPVERSION */ 155 #define _SYSRTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_IPVERSION */ 156 #define _SYSRTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSRTC_IPVERSION */ 157 #define SYSRTC_IPVERSION_IPVERSION_DEFAULT (_SYSRTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_IPVERSION */ 158 159 /* Bit fields for SYSRTC EN */ 160 #define _SYSRTC_EN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_EN */ 161 #define _SYSRTC_EN_MASK 0x00000003UL /**< Mask for SYSRTC_EN */ 162 #define SYSRTC_EN_EN (0x1UL << 0) /**< SYSRTC Enable */ 163 #define _SYSRTC_EN_EN_SHIFT 0 /**< Shift value for SYSRTC_EN */ 164 #define _SYSRTC_EN_EN_MASK 0x1UL /**< Bit mask for SYSRTC_EN */ 165 #define _SYSRTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ 166 #define SYSRTC_EN_EN_DEFAULT (_SYSRTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_EN */ 167 #define SYSRTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ 168 #define _SYSRTC_EN_DISABLING_SHIFT 1 /**< Shift value for SYSRTC_DISABLING */ 169 #define _SYSRTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for SYSRTC_DISABLING */ 170 #define _SYSRTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_EN */ 171 #define SYSRTC_EN_DISABLING_DEFAULT (_SYSRTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_EN */ 172 173 /* Bit fields for SYSRTC SWRST */ 174 #define _SYSRTC_SWRST_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SWRST */ 175 #define _SYSRTC_SWRST_MASK 0x00000003UL /**< Mask for SYSRTC_SWRST */ 176 #define SYSRTC_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ 177 #define _SYSRTC_SWRST_SWRST_SHIFT 0 /**< Shift value for SYSRTC_SWRST */ 178 #define _SYSRTC_SWRST_SWRST_MASK 0x1UL /**< Bit mask for SYSRTC_SWRST */ 179 #define _SYSRTC_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ 180 #define SYSRTC_SWRST_SWRST_DEFAULT (_SYSRTC_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ 181 #define SYSRTC_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ 182 #define _SYSRTC_SWRST_RESETTING_SHIFT 1 /**< Shift value for SYSRTC_RESETTING */ 183 #define _SYSRTC_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for SYSRTC_RESETTING */ 184 #define _SYSRTC_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SWRST */ 185 #define SYSRTC_SWRST_RESETTING_DEFAULT (_SYSRTC_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SWRST */ 186 187 /* Bit fields for SYSRTC CFG */ 188 #define _SYSRTC_CFG_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CFG */ 189 #define _SYSRTC_CFG_MASK 0x00000001UL /**< Mask for SYSRTC_CFG */ 190 #define SYSRTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ 191 #define _SYSRTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for SYSRTC_DEBUGRUN */ 192 #define _SYSRTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for SYSRTC_DEBUGRUN */ 193 #define _SYSRTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CFG */ 194 #define _SYSRTC_CFG_DEBUGRUN_DISABLE 0x00000000UL /**< Mode DISABLE for SYSRTC_CFG */ 195 #define _SYSRTC_CFG_DEBUGRUN_ENABLE 0x00000001UL /**< Mode ENABLE for SYSRTC_CFG */ 196 #define SYSRTC_CFG_DEBUGRUN_DEFAULT (_SYSRTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CFG */ 197 #define SYSRTC_CFG_DEBUGRUN_DISABLE (_SYSRTC_CFG_DEBUGRUN_DISABLE << 0) /**< Shifted mode DISABLE for SYSRTC_CFG */ 198 #define SYSRTC_CFG_DEBUGRUN_ENABLE (_SYSRTC_CFG_DEBUGRUN_ENABLE << 0) /**< Shifted mode ENABLE for SYSRTC_CFG */ 199 200 /* Bit fields for SYSRTC CMD */ 201 #define _SYSRTC_CMD_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CMD */ 202 #define _SYSRTC_CMD_MASK 0x00000003UL /**< Mask for SYSRTC_CMD */ 203 #define SYSRTC_CMD_START (0x1UL << 0) /**< Start SYSRTC */ 204 #define _SYSRTC_CMD_START_SHIFT 0 /**< Shift value for SYSRTC_START */ 205 #define _SYSRTC_CMD_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ 206 #define _SYSRTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ 207 #define SYSRTC_CMD_START_DEFAULT (_SYSRTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CMD */ 208 #define SYSRTC_CMD_STOP (0x1UL << 1) /**< Stop SYSRTC */ 209 #define _SYSRTC_CMD_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ 210 #define _SYSRTC_CMD_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ 211 #define _SYSRTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CMD */ 212 #define SYSRTC_CMD_STOP_DEFAULT (_SYSRTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_CMD */ 213 214 /* Bit fields for SYSRTC STATUS */ 215 #define _SYSRTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_STATUS */ 216 #define _SYSRTC_STATUS_MASK 0x00000007UL /**< Mask for SYSRTC_STATUS */ 217 #define SYSRTC_STATUS_RUNNING (0x1UL << 0) /**< SYSRTC running status */ 218 #define _SYSRTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for SYSRTC_RUNNING */ 219 #define _SYSRTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for SYSRTC_RUNNING */ 220 #define _SYSRTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ 221 #define SYSRTC_STATUS_RUNNING_DEFAULT (_SYSRTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ 222 #define SYSRTC_STATUS_LOCKSTATUS (0x1UL << 1) /**< Lock Status */ 223 #define _SYSRTC_STATUS_LOCKSTATUS_SHIFT 1 /**< Shift value for SYSRTC_LOCKSTATUS */ 224 #define _SYSRTC_STATUS_LOCKSTATUS_MASK 0x2UL /**< Bit mask for SYSRTC_LOCKSTATUS */ 225 #define _SYSRTC_STATUS_LOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_STATUS */ 226 #define _SYSRTC_STATUS_LOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for SYSRTC_STATUS */ 227 #define _SYSRTC_STATUS_LOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for SYSRTC_STATUS */ 228 #define SYSRTC_STATUS_LOCKSTATUS_DEFAULT (_SYSRTC_STATUS_LOCKSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_STATUS */ 229 #define SYSRTC_STATUS_LOCKSTATUS_UNLOCKED (_SYSRTC_STATUS_LOCKSTATUS_UNLOCKED << 1) /**< Shifted mode UNLOCKED for SYSRTC_STATUS */ 230 #define SYSRTC_STATUS_LOCKSTATUS_LOCKED (_SYSRTC_STATUS_LOCKSTATUS_LOCKED << 1) /**< Shifted mode LOCKED for SYSRTC_STATUS */ 231 232 /* Bit fields for SYSRTC CNT */ 233 #define _SYSRTC_CNT_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_CNT */ 234 #define _SYSRTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_CNT */ 235 #define _SYSRTC_CNT_CNT_SHIFT 0 /**< Shift value for SYSRTC_CNT */ 236 #define _SYSRTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CNT */ 237 #define _SYSRTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_CNT */ 238 #define SYSRTC_CNT_CNT_DEFAULT (_SYSRTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_CNT */ 239 240 /* Bit fields for SYSRTC SYNCBUSY */ 241 #define _SYSRTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_SYNCBUSY */ 242 #define _SYSRTC_SYNCBUSY_MASK 0x0000000FUL /**< Mask for SYSRTC_SYNCBUSY */ 243 #define SYSRTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START bitfield */ 244 #define _SYSRTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for SYSRTC_START */ 245 #define _SYSRTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for SYSRTC_START */ 246 #define _SYSRTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ 247 #define SYSRTC_SYNCBUSY_START_DEFAULT (_SYSRTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ 248 #define SYSRTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP bitfield */ 249 #define _SYSRTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for SYSRTC_STOP */ 250 #define _SYSRTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for SYSRTC_STOP */ 251 #define _SYSRTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ 252 #define SYSRTC_SYNCBUSY_STOP_DEFAULT (_SYSRTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ 253 #define SYSRTC_SYNCBUSY_CNT (0x1UL << 2) /**< Sync busy for CNT bitfield */ 254 #define _SYSRTC_SYNCBUSY_CNT_SHIFT 2 /**< Shift value for SYSRTC_CNT */ 255 #define _SYSRTC_SYNCBUSY_CNT_MASK 0x4UL /**< Bit mask for SYSRTC_CNT */ 256 #define _SYSRTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_SYNCBUSY */ 257 #define SYSRTC_SYNCBUSY_CNT_DEFAULT (_SYSRTC_SYNCBUSY_CNT_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_SYNCBUSY */ 258 259 /* Bit fields for SYSRTC LOCK */ 260 #define _SYSRTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_LOCK */ 261 #define _SYSRTC_LOCK_MASK 0x0000FFFFUL /**< Mask for SYSRTC_LOCK */ 262 #define _SYSRTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for SYSRTC_LOCKKEY */ 263 #define _SYSRTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for SYSRTC_LOCKKEY */ 264 #define _SYSRTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_LOCK */ 265 #define _SYSRTC_LOCK_LOCKKEY_UNLOCK 0x00004776UL /**< Mode UNLOCK for SYSRTC_LOCK */ 266 #define SYSRTC_LOCK_LOCKKEY_DEFAULT (_SYSRTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_LOCK */ 267 #define SYSRTC_LOCK_LOCKKEY_UNLOCK (_SYSRTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for SYSRTC_LOCK */ 268 269 /* Bit fields for SYSRTC GRP0_IF */ 270 #define _SYSRTC_GRP0_IF_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IF */ 271 #define _SYSRTC_GRP0_IF_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IF */ 272 #define SYSRTC_GRP0_IF_OVF (0x1UL << 0) /**< Overflow Interrupt Flag */ 273 #define _SYSRTC_GRP0_IF_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ 274 #define _SYSRTC_GRP0_IF_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ 275 #define _SYSRTC_GRP0_IF_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ 276 #define SYSRTC_GRP0_IF_OVF_DEFAULT (_SYSRTC_GRP0_IF_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ 277 #define SYSRTC_GRP0_IF_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Flag */ 278 #define _SYSRTC_GRP0_IF_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ 279 #define _SYSRTC_GRP0_IF_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ 280 #define _SYSRTC_GRP0_IF_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ 281 #define SYSRTC_GRP0_IF_CMP0_DEFAULT (_SYSRTC_GRP0_IF_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ 282 #define SYSRTC_GRP0_IF_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Flag */ 283 #define _SYSRTC_GRP0_IF_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ 284 #define _SYSRTC_GRP0_IF_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ 285 #define _SYSRTC_GRP0_IF_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ 286 #define SYSRTC_GRP0_IF_CMP1_DEFAULT (_SYSRTC_GRP0_IF_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ 287 #define SYSRTC_GRP0_IF_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Flag */ 288 #define _SYSRTC_GRP0_IF_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ 289 #define _SYSRTC_GRP0_IF_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ 290 #define _SYSRTC_GRP0_IF_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IF */ 291 #define SYSRTC_GRP0_IF_CAP0_DEFAULT (_SYSRTC_GRP0_IF_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IF */ 292 293 /* Bit fields for SYSRTC GRP0_IEN */ 294 #define _SYSRTC_GRP0_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_IEN */ 295 #define _SYSRTC_GRP0_IEN_MASK 0x0000000FUL /**< Mask for SYSRTC_GRP0_IEN */ 296 #define SYSRTC_GRP0_IEN_OVF (0x1UL << 0) /**< Overflow Interrupt Enable */ 297 #define _SYSRTC_GRP0_IEN_OVF_SHIFT 0 /**< Shift value for SYSRTC_OVF */ 298 #define _SYSRTC_GRP0_IEN_OVF_MASK 0x1UL /**< Bit mask for SYSRTC_OVF */ 299 #define _SYSRTC_GRP0_IEN_OVF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ 300 #define SYSRTC_GRP0_IEN_OVF_DEFAULT (_SYSRTC_GRP0_IEN_OVF_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ 301 #define SYSRTC_GRP0_IEN_CMP0 (0x1UL << 1) /**< Compare 0 Interrupt Enable */ 302 #define _SYSRTC_GRP0_IEN_CMP0_SHIFT 1 /**< Shift value for SYSRTC_CMP0 */ 303 #define _SYSRTC_GRP0_IEN_CMP0_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0 */ 304 #define _SYSRTC_GRP0_IEN_CMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ 305 #define SYSRTC_GRP0_IEN_CMP0_DEFAULT (_SYSRTC_GRP0_IEN_CMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ 306 #define SYSRTC_GRP0_IEN_CMP1 (0x1UL << 2) /**< Compare 1 Interrupt Enable */ 307 #define _SYSRTC_GRP0_IEN_CMP1_SHIFT 2 /**< Shift value for SYSRTC_CMP1 */ 308 #define _SYSRTC_GRP0_IEN_CMP1_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1 */ 309 #define _SYSRTC_GRP0_IEN_CMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ 310 #define SYSRTC_GRP0_IEN_CMP1_DEFAULT (_SYSRTC_GRP0_IEN_CMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ 311 #define SYSRTC_GRP0_IEN_CAP0 (0x1UL << 3) /**< Capture 0 Interrupt Enable */ 312 #define _SYSRTC_GRP0_IEN_CAP0_SHIFT 3 /**< Shift value for SYSRTC_CAP0 */ 313 #define _SYSRTC_GRP0_IEN_CAP0_MASK 0x8UL /**< Bit mask for SYSRTC_CAP0 */ 314 #define _SYSRTC_GRP0_IEN_CAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_IEN */ 315 #define SYSRTC_GRP0_IEN_CAP0_DEFAULT (_SYSRTC_GRP0_IEN_CAP0_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_IEN */ 316 317 /* Bit fields for SYSRTC GRP0_CTRL */ 318 #define _SYSRTC_GRP0_CTRL_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CTRL */ 319 #define _SYSRTC_GRP0_CTRL_MASK 0x000007FFUL /**< Mask for SYSRTC_GRP0_CTRL */ 320 #define SYSRTC_GRP0_CTRL_CMP0EN (0x1UL << 0) /**< Compare 0 Enable */ 321 #define _SYSRTC_GRP0_CTRL_CMP0EN_SHIFT 0 /**< Shift value for SYSRTC_CMP0EN */ 322 #define _SYSRTC_GRP0_CTRL_CMP0EN_MASK 0x1UL /**< Bit mask for SYSRTC_CMP0EN */ 323 #define _SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ 324 #define SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ 325 #define SYSRTC_GRP0_CTRL_CMP1EN (0x1UL << 1) /**< Compare 1 Enable */ 326 #define _SYSRTC_GRP0_CTRL_CMP1EN_SHIFT 1 /**< Shift value for SYSRTC_CMP1EN */ 327 #define _SYSRTC_GRP0_CTRL_CMP1EN_MASK 0x2UL /**< Bit mask for SYSRTC_CMP1EN */ 328 #define _SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ 329 #define SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ 330 #define SYSRTC_GRP0_CTRL_CAP0EN (0x1UL << 2) /**< Capture 0 Enable */ 331 #define _SYSRTC_GRP0_CTRL_CAP0EN_SHIFT 2 /**< Shift value for SYSRTC_CAP0EN */ 332 #define _SYSRTC_GRP0_CTRL_CAP0EN_MASK 0x4UL /**< Bit mask for SYSRTC_CAP0EN */ 333 #define _SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ 334 #define SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ 335 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_SHIFT 3 /**< Shift value for SYSRTC_CMP0CMOA */ 336 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_MASK 0x38UL /**< Bit mask for SYSRTC_CMP0CMOA */ 337 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ 338 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ 339 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ 340 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ 341 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ 342 #define _SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ 343 #define SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP0CMOA_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ 344 #define SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP0CMOA_CLEAR << 3) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ 345 #define SYSRTC_GRP0_CTRL_CMP0CMOA_SET (_SYSRTC_GRP0_CTRL_CMP0CMOA_SET << 3) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ 346 #define SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP0CMOA_PULSE << 3) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ 347 #define SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP0CMOA_TOGGLE << 3) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ 348 #define SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP0CMOA_CMPIF << 3) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ 349 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_SHIFT 6 /**< Shift value for SYSRTC_CMP1CMOA */ 350 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_MASK 0x1C0UL /**< Bit mask for SYSRTC_CMP1CMOA */ 351 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ 352 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR 0x00000000UL /**< Mode CLEAR for SYSRTC_GRP0_CTRL */ 353 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_SET 0x00000001UL /**< Mode SET for SYSRTC_GRP0_CTRL */ 354 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE 0x00000002UL /**< Mode PULSE for SYSRTC_GRP0_CTRL */ 355 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE 0x00000003UL /**< Mode TOGGLE for SYSRTC_GRP0_CTRL */ 356 #define _SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF 0x00000004UL /**< Mode CMPIF for SYSRTC_GRP0_CTRL */ 357 #define SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT (_SYSRTC_GRP0_CTRL_CMP1CMOA_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ 358 #define SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR (_SYSRTC_GRP0_CTRL_CMP1CMOA_CLEAR << 6) /**< Shifted mode CLEAR for SYSRTC_GRP0_CTRL */ 359 #define SYSRTC_GRP0_CTRL_CMP1CMOA_SET (_SYSRTC_GRP0_CTRL_CMP1CMOA_SET << 6) /**< Shifted mode SET for SYSRTC_GRP0_CTRL */ 360 #define SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE (_SYSRTC_GRP0_CTRL_CMP1CMOA_PULSE << 6) /**< Shifted mode PULSE for SYSRTC_GRP0_CTRL */ 361 #define SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE (_SYSRTC_GRP0_CTRL_CMP1CMOA_TOGGLE << 6) /**< Shifted mode TOGGLE for SYSRTC_GRP0_CTRL */ 362 #define SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF (_SYSRTC_GRP0_CTRL_CMP1CMOA_CMPIF << 6) /**< Shifted mode CMPIF for SYSRTC_GRP0_CTRL */ 363 #define _SYSRTC_GRP0_CTRL_CAP0EDGE_SHIFT 9 /**< Shift value for SYSRTC_CAP0EDGE */ 364 #define _SYSRTC_GRP0_CTRL_CAP0EDGE_MASK 0x600UL /**< Bit mask for SYSRTC_CAP0EDGE */ 365 #define _SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CTRL */ 366 #define _SYSRTC_GRP0_CTRL_CAP0EDGE_RISING 0x00000000UL /**< Mode RISING for SYSRTC_GRP0_CTRL */ 367 #define _SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING 0x00000001UL /**< Mode FALLING for SYSRTC_GRP0_CTRL */ 368 #define _SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH 0x00000002UL /**< Mode BOTH for SYSRTC_GRP0_CTRL */ 369 #define SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT (_SYSRTC_GRP0_CTRL_CAP0EDGE_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CTRL */ 370 #define SYSRTC_GRP0_CTRL_CAP0EDGE_RISING (_SYSRTC_GRP0_CTRL_CAP0EDGE_RISING << 9) /**< Shifted mode RISING for SYSRTC_GRP0_CTRL */ 371 #define SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING (_SYSRTC_GRP0_CTRL_CAP0EDGE_FALLING << 9) /**< Shifted mode FALLING for SYSRTC_GRP0_CTRL */ 372 #define SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH (_SYSRTC_GRP0_CTRL_CAP0EDGE_BOTH << 9) /**< Shifted mode BOTH for SYSRTC_GRP0_CTRL */ 373 374 /* Bit fields for SYSRTC GRP0_CMP0VALUE */ 375 #define _SYSRTC_GRP0_CMP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP0VALUE */ 376 #define _SYSRTC_GRP0_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP0VALUE */ 377 #define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP0VALUE */ 378 #define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP0VALUE */ 379 #define _SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP0VALUE */ 380 #define SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_CMP0VALUE_CMP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP0VALUE*/ 381 382 /* Bit fields for SYSRTC GRP0_CMP1VALUE */ 383 #define _SYSRTC_GRP0_CMP1VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CMP1VALUE */ 384 #define _SYSRTC_GRP0_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CMP1VALUE */ 385 #define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_SHIFT 0 /**< Shift value for SYSRTC_CMP1VALUE */ 386 #define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CMP1VALUE */ 387 #define _SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CMP1VALUE */ 388 #define SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_CMP1VALUE_CMP1VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CMP1VALUE*/ 389 390 /* Bit fields for SYSRTC GRP0_CAP0VALUE */ 391 #define _SYSRTC_GRP0_CAP0VALUE_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_CAP0VALUE */ 392 #define _SYSRTC_GRP0_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Mask for SYSRTC_GRP0_CAP0VALUE */ 393 #define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_SHIFT 0 /**< Shift value for SYSRTC_CAP0VALUE */ 394 #define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for SYSRTC_CAP0VALUE */ 395 #define _SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_CAP0VALUE */ 396 #define SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT (_SYSRTC_GRP0_CAP0VALUE_CAP0VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_CAP0VALUE*/ 397 398 /* Bit fields for SYSRTC GRP0_SYNCBUSY */ 399 #define _SYSRTC_GRP0_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for SYSRTC_GRP0_SYNCBUSY */ 400 #define _SYSRTC_GRP0_SYNCBUSY_MASK 0x00000007UL /**< Mask for SYSRTC_GRP0_SYNCBUSY */ 401 #define SYSRTC_GRP0_SYNCBUSY_CTRL (0x1UL << 0) /**< Sync busy for CTRL register */ 402 #define _SYSRTC_GRP0_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for SYSRTC_CTRL */ 403 #define _SYSRTC_GRP0_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for SYSRTC_CTRL */ 404 #define _SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ 405 #define SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ 406 #define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE (0x1UL << 1) /**< Sync busy for CMP0VALUE register */ 407 #define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_SHIFT 1 /**< Shift value for SYSRTC_CMP0VALUE */ 408 #define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_MASK 0x2UL /**< Bit mask for SYSRTC_CMP0VALUE */ 409 #define _SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ 410 #define SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP0VALUE_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ 411 #define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE (0x1UL << 2) /**< Sync busy for CMP1VALUE register */ 412 #define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_SHIFT 2 /**< Shift value for SYSRTC_CMP1VALUE */ 413 #define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_MASK 0x4UL /**< Bit mask for SYSRTC_CMP1VALUE */ 414 #define _SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSRTC_GRP0_SYNCBUSY */ 415 #define SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT (_SYSRTC_GRP0_SYNCBUSY_CMP1VALUE_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSRTC_GRP0_SYNCBUSY*/ 416 417 /** @} End of group EFR32MG24_SYSRTC_BitFields */ 418 /** @} End of group EFR32MG24_SYSRTC */ 419 /** @} End of group Parts */ 420 421 #endif /* EFR32MG24_SYSRTC_H */ 422
