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Searched refs:_SMU_PPUPATD0_EMU_DEFAULT (Results 1 – 25 of 73) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_smu.h172 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
173 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_smu.h172 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
173 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_smu.h172 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
173 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_smu.h172 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
173 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_smu.h172 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
173 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 13) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h193 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
194 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b390f1024gl112.h7638 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
7639 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b390f512gl112.h7638 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
7639 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b110f1024iq64.h8415 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8416 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b510f1024gl120.h8446 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8447 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b510f1024gm64.h8446 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8447 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b510f1024gl112.h8446 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8447 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b530f512im64.h8446 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8447 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b530f512iq64.h8446 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8447 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b130f512gm64.h8415 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8416 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b130f512gq64.h8415 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8416 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b130f512im64.h8415 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8416 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b130f512iq64.h8415 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8416 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b530f512iq100.h8446 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8447 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
Defm32gg12b110f1024gm64.h8415 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
8416 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 14) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h198 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< Mode DEFAULT… macro
199 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 15) /**< Shifted mode…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG21/Include/
Defr32mg21_smu.h302 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000000UL /**< M… macro
303 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< S…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_smu.h302 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< M… macro
303 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< S…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_smu.h302 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< M… macro
303 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< S…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG24/Include/
Defr32mg24_smu.h302 #define _SMU_PPUPATD0_EMU_DEFAULT 0x00000001UL /**< Mo… macro
303 #define SMU_PPUPATD0_EMU_DEFAULT (_SMU_PPUPATD0_EMU_DEFAULT << 1) /**< Sh…

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