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Searched refs:_SMU_PPUFS_PERIPHID_TRNG0 (Results 1 – 25 of 69) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_smu.h339 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000026UL /**< Mode TRNG0 for… macro
376 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_smu.h339 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000026UL /**< Mode TRNG0 for… macro
376 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_smu.h355 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for… macro
395 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_smu.h355 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for… macro
395 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_smu.h355 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000027UL /**< Mode TRNG0 for… macro
395 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h458 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
515 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b390f1024gl112.h7892 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
7947 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b390f512gl112.h7892 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
7947 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b110f1024iq64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b510f1024gl120.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b510f1024gm64.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b510f1024gl112.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b530f512im64.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b530f512iq64.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b130f512gm64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b130f512gq64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b130f512im64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b130f512iq64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b530f512iq100.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b110f1024gm64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b110f1024gq64.h8657 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8710 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b510f1024iq100.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b510f1024gq64.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
Defm32gg12b510f1024il112.h8694 #define _SMU_PPUFS_PERIPHID_TRNG0 0x0000002EUL /**< Mode TRNG0 for… macro
8748 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h503 #define _SMU_PPUFS_PERIPHID_TRNG0 0x00000030UL /**< Mode TRNG0 for… macro
568 #define SMU_PPUFS_PERIPHID_TRNG0 (_SMU_PPUFS_PERIPHID_TRNG0 << 0) /**< Shifted mode T…

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