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Searched refs:_PDM_CFG0_CH1CLKPOL_NORMAL (Results 1 – 4 of 4) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG27/Include/
Defr32bg27_pdm.h271 #define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mod… macro
274 #define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shi…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG22/Include/
Defr32bg22_pdm.h271 #define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mod… macro
274 #define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shi…
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_pdm.h249 #define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mod… macro
252 #define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shi…
/hal_silabs-3.5.0/gecko/emlib/inc/
Dem_pdm.h122 …pdmCh1ClkPolarityRisingEdge = _PDM_CFG0_CH1CLKPOL_NORMAL, /**< Input data clocked on rising clock…