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Searched refs:_DMA_STATUS_STATE_WAITREQCLR (Results 1 – 25 of 35) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_dma.h103 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
115 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32hg321f32.h463 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
475 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32hg321f64.h463 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
475 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32hg108f32.h509 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
521 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32hg108f64.h509 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
521 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32hg308f32.h521 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
533 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32hg308f64.h521 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
533 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_dma.h111 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
123 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg360f128.h548 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
560 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg360f256.h548 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
560 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg360f64.h548 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
560 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg842f128.h628 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg840f256.h628 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg840f64.h628 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg842f256.h628 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg330f256.h636 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg330f64.h636 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg332f128.h636 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg332f256.h636 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg332f64.h636 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg840f128.h628 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg940f128.h641 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg940f256.h641 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg942f128.h641 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …
Defm32wg942f256.h641 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< … macro
653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< …

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