Home
last modified time | relevance | path

Searched refs:_DMA_STATUS_STATE_RDSRCENDPTR (Results 1 – 25 of 35) sorted by relevance

12

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_dma.h99 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
111 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32hg321f32.h459 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
471 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32hg321f64.h459 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
471 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32hg108f32.h505 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
517 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32hg108f64.h505 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
517 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32hg308f32.h517 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
529 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32hg308f64.h517 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
529 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_dma.h107 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
119 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg360f128.h544 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
556 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg360f256.h544 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
556 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg360f64.h544 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
556 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg842f128.h624 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
636 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg840f256.h624 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
636 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg840f64.h624 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
636 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg842f256.h624 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
636 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg330f256.h632 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
644 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg330f64.h632 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
644 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg332f128.h632 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
644 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg332f256.h632 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
644 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg332f64.h632 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
644 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg840f128.h624 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
636 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg940f128.h637 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
649 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg940f256.h637 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
649 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg942f128.h637 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
649 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …
Defm32wg942f256.h637 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< … macro
649 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< …

12