1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 BURTC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_BURTC_H 31 #define EFR32MG24_BURTC_H 32 #define BURTC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_BURTC BURTC 40 * @{ 41 * @brief EFR32MG24 BURTC Register Declaration. 42 *****************************************************************************/ 43 44 /** BURTC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t EN; /**< Module Enable Register */ 48 __IOM uint32_t CFG; /**< Configuration Register */ 49 __IOM uint32_t CMD; /**< Command Register */ 50 __IM uint32_t STATUS; /**< Status Register */ 51 __IOM uint32_t IF; /**< Interrupt Flag Register */ 52 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 53 __IOM uint32_t PRECNT; /**< Pre-Counter Value Register */ 54 __IOM uint32_t CNT; /**< Counter Value Register */ 55 __IOM uint32_t EM4WUEN; /**< EM4 wakeup request Enable Register */ 56 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 57 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 58 __IOM uint32_t COMP; /**< Compare Value Register */ 59 uint32_t RESERVED0[1011U]; /**< Reserved for future use */ 60 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 61 __IOM uint32_t EN_SET; /**< Module Enable Register */ 62 __IOM uint32_t CFG_SET; /**< Configuration Register */ 63 __IOM uint32_t CMD_SET; /**< Command Register */ 64 __IM uint32_t STATUS_SET; /**< Status Register */ 65 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 66 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 67 __IOM uint32_t PRECNT_SET; /**< Pre-Counter Value Register */ 68 __IOM uint32_t CNT_SET; /**< Counter Value Register */ 69 __IOM uint32_t EM4WUEN_SET; /**< EM4 wakeup request Enable Register */ 70 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 71 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 72 __IOM uint32_t COMP_SET; /**< Compare Value Register */ 73 uint32_t RESERVED1[1011U]; /**< Reserved for future use */ 74 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 75 __IOM uint32_t EN_CLR; /**< Module Enable Register */ 76 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 77 __IOM uint32_t CMD_CLR; /**< Command Register */ 78 __IM uint32_t STATUS_CLR; /**< Status Register */ 79 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 80 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 81 __IOM uint32_t PRECNT_CLR; /**< Pre-Counter Value Register */ 82 __IOM uint32_t CNT_CLR; /**< Counter Value Register */ 83 __IOM uint32_t EM4WUEN_CLR; /**< EM4 wakeup request Enable Register */ 84 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 85 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 86 __IOM uint32_t COMP_CLR; /**< Compare Value Register */ 87 uint32_t RESERVED2[1011U]; /**< Reserved for future use */ 88 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 89 __IOM uint32_t EN_TGL; /**< Module Enable Register */ 90 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 91 __IOM uint32_t CMD_TGL; /**< Command Register */ 92 __IM uint32_t STATUS_TGL; /**< Status Register */ 93 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 94 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 95 __IOM uint32_t PRECNT_TGL; /**< Pre-Counter Value Register */ 96 __IOM uint32_t CNT_TGL; /**< Counter Value Register */ 97 __IOM uint32_t EM4WUEN_TGL; /**< EM4 wakeup request Enable Register */ 98 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 99 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 100 __IOM uint32_t COMP_TGL; /**< Compare Value Register */ 101 } BURTC_TypeDef; 102 /** @} End of group EFR32MG24_BURTC */ 103 104 /**************************************************************************//** 105 * @addtogroup EFR32MG24_BURTC 106 * @{ 107 * @defgroup EFR32MG24_BURTC_BitFields BURTC Bit Fields 108 * @{ 109 *****************************************************************************/ 110 111 /* Bit fields for BURTC IPVERSION */ 112 #define _BURTC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BURTC_IPVERSION */ 113 #define _BURTC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BURTC_IPVERSION */ 114 #define _BURTC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BURTC_IPVERSION */ 115 #define _BURTC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_IPVERSION */ 116 #define _BURTC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_IPVERSION */ 117 #define BURTC_IPVERSION_IPVERSION_DEFAULT (_BURTC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IPVERSION */ 118 119 /* Bit fields for BURTC EN */ 120 #define _BURTC_EN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EN */ 121 #define _BURTC_EN_MASK 0x00000003UL /**< Mask for BURTC_EN */ 122 #define BURTC_EN_EN (0x1UL << 0) /**< BURTC Enable */ 123 #define _BURTC_EN_EN_SHIFT 0 /**< Shift value for BURTC_EN */ 124 #define _BURTC_EN_EN_MASK 0x1UL /**< Bit mask for BURTC_EN */ 125 #define _BURTC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ 126 #define BURTC_EN_EN_DEFAULT (_BURTC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EN */ 127 #define BURTC_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ 128 #define _BURTC_EN_DISABLING_SHIFT 1 /**< Shift value for BURTC_DISABLING */ 129 #define _BURTC_EN_DISABLING_MASK 0x2UL /**< Bit mask for BURTC_DISABLING */ 130 #define _BURTC_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EN */ 131 #define BURTC_EN_DISABLING_DEFAULT (_BURTC_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EN */ 132 133 /* Bit fields for BURTC CFG */ 134 #define _BURTC_CFG_RESETVALUE 0x00000000UL /**< Default value for BURTC_CFG */ 135 #define _BURTC_CFG_MASK 0x000000F3UL /**< Mask for BURTC_CFG */ 136 #define BURTC_CFG_DEBUGRUN (0x1UL << 0) /**< Debug Mode Run Enable */ 137 #define _BURTC_CFG_DEBUGRUN_SHIFT 0 /**< Shift value for BURTC_DEBUGRUN */ 138 #define _BURTC_CFG_DEBUGRUN_MASK 0x1UL /**< Bit mask for BURTC_DEBUGRUN */ 139 #define _BURTC_CFG_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ 140 #define _BURTC_CFG_DEBUGRUN_X0 0x00000000UL /**< Mode X0 for BURTC_CFG */ 141 #define _BURTC_CFG_DEBUGRUN_X1 0x00000001UL /**< Mode X1 for BURTC_CFG */ 142 #define BURTC_CFG_DEBUGRUN_DEFAULT (_BURTC_CFG_DEBUGRUN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CFG */ 143 #define BURTC_CFG_DEBUGRUN_X0 (_BURTC_CFG_DEBUGRUN_X0 << 0) /**< Shifted mode X0 for BURTC_CFG */ 144 #define BURTC_CFG_DEBUGRUN_X1 (_BURTC_CFG_DEBUGRUN_X1 << 0) /**< Shifted mode X1 for BURTC_CFG */ 145 #define BURTC_CFG_COMPTOP (0x1UL << 1) /**< Compare Channel is Top Value */ 146 #define _BURTC_CFG_COMPTOP_SHIFT 1 /**< Shift value for BURTC_COMPTOP */ 147 #define _BURTC_CFG_COMPTOP_MASK 0x2UL /**< Bit mask for BURTC_COMPTOP */ 148 #define _BURTC_CFG_COMPTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ 149 #define _BURTC_CFG_COMPTOP_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CFG */ 150 #define _BURTC_CFG_COMPTOP_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_CFG */ 151 #define BURTC_CFG_COMPTOP_DEFAULT (_BURTC_CFG_COMPTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CFG */ 152 #define BURTC_CFG_COMPTOP_DISABLE (_BURTC_CFG_COMPTOP_DISABLE << 1) /**< Shifted mode DISABLE for BURTC_CFG */ 153 #define BURTC_CFG_COMPTOP_ENABLE (_BURTC_CFG_COMPTOP_ENABLE << 1) /**< Shifted mode ENABLE for BURTC_CFG */ 154 #define _BURTC_CFG_CNTPRESC_SHIFT 4 /**< Shift value for BURTC_CNTPRESC */ 155 #define _BURTC_CFG_CNTPRESC_MASK 0xF0UL /**< Bit mask for BURTC_CNTPRESC */ 156 #define _BURTC_CFG_CNTPRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CFG */ 157 #define _BURTC_CFG_CNTPRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CFG */ 158 #define _BURTC_CFG_CNTPRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CFG */ 159 #define _BURTC_CFG_CNTPRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CFG */ 160 #define _BURTC_CFG_CNTPRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CFG */ 161 #define _BURTC_CFG_CNTPRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CFG */ 162 #define _BURTC_CFG_CNTPRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CFG */ 163 #define _BURTC_CFG_CNTPRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CFG */ 164 #define _BURTC_CFG_CNTPRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CFG */ 165 #define _BURTC_CFG_CNTPRESC_DIV256 0x00000008UL /**< Mode DIV256 for BURTC_CFG */ 166 #define _BURTC_CFG_CNTPRESC_DIV512 0x00000009UL /**< Mode DIV512 for BURTC_CFG */ 167 #define _BURTC_CFG_CNTPRESC_DIV1024 0x0000000AUL /**< Mode DIV1024 for BURTC_CFG */ 168 #define _BURTC_CFG_CNTPRESC_DIV2048 0x0000000BUL /**< Mode DIV2048 for BURTC_CFG */ 169 #define _BURTC_CFG_CNTPRESC_DIV4096 0x0000000CUL /**< Mode DIV4096 for BURTC_CFG */ 170 #define _BURTC_CFG_CNTPRESC_DIV8192 0x0000000DUL /**< Mode DIV8192 for BURTC_CFG */ 171 #define _BURTC_CFG_CNTPRESC_DIV16384 0x0000000EUL /**< Mode DIV16384 for BURTC_CFG */ 172 #define _BURTC_CFG_CNTPRESC_DIV32768 0x0000000FUL /**< Mode DIV32768 for BURTC_CFG */ 173 #define BURTC_CFG_CNTPRESC_DEFAULT (_BURTC_CFG_CNTPRESC_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CFG */ 174 #define BURTC_CFG_CNTPRESC_DIV1 (_BURTC_CFG_CNTPRESC_DIV1 << 4) /**< Shifted mode DIV1 for BURTC_CFG */ 175 #define BURTC_CFG_CNTPRESC_DIV2 (_BURTC_CFG_CNTPRESC_DIV2 << 4) /**< Shifted mode DIV2 for BURTC_CFG */ 176 #define BURTC_CFG_CNTPRESC_DIV4 (_BURTC_CFG_CNTPRESC_DIV4 << 4) /**< Shifted mode DIV4 for BURTC_CFG */ 177 #define BURTC_CFG_CNTPRESC_DIV8 (_BURTC_CFG_CNTPRESC_DIV8 << 4) /**< Shifted mode DIV8 for BURTC_CFG */ 178 #define BURTC_CFG_CNTPRESC_DIV16 (_BURTC_CFG_CNTPRESC_DIV16 << 4) /**< Shifted mode DIV16 for BURTC_CFG */ 179 #define BURTC_CFG_CNTPRESC_DIV32 (_BURTC_CFG_CNTPRESC_DIV32 << 4) /**< Shifted mode DIV32 for BURTC_CFG */ 180 #define BURTC_CFG_CNTPRESC_DIV64 (_BURTC_CFG_CNTPRESC_DIV64 << 4) /**< Shifted mode DIV64 for BURTC_CFG */ 181 #define BURTC_CFG_CNTPRESC_DIV128 (_BURTC_CFG_CNTPRESC_DIV128 << 4) /**< Shifted mode DIV128 for BURTC_CFG */ 182 #define BURTC_CFG_CNTPRESC_DIV256 (_BURTC_CFG_CNTPRESC_DIV256 << 4) /**< Shifted mode DIV256 for BURTC_CFG */ 183 #define BURTC_CFG_CNTPRESC_DIV512 (_BURTC_CFG_CNTPRESC_DIV512 << 4) /**< Shifted mode DIV512 for BURTC_CFG */ 184 #define BURTC_CFG_CNTPRESC_DIV1024 (_BURTC_CFG_CNTPRESC_DIV1024 << 4) /**< Shifted mode DIV1024 for BURTC_CFG */ 185 #define BURTC_CFG_CNTPRESC_DIV2048 (_BURTC_CFG_CNTPRESC_DIV2048 << 4) /**< Shifted mode DIV2048 for BURTC_CFG */ 186 #define BURTC_CFG_CNTPRESC_DIV4096 (_BURTC_CFG_CNTPRESC_DIV4096 << 4) /**< Shifted mode DIV4096 for BURTC_CFG */ 187 #define BURTC_CFG_CNTPRESC_DIV8192 (_BURTC_CFG_CNTPRESC_DIV8192 << 4) /**< Shifted mode DIV8192 for BURTC_CFG */ 188 #define BURTC_CFG_CNTPRESC_DIV16384 (_BURTC_CFG_CNTPRESC_DIV16384 << 4) /**< Shifted mode DIV16384 for BURTC_CFG */ 189 #define BURTC_CFG_CNTPRESC_DIV32768 (_BURTC_CFG_CNTPRESC_DIV32768 << 4) /**< Shifted mode DIV32768 for BURTC_CFG */ 190 191 /* Bit fields for BURTC CMD */ 192 #define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ 193 #define _BURTC_CMD_MASK 0x00000003UL /**< Mask for BURTC_CMD */ 194 #define BURTC_CMD_START (0x1UL << 0) /**< Start BURTC counter */ 195 #define _BURTC_CMD_START_SHIFT 0 /**< Shift value for BURTC_START */ 196 #define _BURTC_CMD_START_MASK 0x1UL /**< Bit mask for BURTC_START */ 197 #define _BURTC_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ 198 #define BURTC_CMD_START_DEFAULT (_BURTC_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ 199 #define BURTC_CMD_STOP (0x1UL << 1) /**< Stop BURTC counter */ 200 #define _BURTC_CMD_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ 201 #define _BURTC_CMD_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ 202 #define _BURTC_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ 203 #define BURTC_CMD_STOP_DEFAULT (_BURTC_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_CMD */ 204 205 /* Bit fields for BURTC STATUS */ 206 #define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ 207 #define _BURTC_STATUS_MASK 0x00000003UL /**< Mask for BURTC_STATUS */ 208 #define BURTC_STATUS_RUNNING (0x1UL << 0) /**< BURTC running status */ 209 #define _BURTC_STATUS_RUNNING_SHIFT 0 /**< Shift value for BURTC_RUNNING */ 210 #define _BURTC_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for BURTC_RUNNING */ 211 #define _BURTC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ 212 #define BURTC_STATUS_RUNNING_DEFAULT (_BURTC_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ 213 #define BURTC_STATUS_LOCK (0x1UL << 1) /**< Configuration Lock Status */ 214 #define _BURTC_STATUS_LOCK_SHIFT 1 /**< Shift value for BURTC_LOCK */ 215 #define _BURTC_STATUS_LOCK_MASK 0x2UL /**< Bit mask for BURTC_LOCK */ 216 #define _BURTC_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ 217 #define _BURTC_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_STATUS */ 218 #define _BURTC_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_STATUS */ 219 #define BURTC_STATUS_LOCK_DEFAULT (_BURTC_STATUS_LOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ 220 #define BURTC_STATUS_LOCK_UNLOCKED (_BURTC_STATUS_LOCK_UNLOCKED << 1) /**< Shifted mode UNLOCKED for BURTC_STATUS */ 221 #define BURTC_STATUS_LOCK_LOCKED (_BURTC_STATUS_LOCK_LOCKED << 1) /**< Shifted mode LOCKED for BURTC_STATUS */ 222 223 /* Bit fields for BURTC IF */ 224 #define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ 225 #define _BURTC_IF_MASK 0x00000003UL /**< Mask for BURTC_IF */ 226 #define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 227 #define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ 228 #define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ 229 #define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ 230 #define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ 231 #define BURTC_IF_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ 232 #define _BURTC_IF_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ 233 #define _BURTC_IF_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ 234 #define _BURTC_IF_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ 235 #define BURTC_IF_COMP_DEFAULT (_BURTC_IF_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ 236 237 /* Bit fields for BURTC IEN */ 238 #define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ 239 #define _BURTC_IEN_MASK 0x00000003UL /**< Mask for BURTC_IEN */ 240 #define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ 241 #define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ 242 #define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ 243 #define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ 244 #define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ 245 #define BURTC_IEN_COMP (0x1UL << 1) /**< Compare Match Interrupt Flag */ 246 #define _BURTC_IEN_COMP_SHIFT 1 /**< Shift value for BURTC_COMP */ 247 #define _BURTC_IEN_COMP_MASK 0x2UL /**< Bit mask for BURTC_COMP */ 248 #define _BURTC_IEN_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ 249 #define BURTC_IEN_COMP_DEFAULT (_BURTC_IEN_COMP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ 250 251 /* Bit fields for BURTC PRECNT */ 252 #define _BURTC_PRECNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_PRECNT */ 253 #define _BURTC_PRECNT_MASK 0x00007FFFUL /**< Mask for BURTC_PRECNT */ 254 #define _BURTC_PRECNT_PRECNT_SHIFT 0 /**< Shift value for BURTC_PRECNT */ 255 #define _BURTC_PRECNT_PRECNT_MASK 0x7FFFUL /**< Bit mask for BURTC_PRECNT */ 256 #define _BURTC_PRECNT_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_PRECNT */ 257 #define BURTC_PRECNT_PRECNT_DEFAULT (_BURTC_PRECNT_PRECNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_PRECNT */ 258 259 /* Bit fields for BURTC CNT */ 260 #define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ 261 #define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ 262 #define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ 263 #define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ 264 #define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ 265 #define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ 266 267 /* Bit fields for BURTC EM4WUEN */ 268 #define _BURTC_EM4WUEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_EM4WUEN */ 269 #define _BURTC_EM4WUEN_MASK 0x00000003UL /**< Mask for BURTC_EM4WUEN */ 270 #define BURTC_EM4WUEN_OFEM4WUEN (0x1UL << 0) /**< Overflow EM4 Wakeup Enable */ 271 #define _BURTC_EM4WUEN_OFEM4WUEN_SHIFT 0 /**< Shift value for BURTC_OFEM4WUEN */ 272 #define _BURTC_EM4WUEN_OFEM4WUEN_MASK 0x1UL /**< Bit mask for BURTC_OFEM4WUEN */ 273 #define _BURTC_EM4WUEN_OFEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ 274 #define BURTC_EM4WUEN_OFEM4WUEN_DEFAULT (_BURTC_EM4WUEN_OFEM4WUEN_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ 275 #define BURTC_EM4WUEN_COMPEM4WUEN (0x1UL << 1) /**< Compare Match EM4 Wakeup Enable */ 276 #define _BURTC_EM4WUEN_COMPEM4WUEN_SHIFT 1 /**< Shift value for BURTC_COMPEM4WUEN */ 277 #define _BURTC_EM4WUEN_COMPEM4WUEN_MASK 0x2UL /**< Bit mask for BURTC_COMPEM4WUEN */ 278 #define _BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_EM4WUEN */ 279 #define BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT (_BURTC_EM4WUEN_COMPEM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_EM4WUEN */ 280 281 /* Bit fields for BURTC SYNCBUSY */ 282 #define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ 283 #define _BURTC_SYNCBUSY_MASK 0x0000001FUL /**< Mask for BURTC_SYNCBUSY */ 284 #define BURTC_SYNCBUSY_START (0x1UL << 0) /**< Sync busy for START */ 285 #define _BURTC_SYNCBUSY_START_SHIFT 0 /**< Shift value for BURTC_START */ 286 #define _BURTC_SYNCBUSY_START_MASK 0x1UL /**< Bit mask for BURTC_START */ 287 #define _BURTC_SYNCBUSY_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ 288 #define BURTC_SYNCBUSY_START_DEFAULT (_BURTC_SYNCBUSY_START_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ 289 #define BURTC_SYNCBUSY_STOP (0x1UL << 1) /**< Sync busy for STOP */ 290 #define _BURTC_SYNCBUSY_STOP_SHIFT 1 /**< Shift value for BURTC_STOP */ 291 #define _BURTC_SYNCBUSY_STOP_MASK 0x2UL /**< Bit mask for BURTC_STOP */ 292 #define _BURTC_SYNCBUSY_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ 293 #define BURTC_SYNCBUSY_STOP_DEFAULT (_BURTC_SYNCBUSY_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ 294 #define BURTC_SYNCBUSY_PRECNT (0x1UL << 2) /**< Sync busy for PRECNT */ 295 #define _BURTC_SYNCBUSY_PRECNT_SHIFT 2 /**< Shift value for BURTC_PRECNT */ 296 #define _BURTC_SYNCBUSY_PRECNT_MASK 0x4UL /**< Bit mask for BURTC_PRECNT */ 297 #define _BURTC_SYNCBUSY_PRECNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ 298 #define BURTC_SYNCBUSY_PRECNT_DEFAULT (_BURTC_SYNCBUSY_PRECNT_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ 299 #define BURTC_SYNCBUSY_CNT (0x1UL << 3) /**< Sync busy for CNT */ 300 #define _BURTC_SYNCBUSY_CNT_SHIFT 3 /**< Shift value for BURTC_CNT */ 301 #define _BURTC_SYNCBUSY_CNT_MASK 0x8UL /**< Bit mask for BURTC_CNT */ 302 #define _BURTC_SYNCBUSY_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ 303 #define BURTC_SYNCBUSY_CNT_DEFAULT (_BURTC_SYNCBUSY_CNT_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ 304 #define BURTC_SYNCBUSY_COMP (0x1UL << 4) /**< Sync busy for COMP */ 305 #define _BURTC_SYNCBUSY_COMP_SHIFT 4 /**< Shift value for BURTC_COMP */ 306 #define _BURTC_SYNCBUSY_COMP_MASK 0x10UL /**< Bit mask for BURTC_COMP */ 307 #define _BURTC_SYNCBUSY_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ 308 #define BURTC_SYNCBUSY_COMP_DEFAULT (_BURTC_SYNCBUSY_COMP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ 309 310 /* Bit fields for BURTC LOCK */ 311 #define _BURTC_LOCK_RESETVALUE 0x0000AEE8UL /**< Default value for BURTC_LOCK */ 312 #define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ 313 #define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ 314 #define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ 315 #define _BURTC_LOCK_LOCKKEY_DEFAULT 0x0000AEE8UL /**< Mode DEFAULT for BURTC_LOCK */ 316 #define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ 317 #define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ 318 #define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ 319 320 /* Bit fields for BURTC COMP */ 321 #define _BURTC_COMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP */ 322 #define _BURTC_COMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP */ 323 #define _BURTC_COMP_COMP_SHIFT 0 /**< Shift value for BURTC_COMP */ 324 #define _BURTC_COMP_COMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP */ 325 #define _BURTC_COMP_COMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP */ 326 #define BURTC_COMP_COMP_DEFAULT (_BURTC_COMP_COMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP */ 327 328 /** @} End of group EFR32MG24_BURTC_BitFields */ 329 /** @} End of group EFR32MG24_BURTC */ 330 /** @} End of group Parts */ 331 332 #endif /* EFR32MG24_BURTC_H */ 333
