1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 SYSCFG register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_SYSCFG_H 31 #define EFR32MG21_SYSCFG_H 32 #define SYSCFG_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG21_SYSCFG SYSCFG 40 * @{ 41 * @brief EFR32MG21 SYSCFG Register Declaration. 42 *****************************************************************************/ 43 44 /** SYSCFG Register Declaration. */ 45 typedef struct { 46 __IOM uint32_t IF; /**< Interrupt Flag Register */ 47 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 48 uint32_t RESERVED0[2U]; /**< Reserved for future use */ 49 __IOM uint32_t CHIPREVHW; /**< Hardwired Chip Rev values */ 50 __IOM uint32_t CHIPREV; /**< Part Family and Revision values */ 51 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 52 __IOM uint32_t CFGSYSTIC; /**< SysTick clock source */ 53 uint32_t RESERVED2[54U]; /**< Reserved for future use */ 54 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 55 uint32_t RESERVED4[63U]; /**< Reserved for future use */ 56 __IOM uint32_t CTRL; /**< Memory System Control Register */ 57 uint32_t RESERVED5[1U]; /**< Reserved for future use */ 58 __IOM uint32_t DMEM0RETNCTRL; /**< DMEM retention Control Register */ 59 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 60 __IM uint32_t DMEM0ECCADDR; /**< DMEM ECC Error Address Register */ 61 __IOM uint32_t DMEM0ECCCTRL; /**< DMEM ECC Control Register */ 62 __IOM uint32_t DMEM0RAMCTRL; /**< DMEM Control enable Register */ 63 uint32_t RESERVED7[121U]; /**< Reserved for future use */ 64 __IOM uint32_t RADIORAMRETNCTRL; /**< RADIO RAM Retention Control Register */ 65 uint32_t RESERVED8[1U]; /**< Reserved for future use */ 66 __IOM uint32_t RADIOECCCTRL; /**< RADIO RAM ECC Control Register */ 67 __IOM uint32_t RADIORAMCTRL; /**< RADIO RAM Control Register */ 68 __IM uint32_t SEQRAMECCADDR; /**< SEQRAM ECC Error Address Register */ 69 __IM uint32_t FRCRAMECCADDR; /**< FRCRAM ECC Error Address Register */ 70 uint32_t RESERVED9[762U]; /**< Reserved for future use */ 71 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 72 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 73 uint32_t RESERVED10[2U]; /**< Reserved for future use */ 74 __IOM uint32_t CHIPREVHW_SET; /**< Hardwired Chip Rev values */ 75 __IOM uint32_t CHIPREV_SET; /**< Part Family and Revision values */ 76 uint32_t RESERVED11[3U]; /**< Reserved for future use */ 77 __IOM uint32_t CFGSYSTIC_SET; /**< SysTick clock source */ 78 uint32_t RESERVED12[54U]; /**< Reserved for future use */ 79 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 80 uint32_t RESERVED14[63U]; /**< Reserved for future use */ 81 __IOM uint32_t CTRL_SET; /**< Memory System Control Register */ 82 uint32_t RESERVED15[1U]; /**< Reserved for future use */ 83 __IOM uint32_t DMEM0RETNCTRL_SET; /**< DMEM retention Control Register */ 84 uint32_t RESERVED16[1U]; /**< Reserved for future use */ 85 __IM uint32_t DMEM0ECCADDR_SET; /**< DMEM ECC Error Address Register */ 86 __IOM uint32_t DMEM0ECCCTRL_SET; /**< DMEM ECC Control Register */ 87 __IOM uint32_t DMEM0RAMCTRL_SET; /**< DMEM Control enable Register */ 88 uint32_t RESERVED17[121U]; /**< Reserved for future use */ 89 __IOM uint32_t RADIORAMRETNCTRL_SET; /**< RADIO RAM Retention Control Register */ 90 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 91 __IOM uint32_t RADIOECCCTRL_SET; /**< RADIO RAM ECC Control Register */ 92 __IOM uint32_t RADIORAMCTRL_SET; /**< RADIO RAM Control Register */ 93 __IM uint32_t SEQRAMECCADDR_SET; /**< SEQRAM ECC Error Address Register */ 94 __IM uint32_t FRCRAMECCADDR_SET; /**< FRCRAM ECC Error Address Register */ 95 uint32_t RESERVED19[762U]; /**< Reserved for future use */ 96 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 97 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 98 uint32_t RESERVED20[2U]; /**< Reserved for future use */ 99 __IOM uint32_t CHIPREVHW_CLR; /**< Hardwired Chip Rev values */ 100 __IOM uint32_t CHIPREV_CLR; /**< Part Family and Revision values */ 101 uint32_t RESERVED21[3U]; /**< Reserved for future use */ 102 __IOM uint32_t CFGSYSTIC_CLR; /**< SysTick clock source */ 103 uint32_t RESERVED22[54U]; /**< Reserved for future use */ 104 uint32_t RESERVED23[1U]; /**< Reserved for future use */ 105 uint32_t RESERVED24[63U]; /**< Reserved for future use */ 106 __IOM uint32_t CTRL_CLR; /**< Memory System Control Register */ 107 uint32_t RESERVED25[1U]; /**< Reserved for future use */ 108 __IOM uint32_t DMEM0RETNCTRL_CLR; /**< DMEM retention Control Register */ 109 uint32_t RESERVED26[1U]; /**< Reserved for future use */ 110 __IM uint32_t DMEM0ECCADDR_CLR; /**< DMEM ECC Error Address Register */ 111 __IOM uint32_t DMEM0ECCCTRL_CLR; /**< DMEM ECC Control Register */ 112 __IOM uint32_t DMEM0RAMCTRL_CLR; /**< DMEM Control enable Register */ 113 uint32_t RESERVED27[121U]; /**< Reserved for future use */ 114 __IOM uint32_t RADIORAMRETNCTRL_CLR; /**< RADIO RAM Retention Control Register */ 115 uint32_t RESERVED28[1U]; /**< Reserved for future use */ 116 __IOM uint32_t RADIOECCCTRL_CLR; /**< RADIO RAM ECC Control Register */ 117 __IOM uint32_t RADIORAMCTRL_CLR; /**< RADIO RAM Control Register */ 118 __IM uint32_t SEQRAMECCADDR_CLR; /**< SEQRAM ECC Error Address Register */ 119 __IM uint32_t FRCRAMECCADDR_CLR; /**< FRCRAM ECC Error Address Register */ 120 uint32_t RESERVED29[762U]; /**< Reserved for future use */ 121 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 122 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 123 uint32_t RESERVED30[2U]; /**< Reserved for future use */ 124 __IOM uint32_t CHIPREVHW_TGL; /**< Hardwired Chip Rev values */ 125 __IOM uint32_t CHIPREV_TGL; /**< Part Family and Revision values */ 126 uint32_t RESERVED31[3U]; /**< Reserved for future use */ 127 __IOM uint32_t CFGSYSTIC_TGL; /**< SysTick clock source */ 128 uint32_t RESERVED32[54U]; /**< Reserved for future use */ 129 uint32_t RESERVED33[1U]; /**< Reserved for future use */ 130 uint32_t RESERVED34[63U]; /**< Reserved for future use */ 131 __IOM uint32_t CTRL_TGL; /**< Memory System Control Register */ 132 uint32_t RESERVED35[1U]; /**< Reserved for future use */ 133 __IOM uint32_t DMEM0RETNCTRL_TGL; /**< DMEM retention Control Register */ 134 uint32_t RESERVED36[1U]; /**< Reserved for future use */ 135 __IM uint32_t DMEM0ECCADDR_TGL; /**< DMEM ECC Error Address Register */ 136 __IOM uint32_t DMEM0ECCCTRL_TGL; /**< DMEM ECC Control Register */ 137 __IOM uint32_t DMEM0RAMCTRL_TGL; /**< DMEM Control enable Register */ 138 uint32_t RESERVED37[121U]; /**< Reserved for future use */ 139 __IOM uint32_t RADIORAMRETNCTRL_TGL; /**< RADIO RAM Retention Control Register */ 140 uint32_t RESERVED38[1U]; /**< Reserved for future use */ 141 __IOM uint32_t RADIOECCCTRL_TGL; /**< RADIO RAM ECC Control Register */ 142 __IOM uint32_t RADIORAMCTRL_TGL; /**< RADIO RAM Control Register */ 143 __IM uint32_t SEQRAMECCADDR_TGL; /**< SEQRAM ECC Error Address Register */ 144 __IM uint32_t FRCRAMECCADDR_TGL; /**< FRCRAM ECC Error Address Register */ 145 } SYSCFG_TypeDef; 146 /** @} End of group EFR32MG21_SYSCFG */ 147 148 /**************************************************************************//** 149 * @addtogroup EFR32MG21_SYSCFG 150 * @{ 151 * @defgroup EFR32MG21_SYSCFG_BitFields SYSCFG Bit Fields 152 * @{ 153 *****************************************************************************/ 154 155 /* Bit fields for SYSCFG IF */ 156 #define _SYSCFG_IF_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IF */ 157 #define _SYSCFG_IF_MASK 0x3303000FUL /**< Mask for SYSCFG_IF */ 158 #define SYSCFG_IF_SW0 (0x1UL << 0) /**< Software Interrupt 0 */ 159 #define _SYSCFG_IF_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ 160 #define _SYSCFG_IF_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ 161 #define _SYSCFG_IF_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 162 #define SYSCFG_IF_SW0_DEFAULT (_SYSCFG_IF_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IF */ 163 #define SYSCFG_IF_SW1 (0x1UL << 1) /**< Software Interrupt 1 */ 164 #define _SYSCFG_IF_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ 165 #define _SYSCFG_IF_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ 166 #define _SYSCFG_IF_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 167 #define SYSCFG_IF_SW1_DEFAULT (_SYSCFG_IF_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IF */ 168 #define SYSCFG_IF_SW2 (0x1UL << 2) /**< Software Interrupt 2 */ 169 #define _SYSCFG_IF_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ 170 #define _SYSCFG_IF_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ 171 #define _SYSCFG_IF_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 172 #define SYSCFG_IF_SW2_DEFAULT (_SYSCFG_IF_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IF */ 173 #define SYSCFG_IF_SW3 (0x1UL << 3) /**< Software Interrupt 3 */ 174 #define _SYSCFG_IF_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ 175 #define _SYSCFG_IF_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ 176 #define _SYSCFG_IF_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 177 #define SYSCFG_IF_SW3_DEFAULT (_SYSCFG_IF_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IF */ 178 #define SYSCFG_IF_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt flag */ 179 #define _SYSCFG_IF_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ 180 #define _SYSCFG_IF_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ 181 #define _SYSCFG_IF_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 182 #define SYSCFG_IF_RAMERR1B_DEFAULT (_SYSCFG_IF_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IF */ 183 #define SYSCFG_IF_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt flag */ 184 #define _SYSCFG_IF_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ 185 #define _SYSCFG_IF_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ 186 #define _SYSCFG_IF_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 187 #define SYSCFG_IF_RAMERR2B_DEFAULT (_SYSCFG_IF_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IF */ 188 #define SYSCFG_IF_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-bit ECC Error Interrupt flag */ 189 #define _SYSCFG_IF_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ 190 #define _SYSCFG_IF_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ 191 #define _SYSCFG_IF_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 192 #define SYSCFG_IF_SEQRAMERR1B_DEFAULT (_SYSCFG_IF_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IF */ 193 #define SYSCFG_IF_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-bit ECC Error Interrupt flag */ 194 #define _SYSCFG_IF_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ 195 #define _SYSCFG_IF_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ 196 #define _SYSCFG_IF_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 197 #define SYSCFG_IF_SEQRAMERR2B_DEFAULT (_SYSCFG_IF_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IF */ 198 #define SYSCFG_IF_FRCRAMERR1BIF (0x1UL << 28) /**< FRCRAM 1-bit ECC Error Interrupt flag */ 199 #define _SYSCFG_IF_FRCRAMERR1BIF_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1BIF */ 200 #define _SYSCFG_IF_FRCRAMERR1BIF_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1BIF */ 201 #define _SYSCFG_IF_FRCRAMERR1BIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 202 #define SYSCFG_IF_FRCRAMERR1BIF_DEFAULT (_SYSCFG_IF_FRCRAMERR1BIF_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IF */ 203 #define SYSCFG_IF_FRCRAMERR2BIF (0x1UL << 29) /**< FRCRAM 2-bit ECC Error Interrupt flag */ 204 #define _SYSCFG_IF_FRCRAMERR2BIF_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2BIF */ 205 #define _SYSCFG_IF_FRCRAMERR2BIF_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2BIF */ 206 #define _SYSCFG_IF_FRCRAMERR2BIF_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IF */ 207 #define SYSCFG_IF_FRCRAMERR2BIF_DEFAULT (_SYSCFG_IF_FRCRAMERR2BIF_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IF */ 208 209 /* Bit fields for SYSCFG IEN */ 210 #define _SYSCFG_IEN_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_IEN */ 211 #define _SYSCFG_IEN_MASK 0x3303000FUL /**< Mask for SYSCFG_IEN */ 212 #define SYSCFG_IEN_SW0 (0x1UL << 0) /**< Software Interrupt 0 */ 213 #define _SYSCFG_IEN_SW0_SHIFT 0 /**< Shift value for SYSCFG_SW0 */ 214 #define _SYSCFG_IEN_SW0_MASK 0x1UL /**< Bit mask for SYSCFG_SW0 */ 215 #define _SYSCFG_IEN_SW0_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 216 #define SYSCFG_IEN_SW0_DEFAULT (_SYSCFG_IEN_SW0_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 217 #define SYSCFG_IEN_SW1 (0x1UL << 1) /**< Software Interrupt 1 */ 218 #define _SYSCFG_IEN_SW1_SHIFT 1 /**< Shift value for SYSCFG_SW1 */ 219 #define _SYSCFG_IEN_SW1_MASK 0x2UL /**< Bit mask for SYSCFG_SW1 */ 220 #define _SYSCFG_IEN_SW1_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 221 #define SYSCFG_IEN_SW1_DEFAULT (_SYSCFG_IEN_SW1_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 222 #define SYSCFG_IEN_SW2 (0x1UL << 2) /**< Software Interrupt 2 */ 223 #define _SYSCFG_IEN_SW2_SHIFT 2 /**< Shift value for SYSCFG_SW2 */ 224 #define _SYSCFG_IEN_SW2_MASK 0x4UL /**< Bit mask for SYSCFG_SW2 */ 225 #define _SYSCFG_IEN_SW2_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 226 #define SYSCFG_IEN_SW2_DEFAULT (_SYSCFG_IEN_SW2_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 227 #define SYSCFG_IEN_SW3 (0x1UL << 3) /**< Software Interrupt 3 */ 228 #define _SYSCFG_IEN_SW3_SHIFT 3 /**< Shift value for SYSCFG_SW3 */ 229 #define _SYSCFG_IEN_SW3_MASK 0x8UL /**< Bit mask for SYSCFG_SW3 */ 230 #define _SYSCFG_IEN_SW3_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 231 #define SYSCFG_IEN_SW3_DEFAULT (_SYSCFG_IEN_SW3_DEFAULT << 3) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 232 #define SYSCFG_IEN_RAMERR1B (0x1UL << 16) /**< RAM 1-bit ECC Error Interrupt enable */ 233 #define _SYSCFG_IEN_RAMERR1B_SHIFT 16 /**< Shift value for SYSCFG_RAMERR1B */ 234 #define _SYSCFG_IEN_RAMERR1B_MASK 0x10000UL /**< Bit mask for SYSCFG_RAMERR1B */ 235 #define _SYSCFG_IEN_RAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 236 #define SYSCFG_IEN_RAMERR1B_DEFAULT (_SYSCFG_IEN_RAMERR1B_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 237 #define SYSCFG_IEN_RAMERR2B (0x1UL << 17) /**< RAM 2-bit ECC Error Interrupt enable */ 238 #define _SYSCFG_IEN_RAMERR2B_SHIFT 17 /**< Shift value for SYSCFG_RAMERR2B */ 239 #define _SYSCFG_IEN_RAMERR2B_MASK 0x20000UL /**< Bit mask for SYSCFG_RAMERR2B */ 240 #define _SYSCFG_IEN_RAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 241 #define SYSCFG_IEN_RAMERR2B_DEFAULT (_SYSCFG_IEN_RAMERR2B_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 242 #define SYSCFG_IEN_SEQRAMERR1B (0x1UL << 24) /**< SEQRAM 1-bit ECC Error Interrupt enable */ 243 #define _SYSCFG_IEN_SEQRAMERR1B_SHIFT 24 /**< Shift value for SYSCFG_SEQRAMERR1B */ 244 #define _SYSCFG_IEN_SEQRAMERR1B_MASK 0x1000000UL /**< Bit mask for SYSCFG_SEQRAMERR1B */ 245 #define _SYSCFG_IEN_SEQRAMERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 246 #define SYSCFG_IEN_SEQRAMERR1B_DEFAULT (_SYSCFG_IEN_SEQRAMERR1B_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 247 #define SYSCFG_IEN_SEQRAMERR2B (0x1UL << 25) /**< SEQRAM 2-bit ECC Error Interrupt enable */ 248 #define _SYSCFG_IEN_SEQRAMERR2B_SHIFT 25 /**< Shift value for SYSCFG_SEQRAMERR2B */ 249 #define _SYSCFG_IEN_SEQRAMERR2B_MASK 0x2000000UL /**< Bit mask for SYSCFG_SEQRAMERR2B */ 250 #define _SYSCFG_IEN_SEQRAMERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 251 #define SYSCFG_IEN_SEQRAMERR2B_DEFAULT (_SYSCFG_IEN_SEQRAMERR2B_DEFAULT << 25) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 252 #define SYSCFG_IEN_FRCRAMERR1BIEN (0x1UL << 28) /**< FRCRAM 1-bit ECC Error Interrupt enable */ 253 #define _SYSCFG_IEN_FRCRAMERR1BIEN_SHIFT 28 /**< Shift value for SYSCFG_FRCRAMERR1BIEN */ 254 #define _SYSCFG_IEN_FRCRAMERR1BIEN_MASK 0x10000000UL /**< Bit mask for SYSCFG_FRCRAMERR1BIEN */ 255 #define _SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 256 #define SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT (_SYSCFG_IEN_FRCRAMERR1BIEN_DEFAULT << 28) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 257 #define SYSCFG_IEN_FRCRAMERR2BIEN (0x1UL << 29) /**< FRCRAM 2-bit ECC Error Interrupt enable */ 258 #define _SYSCFG_IEN_FRCRAMERR2BIEN_SHIFT 29 /**< Shift value for SYSCFG_FRCRAMERR2BIEN */ 259 #define _SYSCFG_IEN_FRCRAMERR2BIEN_MASK 0x20000000UL /**< Bit mask for SYSCFG_FRCRAMERR2BIEN */ 260 #define _SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_IEN */ 261 #define SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT (_SYSCFG_IEN_FRCRAMERR2BIEN_DEFAULT << 29) /**< Shifted mode DEFAULT for SYSCFG_IEN */ 262 263 /* Bit fields for SYSCFG CHIPREVHW */ 264 #define _SYSCFG_CHIPREVHW_RESETVALUE 0x00000001UL /**< Default value for SYSCFG_CHIPREVHW */ 265 #define _SYSCFG_CHIPREVHW_MASK 0xFF0FFFFFUL /**< Mask for SYSCFG_CHIPREVHW */ 266 #define _SYSCFG_CHIPREVHW_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ 267 #define _SYSCFG_CHIPREVHW_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ 268 #define _SYSCFG_CHIPREVHW_MAJOR_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 269 #define SYSCFG_CHIPREVHW_MAJOR_DEFAULT (_SYSCFG_CHIPREVHW_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 270 #define _SYSCFG_CHIPREVHW_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ 271 #define _SYSCFG_CHIPREVHW_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ 272 #define _SYSCFG_CHIPREVHW_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 273 #define SYSCFG_CHIPREVHW_FAMILY_DEFAULT (_SYSCFG_CHIPREVHW_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 274 #define _SYSCFG_CHIPREVHW_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ 275 #define _SYSCFG_CHIPREVHW_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ 276 #define _SYSCFG_CHIPREVHW_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREVHW */ 277 #define SYSCFG_CHIPREVHW_MINOR_DEFAULT (_SYSCFG_CHIPREVHW_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREVHW */ 278 279 /* Bit fields for SYSCFG CHIPREV */ 280 #define _SYSCFG_CHIPREV_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CHIPREV */ 281 #define _SYSCFG_CHIPREV_MASK 0x000FFFFFUL /**< Mask for SYSCFG_CHIPREV */ 282 #define _SYSCFG_CHIPREV_MAJOR_SHIFT 0 /**< Shift value for SYSCFG_MAJOR */ 283 #define _SYSCFG_CHIPREV_MAJOR_MASK 0x3FUL /**< Bit mask for SYSCFG_MAJOR */ 284 #define _SYSCFG_CHIPREV_MAJOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 285 #define SYSCFG_CHIPREV_MAJOR_DEFAULT (_SYSCFG_CHIPREV_MAJOR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 286 #define _SYSCFG_CHIPREV_FAMILY_SHIFT 6 /**< Shift value for SYSCFG_FAMILY */ 287 #define _SYSCFG_CHIPREV_FAMILY_MASK 0xFC0UL /**< Bit mask for SYSCFG_FAMILY */ 288 #define _SYSCFG_CHIPREV_FAMILY_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 289 #define SYSCFG_CHIPREV_FAMILY_DEFAULT (_SYSCFG_CHIPREV_FAMILY_DEFAULT << 6) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 290 #define _SYSCFG_CHIPREV_MINOR_SHIFT 12 /**< Shift value for SYSCFG_MINOR */ 291 #define _SYSCFG_CHIPREV_MINOR_MASK 0xFF000UL /**< Bit mask for SYSCFG_MINOR */ 292 #define _SYSCFG_CHIPREV_MINOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CHIPREV */ 293 #define SYSCFG_CHIPREV_MINOR_DEFAULT (_SYSCFG_CHIPREV_MINOR_DEFAULT << 12) /**< Shifted mode DEFAULT for SYSCFG_CHIPREV */ 294 295 /* Bit fields for SYSCFG CFGSYSTIC */ 296 #define _SYSCFG_CFGSYSTIC_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_CFGSYSTIC */ 297 #define _SYSCFG_CFGSYSTIC_MASK 0x00000003UL /**< Mask for SYSCFG_CFGSYSTIC */ 298 #define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN (0x1UL << 0) /**< SysTick External Clock Enable */ 299 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_SHIFT 0 /**< Shift value for SYSCFG_SYSTICEXTCLKEN */ 300 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_MASK 0x1UL /**< Bit mask for SYSCFG_SYSTICEXTCLKEN */ 301 #define _SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_CFGSYSTIC */ 302 #define SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT (_SYSCFG_CFGSYSTIC_SYSTICEXTCLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CFGSYSTIC */ 303 304 /* Bit fields for SYSCFG CTRL */ 305 #define _SYSCFG_CTRL_RESETVALUE 0x00000021UL /**< Default value for SYSCFG_CTRL */ 306 #define _SYSCFG_CTRL_MASK 0x00000021UL /**< Mask for SYSCFG_CTRL */ 307 #define SYSCFG_CTRL_ADDRFAULTEN (0x1UL << 0) /**< Invalid Address Bus Fault Response Enable */ 308 #define _SYSCFG_CTRL_ADDRFAULTEN_SHIFT 0 /**< Shift value for SYSCFG_ADDRFAULTEN */ 309 #define _SYSCFG_CTRL_ADDRFAULTEN_MASK 0x1UL /**< Bit mask for SYSCFG_ADDRFAULTEN */ 310 #define _SYSCFG_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 311 #define SYSCFG_CTRL_ADDRFAULTEN_DEFAULT (_SYSCFG_CTRL_ADDRFAULTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 312 #define SYSCFG_CTRL_RAMECCERRFAULTEN (0x1UL << 5) /**< Two bit ECC Error Bus Fault Response Enable */ 313 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_SHIFT 5 /**< Shift value for SYSCFG_RAMECCERRFAULTEN */ 314 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_MASK 0x20UL /**< Bit mask for SYSCFG_RAMECCERRFAULTEN */ 315 #define _SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for SYSCFG_CTRL */ 316 #define SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT (_SYSCFG_CTRL_RAMECCERRFAULTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for SYSCFG_CTRL */ 317 318 /* Bit fields for SYSCFG DMEM0RETNCTRL */ 319 #define _SYSCFG_DMEM0RETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RETNCTRL */ 320 #define _SYSCFG_DMEM0RETNCTRL_MASK 0x0000001FUL /**< Mask for SYSCFG_DMEM0RETNCTRL */ 321 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_RAMRETNCTRL */ 322 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_MASK 0x1FUL /**< Bit mask for SYSCFG_RAMRETNCTRL */ 323 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RETNCTRL */ 324 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_DMEM0RETNCTRL */ 325 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5 0x00000010UL /**< Mode BLK5 for SYSCFG_DMEM0RETNCTRL */ 326 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO5 0x00000018UL /**< Mode BLK4TO5 for SYSCFG_DMEM0RETNCTRL */ 327 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO5 0x0000001CUL /**< Mode BLK3TO5 for SYSCFG_DMEM0RETNCTRL */ 328 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO5 0x0000001EUL /**< Mode BLK2TO5 for SYSCFG_DMEM0RETNCTRL */ 329 #define _SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO5 0x0000001FUL /**< Mode BLK1TO5 for SYSCFG_DMEM0RETNCTRL */ 330 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RETNCTRL*/ 331 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_DMEM0RETNCTRL */ 332 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK5 << 0) /**< Shifted mode BLK5 for SYSCFG_DMEM0RETNCTRL */ 333 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO5 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK4TO5 << 0) /**< Shifted mode BLK4TO5 for SYSCFG_DMEM0RETNCTRL*/ 334 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO5 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK3TO5 << 0) /**< Shifted mode BLK3TO5 for SYSCFG_DMEM0RETNCTRL*/ 335 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO5 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK2TO5 << 0) /**< Shifted mode BLK2TO5 for SYSCFG_DMEM0RETNCTRL*/ 336 #define SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO5 (_SYSCFG_DMEM0RETNCTRL_RAMRETNCTRL_BLK1TO5 << 0) /**< Shifted mode BLK1TO5 for SYSCFG_DMEM0RETNCTRL*/ 337 338 /* Bit fields for SYSCFG DMEM0ECCADDR */ 339 #define _SYSCFG_DMEM0ECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCADDR */ 340 #define _SYSCFG_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_DMEM0ECCADDR */ 341 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_SHIFT 0 /**< Shift value for SYSCFG_DMEM0ECCADDR */ 342 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_DMEM0ECCADDR */ 343 #define _SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCADDR */ 344 #define SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT (_SYSCFG_DMEM0ECCADDR_DMEM0ECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCADDR*/ 345 346 /* Bit fields for SYSCFG DMEM0ECCCTRL */ 347 #define _SYSCFG_DMEM0ECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0ECCCTRL */ 348 #define _SYSCFG_DMEM0ECCCTRL_MASK 0x00000003UL /**< Mask for SYSCFG_DMEM0ECCCTRL */ 349 #define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN (0x1UL << 0) /**< RAM ECC Write Enable */ 350 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_SHIFT 0 /**< Shift value for SYSCFG_RAMECCEWEN */ 351 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_MASK 0x1UL /**< Bit mask for SYSCFG_RAMECCEWEN */ 352 #define _SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ 353 #define SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ 354 #define SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN (0x1UL << 1) /**< RAM ECC Check Enable */ 355 #define _SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN_SHIFT 1 /**< Shift value for SYSCFG_RAMECCCHKEN */ 356 #define _SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN_MASK 0x2UL /**< Bit mask for SYSCFG_RAMECCCHKEN */ 357 #define _SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0ECCCTRL */ 358 #define SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN_DEFAULT (_SYSCFG_DMEM0ECCCTRL_RAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0ECCCTRL*/ 359 360 /* Bit fields for SYSCFG DMEM0RAMCTRL */ 361 #define _SYSCFG_DMEM0RAMCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_DMEM0RAMCTRL */ 362 #define _SYSCFG_DMEM0RAMCTRL_MASK 0x00000007UL /**< Mask for SYSCFG_DMEM0RAMCTRL */ 363 #define SYSCFG_DMEM0RAMCTRL_RAMCACHEEN (0x1UL << 0) /**< RAM CACHE Enable */ 364 #define _SYSCFG_DMEM0RAMCTRL_RAMCACHEEN_SHIFT 0 /**< Shift value for SYSCFG_RAMCACHEEN */ 365 #define _SYSCFG_DMEM0RAMCTRL_RAMCACHEEN_MASK 0x1UL /**< Bit mask for SYSCFG_RAMCACHEEN */ 366 #define _SYSCFG_DMEM0RAMCTRL_RAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RAMCTRL */ 367 #define SYSCFG_DMEM0RAMCTRL_RAMCACHEEN_DEFAULT (_SYSCFG_DMEM0RAMCTRL_RAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RAMCTRL*/ 368 #define SYSCFG_DMEM0RAMCTRL_RAMWSEN (0x1UL << 1) /**< RAM WAIT STATE Enable */ 369 #define _SYSCFG_DMEM0RAMCTRL_RAMWSEN_SHIFT 1 /**< Shift value for SYSCFG_RAMWSEN */ 370 #define _SYSCFG_DMEM0RAMCTRL_RAMWSEN_MASK 0x2UL /**< Bit mask for SYSCFG_RAMWSEN */ 371 #define _SYSCFG_DMEM0RAMCTRL_RAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RAMCTRL */ 372 #define SYSCFG_DMEM0RAMCTRL_RAMWSEN_DEFAULT (_SYSCFG_DMEM0RAMCTRL_RAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RAMCTRL*/ 373 #define SYSCFG_DMEM0RAMCTRL_RAMPREFETCHEN (0x1UL << 2) /**< RAM Prfetch Enable */ 374 #define _SYSCFG_DMEM0RAMCTRL_RAMPREFETCHEN_SHIFT 2 /**< Shift value for SYSCFG_RAMPREFETCHEN */ 375 #define _SYSCFG_DMEM0RAMCTRL_RAMPREFETCHEN_MASK 0x4UL /**< Bit mask for SYSCFG_RAMPREFETCHEN */ 376 #define _SYSCFG_DMEM0RAMCTRL_RAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_DMEM0RAMCTRL */ 377 #define SYSCFG_DMEM0RAMCTRL_RAMPREFETCHEN_DEFAULT (_SYSCFG_DMEM0RAMCTRL_RAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_DMEM0RAMCTRL*/ 378 379 /* Bit fields for SYSCFG RADIORAMRETNCTRL */ 380 #define _SYSCFG_RADIORAMRETNCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMRETNCTRL */ 381 #define _SYSCFG_RADIORAMRETNCTRL_MASK 0x00000101UL /**< Mask for SYSCFG_RADIORAMRETNCTRL */ 382 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL (0x1UL << 0) /**< SEQRAM Memory Shutdown Control Register */ 383 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMRETNCTRL */ 384 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMRETNCTRL */ 385 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ 386 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ 387 #define _SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SEQBLK 0x00000001UL /**< Mode SEQBLK for SYSCFG_RADIORAMRETNCTRL */ 388 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ 389 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_ALLON << 0) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ 390 #define SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SEQBLK (_SYSCFG_RADIORAMRETNCTRL_SEQRAMRETNCTRL_SEQBLK << 0) /**< Shifted mode SEQBLK for SYSCFG_RADIORAMRETNCTRL*/ 391 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL (0x1UL << 8) /**< FRCRAM Memory Shutdown Control Register */ 392 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMRETNCTRL */ 393 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMRETNCTRL */ 394 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMRETNCTRL */ 395 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON 0x00000000UL /**< Mode ALLON for SYSCFG_RADIORAMRETNCTRL */ 396 #define _SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_FRCBLK 0x00000001UL /**< Mode FRCBLK for SYSCFG_RADIORAMRETNCTRL */ 397 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMRETNCTRL*/ 398 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_ALLON << 8) /**< Shifted mode ALLON for SYSCFG_RADIORAMRETNCTRL*/ 399 #define SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_FRCBLK (_SYSCFG_RADIORAMRETNCTRL_FRCRAMRETNCTRL_FRCBLK << 8) /**< Shifted mode FRCBLK for SYSCFG_RADIORAMRETNCTRL*/ 400 401 /* Bit fields for SYSCFG RADIOECCCTRL */ 402 #define _SYSCFG_RADIOECCCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIOECCCTRL */ 403 #define _SYSCFG_RADIOECCCTRL_MASK 0x00000303UL /**< Mask for SYSCFG_RADIOECCCTRL */ 404 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN (0x1UL << 0) /**< SEQRAM ECC Write Enable */ 405 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCEWEN */ 406 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMECCEWEN */ 407 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 408 #define SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCEWEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 409 #define SYSCFG_RADIOECCCTRL_SEQRAMECCCHKEN (0x1UL << 1) /**< SEQRAM ECC Check Enable */ 410 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCCHKEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMECCCHKEN */ 411 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCCHKEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMECCCHKEN */ 412 #define _SYSCFG_RADIOECCCTRL_SEQRAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 413 #define SYSCFG_RADIOECCCTRL_SEQRAMECCCHKEN_DEFAULT (_SYSCFG_RADIOECCCTRL_SEQRAMECCCHKEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 414 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN (0x1UL << 8) /**< FRCRAM ECC Write Enable */ 415 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_SHIFT 8 /**< Shift value for SYSCFG_FRCRAMECCEWEN */ 416 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_MASK 0x100UL /**< Bit mask for SYSCFG_FRCRAMECCEWEN */ 417 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 418 #define SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCEWEN_DEFAULT << 8) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 419 #define SYSCFG_RADIOECCCTRL_FRCRAMECCCHKEN (0x1UL << 9) /**< FRCRAM ECC Check Enable */ 420 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCCHKEN_SHIFT 9 /**< Shift value for SYSCFG_FRCRAMECCCHKEN */ 421 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCCHKEN_MASK 0x200UL /**< Bit mask for SYSCFG_FRCRAMECCCHKEN */ 422 #define _SYSCFG_RADIOECCCTRL_FRCRAMECCCHKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIOECCCTRL */ 423 #define SYSCFG_RADIOECCCTRL_FRCRAMECCCHKEN_DEFAULT (_SYSCFG_RADIOECCCTRL_FRCRAMECCCHKEN_DEFAULT << 9) /**< Shifted mode DEFAULT for SYSCFG_RADIOECCCTRL*/ 424 425 /* Bit fields for SYSCFG RADIORAMCTRL */ 426 #define _SYSCFG_RADIORAMCTRL_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_RADIORAMCTRL */ 427 #define _SYSCFG_RADIORAMCTRL_MASK 0x01070007UL /**< Mask for SYSCFG_RADIORAMCTRL */ 428 #define SYSCFG_RADIORAMCTRL_SEQRAMCACHEEN (0x1UL << 0) /**< SEQRAM CACHE Enable */ 429 #define _SYSCFG_RADIORAMCTRL_SEQRAMCACHEEN_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMCACHEEN */ 430 #define _SYSCFG_RADIORAMCTRL_SEQRAMCACHEEN_MASK 0x1UL /**< Bit mask for SYSCFG_SEQRAMCACHEEN */ 431 #define _SYSCFG_RADIORAMCTRL_SEQRAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 432 #define SYSCFG_RADIORAMCTRL_SEQRAMCACHEEN_DEFAULT (_SYSCFG_RADIORAMCTRL_SEQRAMCACHEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 433 #define SYSCFG_RADIORAMCTRL_SEQRAMWSEN (0x1UL << 1) /**< SEQRAM WAIT STATE Enable */ 434 #define _SYSCFG_RADIORAMCTRL_SEQRAMWSEN_SHIFT 1 /**< Shift value for SYSCFG_SEQRAMWSEN */ 435 #define _SYSCFG_RADIORAMCTRL_SEQRAMWSEN_MASK 0x2UL /**< Bit mask for SYSCFG_SEQRAMWSEN */ 436 #define _SYSCFG_RADIORAMCTRL_SEQRAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 437 #define SYSCFG_RADIORAMCTRL_SEQRAMWSEN_DEFAULT (_SYSCFG_RADIORAMCTRL_SEQRAMWSEN_DEFAULT << 1) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 438 #define SYSCFG_RADIORAMCTRL_SEQRAMPREFETCHEN (0x1UL << 2) /**< SEQRAM Prfetch Enable */ 439 #define _SYSCFG_RADIORAMCTRL_SEQRAMPREFETCHEN_SHIFT 2 /**< Shift value for SYSCFG_SEQRAMPREFETCHEN */ 440 #define _SYSCFG_RADIORAMCTRL_SEQRAMPREFETCHEN_MASK 0x4UL /**< Bit mask for SYSCFG_SEQRAMPREFETCHEN */ 441 #define _SYSCFG_RADIORAMCTRL_SEQRAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 442 #define SYSCFG_RADIORAMCTRL_SEQRAMPREFETCHEN_DEFAULT (_SYSCFG_RADIORAMCTRL_SEQRAMPREFETCHEN_DEFAULT << 2) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 443 #define SYSCFG_RADIORAMCTRL_FRCRAMCACHEEN (0x1UL << 16) /**< FRCRAM CACHE Enable */ 444 #define _SYSCFG_RADIORAMCTRL_FRCRAMCACHEEN_SHIFT 16 /**< Shift value for SYSCFG_FRCRAMCACHEEN */ 445 #define _SYSCFG_RADIORAMCTRL_FRCRAMCACHEEN_MASK 0x10000UL /**< Bit mask for SYSCFG_FRCRAMCACHEEN */ 446 #define _SYSCFG_RADIORAMCTRL_FRCRAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 447 #define SYSCFG_RADIORAMCTRL_FRCRAMCACHEEN_DEFAULT (_SYSCFG_RADIORAMCTRL_FRCRAMCACHEEN_DEFAULT << 16) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 448 #define SYSCFG_RADIORAMCTRL_FRCRAMWSEN (0x1UL << 17) /**< FRCRAM WAIT STATE Enable */ 449 #define _SYSCFG_RADIORAMCTRL_FRCRAMWSEN_SHIFT 17 /**< Shift value for SYSCFG_FRCRAMWSEN */ 450 #define _SYSCFG_RADIORAMCTRL_FRCRAMWSEN_MASK 0x20000UL /**< Bit mask for SYSCFG_FRCRAMWSEN */ 451 #define _SYSCFG_RADIORAMCTRL_FRCRAMWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 452 #define SYSCFG_RADIORAMCTRL_FRCRAMWSEN_DEFAULT (_SYSCFG_RADIORAMCTRL_FRCRAMWSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 453 #define SYSCFG_RADIORAMCTRL_FRCRAMPREFETCHEN (0x1UL << 18) /**< FRCRAM Prfetch Enable */ 454 #define _SYSCFG_RADIORAMCTRL_FRCRAMPREFETCHEN_SHIFT 18 /**< Shift value for SYSCFG_FRCRAMPREFETCHEN */ 455 #define _SYSCFG_RADIORAMCTRL_FRCRAMPREFETCHEN_MASK 0x40000UL /**< Bit mask for SYSCFG_FRCRAMPREFETCHEN */ 456 #define _SYSCFG_RADIORAMCTRL_FRCRAMPREFETCHEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 457 #define SYSCFG_RADIORAMCTRL_FRCRAMPREFETCHEN_DEFAULT (_SYSCFG_RADIORAMCTRL_FRCRAMPREFETCHEN_DEFAULT << 18) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 458 #define SYSCFG_RADIORAMCTRL_DEMODRAMCACHEEN (0x1UL << 24) /**< DEMODRAM CACHE Enable */ 459 #define _SYSCFG_RADIORAMCTRL_DEMODRAMCACHEEN_SHIFT 24 /**< Shift value for SYSCFG_DEMODRAMCACHEEN */ 460 #define _SYSCFG_RADIORAMCTRL_DEMODRAMCACHEEN_MASK 0x1000000UL /**< Bit mask for SYSCFG_DEMODRAMCACHEEN */ 461 #define _SYSCFG_RADIORAMCTRL_DEMODRAMCACHEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_RADIORAMCTRL */ 462 #define SYSCFG_RADIORAMCTRL_DEMODRAMCACHEEN_DEFAULT (_SYSCFG_RADIORAMCTRL_DEMODRAMCACHEEN_DEFAULT << 24) /**< Shifted mode DEFAULT for SYSCFG_RADIORAMCTRL*/ 463 464 /* Bit fields for SYSCFG SEQRAMECCADDR */ 465 #define _SYSCFG_SEQRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_SEQRAMECCADDR */ 466 #define _SYSCFG_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_SEQRAMECCADDR */ 467 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_SEQRAMECCADDR */ 468 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_SEQRAMECCADDR */ 469 #define _SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_SEQRAMECCADDR */ 470 #define SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT (_SYSCFG_SEQRAMECCADDR_SEQRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_SEQRAMECCADDR*/ 471 472 /* Bit fields for SYSCFG FRCRAMECCADDR */ 473 #define _SYSCFG_FRCRAMECCADDR_RESETVALUE 0x00000000UL /**< Default value for SYSCFG_FRCRAMECCADDR */ 474 #define _SYSCFG_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Mask for SYSCFG_FRCRAMECCADDR */ 475 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_SHIFT 0 /**< Shift value for SYSCFG_FRCRAMECCADDR */ 476 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_MASK 0xFFFFFFFFUL /**< Bit mask for SYSCFG_FRCRAMECCADDR */ 477 #define _SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for SYSCFG_FRCRAMECCADDR */ 478 #define SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT (_SYSCFG_FRCRAMECCADDR_FRCRAMECCADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for SYSCFG_FRCRAMECCADDR*/ 479 480 /** @} End of group EFR32MG21_SYSCFG_BitFields */ 481 /** @} End of group EFR32MG21_SYSCFG */ 482 /** @} End of group Parts */ 483 484 #endif /* EFR32MG21_SYSCFG_H */ 485
