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Searched refs:SMU_PPUPATD1_TRNG0_DEFAULT (Results 1 – 25 of 69) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32FG13P/Include/
Defr32fg13p_smu.h272 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 6) /**< Shifted mode … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32BG13P/Include/
Defr32bg13p_smu.h272 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 6) /**< Shifted mode … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32PG12B/Include/
Defm32pg12b_smu.h277 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFR32MG12P/Include/
Defr32mg12p_smu.h277 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32JG12B/Include/
Defm32jg12b_smu.h277 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 7) /**< Shifted mode … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b_smu.h343 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b390f1024gl112.h7783 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b390f512gl112.h7783 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b110f1024iq64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b510f1024gl120.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b510f1024gm64.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b510f1024gl112.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b530f512im64.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b530f512iq64.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b130f512gm64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b130f512gq64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b130f512im64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b130f512iq64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b530f512iq100.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b110f1024gm64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b110f1024gq64.h8550 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b510f1024iq100.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b510f1024gq64.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
Defm32gg12b510f1024il112.h8586 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 14) /**< Shifted mode … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG11B/Include/
Defm32gg11b_smu.h368 #define SMU_PPUPATD1_TRNG0_DEFAULT (_SMU_PPUPATD1_TRNG0_DEFAULT << 16) /**< Shifted mode … macro

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