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Searched refs:QSPI0_BASE (Results 1 – 25 of 74) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32GG12B/Include/
Defm32gg12b830f512gm64.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512iq100.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512il112.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512il120.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512iq64.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024im64.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024iq64.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512gl112.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512gq100.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512gq64.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512il112.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512il120.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b830f512im64.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b410f1024gm64.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512gq100.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512gq64.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024gq100.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024gq64.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024il112.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024iq100.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b410f1024il112.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b410f1024iq64.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512gl112.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b430f512gm64.h481 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
550 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */
Defm32gg12b810f1024gl112.h483 #define QSPI0_BASE (0x4001C400UL) /**< QSPI0 base address */ macro
552 #define QSPI0 ((QSPI_TypeDef *) QSPI0_BASE) /**< QSPI0 base pointer */

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