1 /***************************************************************************//** 2 * @file 3 * @brief EFM32GG12B_PDM register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32GG12B_PDM PDM 43 * @{ 44 * @brief EFM32GG12B_PDM Register Declaration 45 ******************************************************************************/ 46 /** PDM Register Declaration */ 47 typedef struct { 48 __IM uint32_t IPVERSION; /**< IP Version ID */ 49 __IOM uint32_t EN; /**< PDM Module enable Register */ 50 __IOM uint32_t CTRL; /**< PDM Core Control Register */ 51 __IOM uint32_t CMD; /**< PDM Core Command Register */ 52 __IM uint32_t STATUS; /**< PDM Status register */ 53 __IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */ 54 __IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */ 55 uint32_t RESERVED0[1U]; /**< Reserved for future use **/ 56 __IM uint32_t RXDATA; /**< PDM Received Data Register */ 57 uint32_t RESERVED1[7U]; /**< Reserved for future use **/ 58 __IM uint32_t IF; /**< Interrupt Flag Register */ 59 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 60 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 61 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 62 __IOM uint32_t ROUTEPEN; /**< I/O LOCATION Enable Register */ 63 __IOM uint32_t ROUTELOC0; /**< I/O LOCATION Register */ 64 __IOM uint32_t ROUTELOC1; /**< I/O LOCATION Register */ 65 uint32_t RESERVED2[1U]; /**< Reserved for future use **/ 66 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 67 } PDM_TypeDef; /** @} */ 68 69 /***************************************************************************//** 70 * @addtogroup EFM32GG12B_PDM 71 * @{ 72 * @defgroup EFM32GG12B_PDM_BitFields PDM Bit Fields 73 * @{ 74 ******************************************************************************/ 75 76 /* Bit fields for PDM IPVERSION */ 77 #define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */ 78 #define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */ 79 #define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */ 80 #define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */ 81 #define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */ 82 #define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */ 83 84 /* Bit fields for PDM EN */ 85 #define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */ 86 #define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */ 87 #define PDM_EN_EN (0x1UL << 0) /**< Module enable */ 88 #define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */ 89 #define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */ 90 #define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */ 91 #define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */ 92 #define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */ 93 #define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */ 94 #define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */ 95 #define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */ 96 97 /* Bit fields for PDM CTRL */ 98 #define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */ 99 #define _PDM_CTRL_MASK 0x800FFF1FUL /**< Mask for PDM_CTRL */ 100 #define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */ 101 #define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */ 102 #define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ 103 #define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */ 104 #define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */ 105 #define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */ 106 #define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ 107 #define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */ 108 #define PDM_CTRL_OUTCLKEN (0x1UL << 31) /**< PDM Clock enable */ 109 #define _PDM_CTRL_OUTCLKEN_SHIFT 31 /**< Shift value for PDM_OUTCLKEN */ 110 #define _PDM_CTRL_OUTCLKEN_MASK 0x80000000UL /**< Bit mask for PDM_OUTCLKEN */ 111 #define _PDM_CTRL_OUTCLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */ 112 #define PDM_CTRL_OUTCLKEN_DEFAULT (_PDM_CTRL_OUTCLKEN_DEFAULT << 31) /**< Shifted mode DEFAULT for PDM_CTRL */ 113 114 /* Bit fields for PDM CMD */ 115 #define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */ 116 #define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */ 117 #define PDM_CMD_START (0x1UL << 0) /**< Start DCF */ 118 #define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */ 119 #define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */ 120 #define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 121 #define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */ 122 #define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */ 123 #define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */ 124 #define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */ 125 #define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 126 #define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */ 127 #define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */ 128 #define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */ 129 #define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */ 130 #define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 131 #define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */ 132 #define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */ 133 #define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */ 134 #define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */ 135 #define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */ 136 #define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */ 137 138 /* Bit fields for PDM STATUS */ 139 #define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */ 140 #define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */ 141 #define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */ 142 #define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */ 143 #define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */ 144 #define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ 145 #define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */ 146 #define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */ 147 #define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */ 148 #define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */ 149 #define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ 150 #define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */ 151 #define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */ 152 #define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */ 153 #define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */ 154 #define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */ 155 #define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */ 156 #define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */ 157 #define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */ 158 #define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */ 159 #define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */ 160 161 /* Bit fields for PDM CFG0 */ 162 #define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */ 163 #define _PDM_CFG0_MASK 0x0F033733UL /**< Mask for PDM_CFG0 */ 164 #define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */ 165 #define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */ 166 #define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 167 #define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */ 168 #define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */ 169 #define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */ 170 #define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */ 171 #define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */ 172 #define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */ 173 #define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */ 174 #define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */ 175 #define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */ 176 #define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */ 177 #define _PDM_CFG0_NUMCH_MASK 0x30UL /**< Bit mask for PDM_NUMCH */ 178 #define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 179 #define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ 180 #define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ 181 #define _PDM_CFG0_NUMCH_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ 182 #define _PDM_CFG0_NUMCH_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ 183 #define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */ 184 #define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */ 185 #define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */ 186 #define PDM_CFG0_NUMCH_THREE (_PDM_CFG0_NUMCH_THREE << 4) /**< Shifted mode THREE for PDM_CFG0 */ 187 #define PDM_CFG0_NUMCH_FOUR (_PDM_CFG0_NUMCH_FOUR << 4) /**< Shifted mode FOUR for PDM_CFG0 */ 188 #define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */ 189 #define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */ 190 #define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 191 #define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */ 192 #define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */ 193 #define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */ 194 #define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */ 195 #define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */ 196 #define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */ 197 #define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */ 198 #define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */ 199 #define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */ 200 #define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */ 201 #define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */ 202 #define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */ 203 #define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */ 204 #define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */ 205 #define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */ 206 #define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */ 207 #define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */ 208 #define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 209 #define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */ 210 #define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */ 211 #define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */ 212 #define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */ 213 #define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */ 214 #define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */ 215 #define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */ 216 #define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */ 217 #define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */ 218 #define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */ 219 #define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */ 220 #define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */ 221 #define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 222 #define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ 223 #define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */ 224 #define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */ 225 #define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */ 226 #define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */ 227 #define PDM_CFG0_STEREOMODECH23 (0x1UL << 17) /**< Stereo mode CH23 */ 228 #define _PDM_CFG0_STEREOMODECH23_SHIFT 17 /**< Shift value for PDM_STEREOMODECH23 */ 229 #define _PDM_CFG0_STEREOMODECH23_MASK 0x20000UL /**< Bit mask for PDM_STEREOMODECH23 */ 230 #define _PDM_CFG0_STEREOMODECH23_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 231 #define _PDM_CFG0_STEREOMODECH23_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */ 232 #define _PDM_CFG0_STEREOMODECH23_CH23ENABLE 0x00000001UL /**< Mode CH23ENABLE for PDM_CFG0 */ 233 #define PDM_CFG0_STEREOMODECH23_DEFAULT (_PDM_CFG0_STEREOMODECH23_DEFAULT << 17) /**< Shifted mode DEFAULT for PDM_CFG0 */ 234 #define PDM_CFG0_STEREOMODECH23_DISABLE (_PDM_CFG0_STEREOMODECH23_DISABLE << 17) /**< Shifted mode DISABLE for PDM_CFG0 */ 235 #define PDM_CFG0_STEREOMODECH23_CH23ENABLE (_PDM_CFG0_STEREOMODECH23_CH23ENABLE << 17) /**< Shifted mode CH23ENABLE for PDM_CFG0 */ 236 #define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */ 237 #define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */ 238 #define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */ 239 #define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 240 #define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ 241 #define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ 242 #define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */ 243 #define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */ 244 #define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */ 245 #define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */ 246 #define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */ 247 #define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */ 248 #define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 249 #define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ 250 #define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ 251 #define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */ 252 #define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */ 253 #define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */ 254 #define PDM_CFG0_CH2CLKPOL (0x1UL << 26) /**< CH2 CLK Polarity */ 255 #define _PDM_CFG0_CH2CLKPOL_SHIFT 26 /**< Shift value for PDM_CH2CLKPOL */ 256 #define _PDM_CFG0_CH2CLKPOL_MASK 0x4000000UL /**< Bit mask for PDM_CH2CLKPOL */ 257 #define _PDM_CFG0_CH2CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 258 #define _PDM_CFG0_CH2CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ 259 #define _PDM_CFG0_CH2CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ 260 #define PDM_CFG0_CH2CLKPOL_DEFAULT (_PDM_CFG0_CH2CLKPOL_DEFAULT << 26) /**< Shifted mode DEFAULT for PDM_CFG0 */ 261 #define PDM_CFG0_CH2CLKPOL_NORMAL (_PDM_CFG0_CH2CLKPOL_NORMAL << 26) /**< Shifted mode NORMAL for PDM_CFG0 */ 262 #define PDM_CFG0_CH2CLKPOL_INVERT (_PDM_CFG0_CH2CLKPOL_INVERT << 26) /**< Shifted mode INVERT for PDM_CFG0 */ 263 #define PDM_CFG0_CH3CLKPOL (0x1UL << 27) /**< CH3 CLK Polarity */ 264 #define _PDM_CFG0_CH3CLKPOL_SHIFT 27 /**< Shift value for PDM_CH3CLKPOL */ 265 #define _PDM_CFG0_CH3CLKPOL_MASK 0x8000000UL /**< Bit mask for PDM_CH3CLKPOL */ 266 #define _PDM_CFG0_CH3CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */ 267 #define _PDM_CFG0_CH3CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */ 268 #define _PDM_CFG0_CH3CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */ 269 #define PDM_CFG0_CH3CLKPOL_DEFAULT (_PDM_CFG0_CH3CLKPOL_DEFAULT << 27) /**< Shifted mode DEFAULT for PDM_CFG0 */ 270 #define PDM_CFG0_CH3CLKPOL_NORMAL (_PDM_CFG0_CH3CLKPOL_NORMAL << 27) /**< Shifted mode NORMAL for PDM_CFG0 */ 271 #define PDM_CFG0_CH3CLKPOL_INVERT (_PDM_CFG0_CH3CLKPOL_INVERT << 27) /**< Shifted mode INVERT for PDM_CFG0 */ 272 273 /* Bit fields for PDM CFG1 */ 274 #define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */ 275 #define _PDM_CFG1_MASK 0x000003FFUL /**< Mask for PDM_CFG1 */ 276 #define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */ 277 #define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */ 278 #define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */ 279 #define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */ 280 281 /* Bit fields for PDM RXDATA */ 282 #define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */ 283 #define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */ 284 #define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */ 285 #define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */ 286 #define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */ 287 #define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */ 288 289 /* Bit fields for PDM IF */ 290 #define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */ 291 #define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */ 292 #define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */ 293 #define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */ 294 #define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ 295 #define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 296 #define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */ 297 #define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */ 298 #define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ 299 #define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ 300 #define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 301 #define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */ 302 #define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */ 303 #define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */ 304 #define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ 305 #define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 306 #define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */ 307 #define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */ 308 #define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */ 309 #define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ 310 #define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */ 311 #define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */ 312 313 /* Bit fields for PDM IFS */ 314 #define _PDM_IFS_RESETVALUE 0x00000000UL /**< Default value for PDM_IFS */ 315 #define _PDM_IFS_MASK 0x0000000FUL /**< Mask for PDM_IFS */ 316 #define PDM_IFS_DV (0x1UL << 0) /**< Set DV Interrupt Flag */ 317 #define _PDM_IFS_DV_SHIFT 0 /**< Shift value for PDM_DV */ 318 #define _PDM_IFS_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ 319 #define _PDM_IFS_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFS */ 320 #define PDM_IFS_DV_DEFAULT (_PDM_IFS_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IFS */ 321 #define PDM_IFS_DVL (0x1UL << 1) /**< Set DVL Interrupt Flag */ 322 #define _PDM_IFS_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ 323 #define _PDM_IFS_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ 324 #define _PDM_IFS_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFS */ 325 #define PDM_IFS_DVL_DEFAULT (_PDM_IFS_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IFS */ 326 #define PDM_IFS_OF (0x1UL << 2) /**< Set OF Interrupt Flag */ 327 #define _PDM_IFS_OF_SHIFT 2 /**< Shift value for PDM_OF */ 328 #define _PDM_IFS_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ 329 #define _PDM_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFS */ 330 #define PDM_IFS_OF_DEFAULT (_PDM_IFS_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IFS */ 331 #define PDM_IFS_UF (0x1UL << 3) /**< Set UF Interrupt Flag */ 332 #define _PDM_IFS_UF_SHIFT 3 /**< Shift value for PDM_UF */ 333 #define _PDM_IFS_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ 334 #define _PDM_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFS */ 335 #define PDM_IFS_UF_DEFAULT (_PDM_IFS_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IFS */ 336 337 /* Bit fields for PDM IFC */ 338 #define _PDM_IFC_RESETVALUE 0x00000000UL /**< Default value for PDM_IFC */ 339 #define _PDM_IFC_MASK 0x0000000FUL /**< Mask for PDM_IFC */ 340 #define PDM_IFC_DV (0x1UL << 0) /**< Clear DV Interrupt Flag */ 341 #define _PDM_IFC_DV_SHIFT 0 /**< Shift value for PDM_DV */ 342 #define _PDM_IFC_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ 343 #define _PDM_IFC_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFC */ 344 #define PDM_IFC_DV_DEFAULT (_PDM_IFC_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IFC */ 345 #define PDM_IFC_DVL (0x1UL << 1) /**< Clear DVL Interrupt Flag */ 346 #define _PDM_IFC_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ 347 #define _PDM_IFC_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ 348 #define _PDM_IFC_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFC */ 349 #define PDM_IFC_DVL_DEFAULT (_PDM_IFC_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IFC */ 350 #define PDM_IFC_OF (0x1UL << 2) /**< Clear OF Interrupt Flag */ 351 #define _PDM_IFC_OF_SHIFT 2 /**< Shift value for PDM_OF */ 352 #define _PDM_IFC_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ 353 #define _PDM_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFC */ 354 #define PDM_IFC_OF_DEFAULT (_PDM_IFC_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IFC */ 355 #define PDM_IFC_UF (0x1UL << 3) /**< Clear UF Interrupt Flag */ 356 #define _PDM_IFC_UF_SHIFT 3 /**< Shift value for PDM_UF */ 357 #define _PDM_IFC_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ 358 #define _PDM_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IFC */ 359 #define PDM_IFC_UF_DEFAULT (_PDM_IFC_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IFC */ 360 361 /* Bit fields for PDM IEN */ 362 #define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */ 363 #define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */ 364 #define PDM_IEN_DV (0x1UL << 0) /**< DV Interrupt Enable */ 365 #define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */ 366 #define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */ 367 #define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 368 #define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */ 369 #define PDM_IEN_DVL (0x1UL << 1) /**< DVL Interrupt Enable */ 370 #define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */ 371 #define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */ 372 #define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 373 #define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */ 374 #define PDM_IEN_OF (0x1UL << 2) /**< OF Interrupt Enable */ 375 #define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */ 376 #define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */ 377 #define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 378 #define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */ 379 #define PDM_IEN_UF (0x1UL << 3) /**< UF Interrupt Enable */ 380 #define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */ 381 #define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */ 382 #define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */ 383 #define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */ 384 385 /* Bit fields for PDM ROUTEPEN */ 386 #define _PDM_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for PDM_ROUTEPEN */ 387 #define _PDM_ROUTEPEN_MASK 0x0000010FUL /**< Mask for PDM_ROUTEPEN */ 388 #define PDM_ROUTEPEN_DAT0PEN (0x1UL << 0) /**< DAT0 I/O Enable */ 389 #define _PDM_ROUTEPEN_DAT0PEN_SHIFT 0 /**< Shift value for PDM_DAT0PEN */ 390 #define _PDM_ROUTEPEN_DAT0PEN_MASK 0x1UL /**< Bit mask for PDM_DAT0PEN */ 391 #define _PDM_ROUTEPEN_DAT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTEPEN */ 392 #define PDM_ROUTEPEN_DAT0PEN_DEFAULT (_PDM_ROUTEPEN_DAT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_ROUTEPEN */ 393 #define PDM_ROUTEPEN_DAT1PEN (0x1UL << 1) /**< DAT1 I/O Enable */ 394 #define _PDM_ROUTEPEN_DAT1PEN_SHIFT 1 /**< Shift value for PDM_DAT1PEN */ 395 #define _PDM_ROUTEPEN_DAT1PEN_MASK 0x2UL /**< Bit mask for PDM_DAT1PEN */ 396 #define _PDM_ROUTEPEN_DAT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTEPEN */ 397 #define PDM_ROUTEPEN_DAT1PEN_DEFAULT (_PDM_ROUTEPEN_DAT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_ROUTEPEN */ 398 #define PDM_ROUTEPEN_DAT2PEN (0x1UL << 2) /**< DAT2 I/O Enable */ 399 #define _PDM_ROUTEPEN_DAT2PEN_SHIFT 2 /**< Shift value for PDM_DAT2PEN */ 400 #define _PDM_ROUTEPEN_DAT2PEN_MASK 0x4UL /**< Bit mask for PDM_DAT2PEN */ 401 #define _PDM_ROUTEPEN_DAT2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTEPEN */ 402 #define PDM_ROUTEPEN_DAT2PEN_DEFAULT (_PDM_ROUTEPEN_DAT2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_ROUTEPEN */ 403 #define PDM_ROUTEPEN_DAT3PEN (0x1UL << 3) /**< DAT3 I/O Enable */ 404 #define _PDM_ROUTEPEN_DAT3PEN_SHIFT 3 /**< Shift value for PDM_DAT3PEN */ 405 #define _PDM_ROUTEPEN_DAT3PEN_MASK 0x8UL /**< Bit mask for PDM_DAT3PEN */ 406 #define _PDM_ROUTEPEN_DAT3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTEPEN */ 407 #define PDM_ROUTEPEN_DAT3PEN_DEFAULT (_PDM_ROUTEPEN_DAT3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_ROUTEPEN */ 408 #define PDM_ROUTEPEN_CLKPEN (0x1UL << 8) /**< CLK I/O Enable */ 409 #define _PDM_ROUTEPEN_CLKPEN_SHIFT 8 /**< Shift value for PDM_CLKPEN */ 410 #define _PDM_ROUTEPEN_CLKPEN_MASK 0x100UL /**< Bit mask for PDM_CLKPEN */ 411 #define _PDM_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTEPEN */ 412 #define PDM_ROUTEPEN_CLKPEN_DEFAULT (_PDM_ROUTEPEN_CLKPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_ROUTEPEN */ 413 414 /* Bit fields for PDM ROUTELOC0 */ 415 #define _PDM_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for PDM_ROUTELOC0 */ 416 #define _PDM_ROUTELOC0_MASK 0x07070707UL /**< Mask for PDM_ROUTELOC0 */ 417 #define _PDM_ROUTELOC0_DAT0LOC_SHIFT 0 /**< Shift value for PDM_DAT0LOC */ 418 #define _PDM_ROUTELOC0_DAT0LOC_MASK 0x7UL /**< Bit mask for PDM_DAT0LOC */ 419 #define _PDM_ROUTELOC0_DAT0LOC_LOC0 0x00000000UL /**< Mode LOC0 for PDM_ROUTELOC0 */ 420 #define _PDM_ROUTELOC0_DAT0LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTELOC0 */ 421 #define _PDM_ROUTELOC0_DAT0LOC_LOC1 0x00000001UL /**< Mode LOC1 for PDM_ROUTELOC0 */ 422 #define _PDM_ROUTELOC0_DAT0LOC_LOC2 0x00000002UL /**< Mode LOC2 for PDM_ROUTELOC0 */ 423 #define _PDM_ROUTELOC0_DAT0LOC_LOC3 0x00000003UL /**< Mode LOC3 for PDM_ROUTELOC0 */ 424 #define _PDM_ROUTELOC0_DAT0LOC_LOC4 0x00000004UL /**< Mode LOC4 for PDM_ROUTELOC0 */ 425 #define PDM_ROUTELOC0_DAT0LOC_LOC0 (_PDM_ROUTELOC0_DAT0LOC_LOC0 << 0) /**< Shifted mode LOC0 for PDM_ROUTELOC0 */ 426 #define PDM_ROUTELOC0_DAT0LOC_DEFAULT (_PDM_ROUTELOC0_DAT0LOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_ROUTELOC0 */ 427 #define PDM_ROUTELOC0_DAT0LOC_LOC1 (_PDM_ROUTELOC0_DAT0LOC_LOC1 << 0) /**< Shifted mode LOC1 for PDM_ROUTELOC0 */ 428 #define PDM_ROUTELOC0_DAT0LOC_LOC2 (_PDM_ROUTELOC0_DAT0LOC_LOC2 << 0) /**< Shifted mode LOC2 for PDM_ROUTELOC0 */ 429 #define PDM_ROUTELOC0_DAT0LOC_LOC3 (_PDM_ROUTELOC0_DAT0LOC_LOC3 << 0) /**< Shifted mode LOC3 for PDM_ROUTELOC0 */ 430 #define PDM_ROUTELOC0_DAT0LOC_LOC4 (_PDM_ROUTELOC0_DAT0LOC_LOC4 << 0) /**< Shifted mode LOC4 for PDM_ROUTELOC0 */ 431 #define _PDM_ROUTELOC0_DAT1LOC_SHIFT 8 /**< Shift value for PDM_DAT1LOC */ 432 #define _PDM_ROUTELOC0_DAT1LOC_MASK 0x700UL /**< Bit mask for PDM_DAT1LOC */ 433 #define _PDM_ROUTELOC0_DAT1LOC_LOC0 0x00000000UL /**< Mode LOC0 for PDM_ROUTELOC0 */ 434 #define _PDM_ROUTELOC0_DAT1LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTELOC0 */ 435 #define _PDM_ROUTELOC0_DAT1LOC_LOC1 0x00000001UL /**< Mode LOC1 for PDM_ROUTELOC0 */ 436 #define _PDM_ROUTELOC0_DAT1LOC_LOC2 0x00000002UL /**< Mode LOC2 for PDM_ROUTELOC0 */ 437 #define _PDM_ROUTELOC0_DAT1LOC_LOC3 0x00000003UL /**< Mode LOC3 for PDM_ROUTELOC0 */ 438 #define _PDM_ROUTELOC0_DAT1LOC_LOC4 0x00000004UL /**< Mode LOC4 for PDM_ROUTELOC0 */ 439 #define PDM_ROUTELOC0_DAT1LOC_LOC0 (_PDM_ROUTELOC0_DAT1LOC_LOC0 << 8) /**< Shifted mode LOC0 for PDM_ROUTELOC0 */ 440 #define PDM_ROUTELOC0_DAT1LOC_DEFAULT (_PDM_ROUTELOC0_DAT1LOC_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_ROUTELOC0 */ 441 #define PDM_ROUTELOC0_DAT1LOC_LOC1 (_PDM_ROUTELOC0_DAT1LOC_LOC1 << 8) /**< Shifted mode LOC1 for PDM_ROUTELOC0 */ 442 #define PDM_ROUTELOC0_DAT1LOC_LOC2 (_PDM_ROUTELOC0_DAT1LOC_LOC2 << 8) /**< Shifted mode LOC2 for PDM_ROUTELOC0 */ 443 #define PDM_ROUTELOC0_DAT1LOC_LOC3 (_PDM_ROUTELOC0_DAT1LOC_LOC3 << 8) /**< Shifted mode LOC3 for PDM_ROUTELOC0 */ 444 #define PDM_ROUTELOC0_DAT1LOC_LOC4 (_PDM_ROUTELOC0_DAT1LOC_LOC4 << 8) /**< Shifted mode LOC4 for PDM_ROUTELOC0 */ 445 #define _PDM_ROUTELOC0_DAT2LOC_SHIFT 16 /**< Shift value for PDM_DAT2LOC */ 446 #define _PDM_ROUTELOC0_DAT2LOC_MASK 0x70000UL /**< Bit mask for PDM_DAT2LOC */ 447 #define _PDM_ROUTELOC0_DAT2LOC_LOC0 0x00000000UL /**< Mode LOC0 for PDM_ROUTELOC0 */ 448 #define _PDM_ROUTELOC0_DAT2LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTELOC0 */ 449 #define _PDM_ROUTELOC0_DAT2LOC_LOC1 0x00000001UL /**< Mode LOC1 for PDM_ROUTELOC0 */ 450 #define _PDM_ROUTELOC0_DAT2LOC_LOC2 0x00000002UL /**< Mode LOC2 for PDM_ROUTELOC0 */ 451 #define _PDM_ROUTELOC0_DAT2LOC_LOC3 0x00000003UL /**< Mode LOC3 for PDM_ROUTELOC0 */ 452 #define _PDM_ROUTELOC0_DAT2LOC_LOC4 0x00000004UL /**< Mode LOC4 for PDM_ROUTELOC0 */ 453 #define PDM_ROUTELOC0_DAT2LOC_LOC0 (_PDM_ROUTELOC0_DAT2LOC_LOC0 << 16) /**< Shifted mode LOC0 for PDM_ROUTELOC0 */ 454 #define PDM_ROUTELOC0_DAT2LOC_DEFAULT (_PDM_ROUTELOC0_DAT2LOC_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_ROUTELOC0 */ 455 #define PDM_ROUTELOC0_DAT2LOC_LOC1 (_PDM_ROUTELOC0_DAT2LOC_LOC1 << 16) /**< Shifted mode LOC1 for PDM_ROUTELOC0 */ 456 #define PDM_ROUTELOC0_DAT2LOC_LOC2 (_PDM_ROUTELOC0_DAT2LOC_LOC2 << 16) /**< Shifted mode LOC2 for PDM_ROUTELOC0 */ 457 #define PDM_ROUTELOC0_DAT2LOC_LOC3 (_PDM_ROUTELOC0_DAT2LOC_LOC3 << 16) /**< Shifted mode LOC3 for PDM_ROUTELOC0 */ 458 #define PDM_ROUTELOC0_DAT2LOC_LOC4 (_PDM_ROUTELOC0_DAT2LOC_LOC4 << 16) /**< Shifted mode LOC4 for PDM_ROUTELOC0 */ 459 #define _PDM_ROUTELOC0_DAT3LOC_SHIFT 24 /**< Shift value for PDM_DAT3LOC */ 460 #define _PDM_ROUTELOC0_DAT3LOC_MASK 0x7000000UL /**< Bit mask for PDM_DAT3LOC */ 461 #define _PDM_ROUTELOC0_DAT3LOC_LOC0 0x00000000UL /**< Mode LOC0 for PDM_ROUTELOC0 */ 462 #define _PDM_ROUTELOC0_DAT3LOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTELOC0 */ 463 #define _PDM_ROUTELOC0_DAT3LOC_LOC1 0x00000001UL /**< Mode LOC1 for PDM_ROUTELOC0 */ 464 #define _PDM_ROUTELOC0_DAT3LOC_LOC2 0x00000002UL /**< Mode LOC2 for PDM_ROUTELOC0 */ 465 #define _PDM_ROUTELOC0_DAT3LOC_LOC3 0x00000003UL /**< Mode LOC3 for PDM_ROUTELOC0 */ 466 #define _PDM_ROUTELOC0_DAT3LOC_LOC4 0x00000004UL /**< Mode LOC4 for PDM_ROUTELOC0 */ 467 #define PDM_ROUTELOC0_DAT3LOC_LOC0 (_PDM_ROUTELOC0_DAT3LOC_LOC0 << 24) /**< Shifted mode LOC0 for PDM_ROUTELOC0 */ 468 #define PDM_ROUTELOC0_DAT3LOC_DEFAULT (_PDM_ROUTELOC0_DAT3LOC_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_ROUTELOC0 */ 469 #define PDM_ROUTELOC0_DAT3LOC_LOC1 (_PDM_ROUTELOC0_DAT3LOC_LOC1 << 24) /**< Shifted mode LOC1 for PDM_ROUTELOC0 */ 470 #define PDM_ROUTELOC0_DAT3LOC_LOC2 (_PDM_ROUTELOC0_DAT3LOC_LOC2 << 24) /**< Shifted mode LOC2 for PDM_ROUTELOC0 */ 471 #define PDM_ROUTELOC0_DAT3LOC_LOC3 (_PDM_ROUTELOC0_DAT3LOC_LOC3 << 24) /**< Shifted mode LOC3 for PDM_ROUTELOC0 */ 472 #define PDM_ROUTELOC0_DAT3LOC_LOC4 (_PDM_ROUTELOC0_DAT3LOC_LOC4 << 24) /**< Shifted mode LOC4 for PDM_ROUTELOC0 */ 473 474 /* Bit fields for PDM ROUTELOC1 */ 475 #define _PDM_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for PDM_ROUTELOC1 */ 476 #define _PDM_ROUTELOC1_MASK 0x00000007UL /**< Mask for PDM_ROUTELOC1 */ 477 #define _PDM_ROUTELOC1_CLKLOC_SHIFT 0 /**< Shift value for PDM_CLKLOC */ 478 #define _PDM_ROUTELOC1_CLKLOC_MASK 0x7UL /**< Bit mask for PDM_CLKLOC */ 479 #define _PDM_ROUTELOC1_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for PDM_ROUTELOC1 */ 480 #define _PDM_ROUTELOC1_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_ROUTELOC1 */ 481 #define _PDM_ROUTELOC1_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for PDM_ROUTELOC1 */ 482 #define _PDM_ROUTELOC1_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for PDM_ROUTELOC1 */ 483 #define _PDM_ROUTELOC1_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for PDM_ROUTELOC1 */ 484 #define _PDM_ROUTELOC1_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for PDM_ROUTELOC1 */ 485 #define PDM_ROUTELOC1_CLKLOC_LOC0 (_PDM_ROUTELOC1_CLKLOC_LOC0 << 0) /**< Shifted mode LOC0 for PDM_ROUTELOC1 */ 486 #define PDM_ROUTELOC1_CLKLOC_DEFAULT (_PDM_ROUTELOC1_CLKLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_ROUTELOC1 */ 487 #define PDM_ROUTELOC1_CLKLOC_LOC1 (_PDM_ROUTELOC1_CLKLOC_LOC1 << 0) /**< Shifted mode LOC1 for PDM_ROUTELOC1 */ 488 #define PDM_ROUTELOC1_CLKLOC_LOC2 (_PDM_ROUTELOC1_CLKLOC_LOC2 << 0) /**< Shifted mode LOC2 for PDM_ROUTELOC1 */ 489 #define PDM_ROUTELOC1_CLKLOC_LOC3 (_PDM_ROUTELOC1_CLKLOC_LOC3 << 0) /**< Shifted mode LOC3 for PDM_ROUTELOC1 */ 490 #define PDM_ROUTELOC1_CLKLOC_LOC4 (_PDM_ROUTELOC1_CLKLOC_LOC4 << 0) /**< Shifted mode LOC4 for PDM_ROUTELOC1 */ 491 492 /* Bit fields for PDM SYNCBUSY */ 493 #define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */ 494 #define _PDM_SYNCBUSY_MASK 0x0000050FUL /**< Mask for PDM_SYNCBUSY */ 495 #define PDM_SYNCBUSY_STARTBUSY (0x1UL << 0) /**< START sync busy */ 496 #define _PDM_SYNCBUSY_STARTBUSY_SHIFT 0 /**< Shift value for PDM_STARTBUSY */ 497 #define _PDM_SYNCBUSY_STARTBUSY_MASK 0x1UL /**< Bit mask for PDM_STARTBUSY */ 498 #define _PDM_SYNCBUSY_STARTBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 499 #define PDM_SYNCBUSY_STARTBUSY_DEFAULT (_PDM_SYNCBUSY_STARTBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 500 #define PDM_SYNCBUSY_STOPBUSY (0x1UL << 1) /**< STOP sync busy */ 501 #define _PDM_SYNCBUSY_STOPBUSY_SHIFT 1 /**< Shift value for PDM_STOPBUSY */ 502 #define _PDM_SYNCBUSY_STOPBUSY_MASK 0x2UL /**< Bit mask for PDM_STOPBUSY */ 503 #define _PDM_SYNCBUSY_STOPBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 504 #define PDM_SYNCBUSY_STOPBUSY_DEFAULT (_PDM_SYNCBUSY_STOPBUSY_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 505 #define PDM_SYNCBUSY_CLEARBUSY (0x1UL << 2) /**< CLEAR sync busy */ 506 #define _PDM_SYNCBUSY_CLEARBUSY_SHIFT 2 /**< Shift value for PDM_CLEARBUSY */ 507 #define _PDM_SYNCBUSY_CLEARBUSY_MASK 0x4UL /**< Bit mask for PDM_CLEARBUSY */ 508 #define _PDM_SYNCBUSY_CLEARBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 509 #define PDM_SYNCBUSY_CLEARBUSY_DEFAULT (_PDM_SYNCBUSY_CLEARBUSY_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 510 #define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */ 511 #define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */ 512 #define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */ 513 #define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 514 #define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 515 #define PDM_SYNCBUSY_PRESCBUSY (0x1UL << 8) /**< PRESC Sync busy */ 516 #define _PDM_SYNCBUSY_PRESCBUSY_SHIFT 8 /**< Shift value for PDM_PRESCBUSY */ 517 #define _PDM_SYNCBUSY_PRESCBUSY_MASK 0x100UL /**< Bit mask for PDM_PRESCBUSY */ 518 #define _PDM_SYNCBUSY_PRESCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 519 #define PDM_SYNCBUSY_PRESCBUSY_DEFAULT (_PDM_SYNCBUSY_PRESCBUSY_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 520 #define PDM_SYNCBUSY_CTRLREGBUSY (0x1UL << 10) /**< CTRLREGBUSY busy */ 521 #define _PDM_SYNCBUSY_CTRLREGBUSY_SHIFT 10 /**< Shift value for PDM_CTRLREGBUSY */ 522 #define _PDM_SYNCBUSY_CTRLREGBUSY_MASK 0x400UL /**< Bit mask for PDM_CTRLREGBUSY */ 523 #define _PDM_SYNCBUSY_CTRLREGBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */ 524 #define PDM_SYNCBUSY_CTRLREGBUSY_DEFAULT (_PDM_SYNCBUSY_CTRLREGBUSY_DEFAULT << 10) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */ 525 526 /** @} */ 527 /** @} End of group EFM32GG12B_PDM */ 528 /** @} End of group Parts */ 529
