1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 MPAHBRAM register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_MPAHBRAM_H 31 #define EFR32MG24_MPAHBRAM_H 32 #define MPAHBRAM_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_MPAHBRAM MPAHBRAM 40 * @{ 41 * @brief EFR32MG24 MPAHBRAM Register Declaration. 42 *****************************************************************************/ 43 44 /** MPAHBRAM Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t CMD; /**< Command register */ 48 __IOM uint32_t CTRL; /**< Control register */ 49 __IM uint32_t ECCERRADDR0; /**< ECC Error Address 0 */ 50 __IM uint32_t ECCERRADDR1; /**< ECC Error Address 1 */ 51 __IM uint32_t ECCERRADDR2; /**< ECC Error Address 2 */ 52 __IM uint32_t ECCERRADDR3; /**< ECC Error Address 3 */ 53 __IM uint32_t ECCMERRIND; /**< Multiple ECC error indication */ 54 __IOM uint32_t IF; /**< Interrupt Flags */ 55 __IOM uint32_t IEN; /**< Interrupt Enable */ 56 __IOM uint32_t RAMBANKSVALID; /**< New Register */ 57 __IOM uint32_t CFGSRTOP; /**< Sequential Region on Top */ 58 __IOM uint32_t CFGSRMAP; /**< Sequential Region Map */ 59 __IOM uint32_t CFGIU0MAP; /**< Interleaving Unit 0 Map */ 60 __IOM uint32_t CFGIU1MAP; /**< Interleaving Unit 1 Map */ 61 __IOM uint32_t CFGIU2MAP; /**< Interleaving Unit 2 Map */ 62 __IOM uint32_t CFGIU3MAP; /**< Interleaving Unit 3 Map */ 63 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 64 uint32_t RESERVED1[1006U]; /**< Reserved for future use */ 65 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 66 __IOM uint32_t CMD_SET; /**< Command register */ 67 __IOM uint32_t CTRL_SET; /**< Control register */ 68 __IM uint32_t ECCERRADDR0_SET; /**< ECC Error Address 0 */ 69 __IM uint32_t ECCERRADDR1_SET; /**< ECC Error Address 1 */ 70 __IM uint32_t ECCERRADDR2_SET; /**< ECC Error Address 2 */ 71 __IM uint32_t ECCERRADDR3_SET; /**< ECC Error Address 3 */ 72 __IM uint32_t ECCMERRIND_SET; /**< Multiple ECC error indication */ 73 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 74 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 75 __IOM uint32_t RAMBANKSVALID_SET; /**< New Register */ 76 __IOM uint32_t CFGSRTOP_SET; /**< Sequential Region on Top */ 77 __IOM uint32_t CFGSRMAP_SET; /**< Sequential Region Map */ 78 __IOM uint32_t CFGIU0MAP_SET; /**< Interleaving Unit 0 Map */ 79 __IOM uint32_t CFGIU1MAP_SET; /**< Interleaving Unit 1 Map */ 80 __IOM uint32_t CFGIU2MAP_SET; /**< Interleaving Unit 2 Map */ 81 __IOM uint32_t CFGIU3MAP_SET; /**< Interleaving Unit 3 Map */ 82 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 83 uint32_t RESERVED3[1006U]; /**< Reserved for future use */ 84 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 85 __IOM uint32_t CMD_CLR; /**< Command register */ 86 __IOM uint32_t CTRL_CLR; /**< Control register */ 87 __IM uint32_t ECCERRADDR0_CLR; /**< ECC Error Address 0 */ 88 __IM uint32_t ECCERRADDR1_CLR; /**< ECC Error Address 1 */ 89 __IM uint32_t ECCERRADDR2_CLR; /**< ECC Error Address 2 */ 90 __IM uint32_t ECCERRADDR3_CLR; /**< ECC Error Address 3 */ 91 __IM uint32_t ECCMERRIND_CLR; /**< Multiple ECC error indication */ 92 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 93 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 94 __IOM uint32_t RAMBANKSVALID_CLR; /**< New Register */ 95 __IOM uint32_t CFGSRTOP_CLR; /**< Sequential Region on Top */ 96 __IOM uint32_t CFGSRMAP_CLR; /**< Sequential Region Map */ 97 __IOM uint32_t CFGIU0MAP_CLR; /**< Interleaving Unit 0 Map */ 98 __IOM uint32_t CFGIU1MAP_CLR; /**< Interleaving Unit 1 Map */ 99 __IOM uint32_t CFGIU2MAP_CLR; /**< Interleaving Unit 2 Map */ 100 __IOM uint32_t CFGIU3MAP_CLR; /**< Interleaving Unit 3 Map */ 101 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 102 uint32_t RESERVED5[1006U]; /**< Reserved for future use */ 103 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 104 __IOM uint32_t CMD_TGL; /**< Command register */ 105 __IOM uint32_t CTRL_TGL; /**< Control register */ 106 __IM uint32_t ECCERRADDR0_TGL; /**< ECC Error Address 0 */ 107 __IM uint32_t ECCERRADDR1_TGL; /**< ECC Error Address 1 */ 108 __IM uint32_t ECCERRADDR2_TGL; /**< ECC Error Address 2 */ 109 __IM uint32_t ECCERRADDR3_TGL; /**< ECC Error Address 3 */ 110 __IM uint32_t ECCMERRIND_TGL; /**< Multiple ECC error indication */ 111 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 112 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 113 __IOM uint32_t RAMBANKSVALID_TGL; /**< New Register */ 114 __IOM uint32_t CFGSRTOP_TGL; /**< Sequential Region on Top */ 115 __IOM uint32_t CFGSRMAP_TGL; /**< Sequential Region Map */ 116 __IOM uint32_t CFGIU0MAP_TGL; /**< Interleaving Unit 0 Map */ 117 __IOM uint32_t CFGIU1MAP_TGL; /**< Interleaving Unit 1 Map */ 118 __IOM uint32_t CFGIU2MAP_TGL; /**< Interleaving Unit 2 Map */ 119 __IOM uint32_t CFGIU3MAP_TGL; /**< Interleaving Unit 3 Map */ 120 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 121 } MPAHBRAM_TypeDef; 122 /** @} End of group EFR32MG24_MPAHBRAM */ 123 124 /**************************************************************************//** 125 * @addtogroup EFR32MG24_MPAHBRAM 126 * @{ 127 * @defgroup EFR32MG24_MPAHBRAM_BitFields MPAHBRAM Bit Fields 128 * @{ 129 *****************************************************************************/ 130 131 /* Bit fields for MPAHBRAM IPVERSION */ 132 #define _MPAHBRAM_IPVERSION_RESETVALUE 0x00000002UL /**< Default value for MPAHBRAM_IPVERSION */ 133 #define _MPAHBRAM_IPVERSION_MASK 0x00000003UL /**< Mask for MPAHBRAM_IPVERSION */ 134 #define _MPAHBRAM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for MPAHBRAM_IPVERSION */ 135 #define _MPAHBRAM_IPVERSION_IPVERSION_MASK 0x3UL /**< Bit mask for MPAHBRAM_IPVERSION */ 136 #define _MPAHBRAM_IPVERSION_IPVERSION_DEFAULT 0x00000002UL /**< Mode DEFAULT for MPAHBRAM_IPVERSION */ 137 #define MPAHBRAM_IPVERSION_IPVERSION_DEFAULT (_MPAHBRAM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IPVERSION */ 138 139 /* Bit fields for MPAHBRAM CMD */ 140 #define _MPAHBRAM_CMD_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CMD */ 141 #define _MPAHBRAM_CMD_MASK 0x0000000FUL /**< Mask for MPAHBRAM_CMD */ 142 #define MPAHBRAM_CMD_CLEARECCADDR0 (0x1UL << 0) /**< Clear ECCERRADDR0 */ 143 #define _MPAHBRAM_CMD_CLEARECCADDR0_SHIFT 0 /**< Shift value for MPAHBRAM_CLEARECCADDR0 */ 144 #define _MPAHBRAM_CMD_CLEARECCADDR0_MASK 0x1UL /**< Bit mask for MPAHBRAM_CLEARECCADDR0 */ 145 #define _MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 146 #define MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 147 #define MPAHBRAM_CMD_CLEARECCADDR1 (0x1UL << 1) /**< Clear ECCERRADDR1 */ 148 #define _MPAHBRAM_CMD_CLEARECCADDR1_SHIFT 1 /**< Shift value for MPAHBRAM_CLEARECCADDR1 */ 149 #define _MPAHBRAM_CMD_CLEARECCADDR1_MASK 0x2UL /**< Bit mask for MPAHBRAM_CLEARECCADDR1 */ 150 #define _MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 151 #define MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 152 #define MPAHBRAM_CMD_CLEARECCADDR2 (0x1UL << 2) /**< Clear ECCERRADDR2 */ 153 #define _MPAHBRAM_CMD_CLEARECCADDR2_SHIFT 2 /**< Shift value for MPAHBRAM_CLEARECCADDR2 */ 154 #define _MPAHBRAM_CMD_CLEARECCADDR2_MASK 0x4UL /**< Bit mask for MPAHBRAM_CLEARECCADDR2 */ 155 #define _MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 156 #define MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 157 #define MPAHBRAM_CMD_CLEARECCADDR3 (0x1UL << 3) /**< Clear ECCERRADDR3 */ 158 #define _MPAHBRAM_CMD_CLEARECCADDR3_SHIFT 3 /**< Shift value for MPAHBRAM_CLEARECCADDR3 */ 159 #define _MPAHBRAM_CMD_CLEARECCADDR3_MASK 0x8UL /**< Bit mask for MPAHBRAM_CLEARECCADDR3 */ 160 #define _MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CMD */ 161 #define MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT (_MPAHBRAM_CMD_CLEARECCADDR3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CMD */ 162 163 /* Bit fields for MPAHBRAM CTRL */ 164 #define _MPAHBRAM_CTRL_RESETVALUE 0x00000040UL /**< Default value for MPAHBRAM_CTRL */ 165 #define _MPAHBRAM_CTRL_MASK 0x000000FFUL /**< Mask for MPAHBRAM_CTRL */ 166 #define MPAHBRAM_CTRL_ECCEN (0x1UL << 0) /**< Enable ECC functionality */ 167 #define _MPAHBRAM_CTRL_ECCEN_SHIFT 0 /**< Shift value for MPAHBRAM_ECCEN */ 168 #define _MPAHBRAM_CTRL_ECCEN_MASK 0x1UL /**< Bit mask for MPAHBRAM_ECCEN */ 169 #define _MPAHBRAM_CTRL_ECCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 170 #define MPAHBRAM_CTRL_ECCEN_DEFAULT (_MPAHBRAM_CTRL_ECCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 171 #define MPAHBRAM_CTRL_ECCWEN (0x1UL << 1) /**< Enable ECC syndrome writes */ 172 #define _MPAHBRAM_CTRL_ECCWEN_SHIFT 1 /**< Shift value for MPAHBRAM_ECCWEN */ 173 #define _MPAHBRAM_CTRL_ECCWEN_MASK 0x2UL /**< Bit mask for MPAHBRAM_ECCWEN */ 174 #define _MPAHBRAM_CTRL_ECCWEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 175 #define MPAHBRAM_CTRL_ECCWEN_DEFAULT (_MPAHBRAM_CTRL_ECCWEN_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 176 #define MPAHBRAM_CTRL_ECCERRFAULTEN (0x1UL << 2) /**< ECC Error bus fault enable */ 177 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_SHIFT 2 /**< Shift value for MPAHBRAM_ECCERRFAULTEN */ 178 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_MASK 0x4UL /**< Bit mask for MPAHBRAM_ECCERRFAULTEN */ 179 #define _MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 180 #define MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ECCERRFAULTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 181 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_SHIFT 3 /**< Shift value for MPAHBRAM_AHBPORTPRIORITY */ 182 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_MASK 0x38UL /**< Bit mask for MPAHBRAM_AHBPORTPRIORITY */ 183 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 184 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE 0x00000000UL /**< Mode NONE for MPAHBRAM_CTRL */ 185 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 0x00000001UL /**< Mode PORT0 for MPAHBRAM_CTRL */ 186 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 0x00000002UL /**< Mode PORT1 for MPAHBRAM_CTRL */ 187 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 0x00000003UL /**< Mode PORT2 for MPAHBRAM_CTRL */ 188 #define _MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 0x00000004UL /**< Mode PORT3 for MPAHBRAM_CTRL */ 189 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT (_MPAHBRAM_CTRL_AHBPORTPRIORITY_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 190 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE (_MPAHBRAM_CTRL_AHBPORTPRIORITY_NONE << 3) /**< Shifted mode NONE for MPAHBRAM_CTRL */ 191 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT0 << 3) /**< Shifted mode PORT0 for MPAHBRAM_CTRL */ 192 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT1 << 3) /**< Shifted mode PORT1 for MPAHBRAM_CTRL */ 193 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT2 << 3) /**< Shifted mode PORT2 for MPAHBRAM_CTRL */ 194 #define MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 (_MPAHBRAM_CTRL_AHBPORTPRIORITY_PORT3 << 3) /**< Shifted mode PORT3 for MPAHBRAM_CTRL */ 195 #define MPAHBRAM_CTRL_ADDRFAULTEN (0x1UL << 6) /**< Address fault bus fault enable */ 196 #define _MPAHBRAM_CTRL_ADDRFAULTEN_SHIFT 6 /**< Shift value for MPAHBRAM_ADDRFAULTEN */ 197 #define _MPAHBRAM_CTRL_ADDRFAULTEN_MASK 0x40UL /**< Bit mask for MPAHBRAM_ADDRFAULTEN */ 198 #define _MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 199 #define MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT (_MPAHBRAM_CTRL_ADDRFAULTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 200 #define MPAHBRAM_CTRL_WAITSTATES (0x1UL << 7) /**< RAM read wait states */ 201 #define _MPAHBRAM_CTRL_WAITSTATES_SHIFT 7 /**< Shift value for MPAHBRAM_WAITSTATES */ 202 #define _MPAHBRAM_CTRL_WAITSTATES_MASK 0x80UL /**< Bit mask for MPAHBRAM_WAITSTATES */ 203 #define _MPAHBRAM_CTRL_WAITSTATES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CTRL */ 204 #define MPAHBRAM_CTRL_WAITSTATES_DEFAULT (_MPAHBRAM_CTRL_WAITSTATES_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_CTRL */ 205 206 /* Bit fields for MPAHBRAM ECCERRADDR0 */ 207 #define _MPAHBRAM_ECCERRADDR0_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR0 */ 208 #define _MPAHBRAM_ECCERRADDR0_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR0 */ 209 #define _MPAHBRAM_ECCERRADDR0_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 210 #define _MPAHBRAM_ECCERRADDR0_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 211 #define _MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR0 */ 212 #define MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR0_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR0*/ 213 214 /* Bit fields for MPAHBRAM ECCERRADDR1 */ 215 #define _MPAHBRAM_ECCERRADDR1_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR1 */ 216 #define _MPAHBRAM_ECCERRADDR1_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR1 */ 217 #define _MPAHBRAM_ECCERRADDR1_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 218 #define _MPAHBRAM_ECCERRADDR1_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 219 #define _MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR1 */ 220 #define MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR1_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR1*/ 221 222 /* Bit fields for MPAHBRAM ECCERRADDR2 */ 223 #define _MPAHBRAM_ECCERRADDR2_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR2 */ 224 #define _MPAHBRAM_ECCERRADDR2_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR2 */ 225 #define _MPAHBRAM_ECCERRADDR2_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 226 #define _MPAHBRAM_ECCERRADDR2_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 227 #define _MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR2 */ 228 #define MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR2_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR2*/ 229 230 /* Bit fields for MPAHBRAM ECCERRADDR3 */ 231 #define _MPAHBRAM_ECCERRADDR3_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCERRADDR3 */ 232 #define _MPAHBRAM_ECCERRADDR3_MASK 0xFFFFFFFFUL /**< Mask for MPAHBRAM_ECCERRADDR3 */ 233 #define _MPAHBRAM_ECCERRADDR3_ADDR_SHIFT 0 /**< Shift value for MPAHBRAM_ADDR */ 234 #define _MPAHBRAM_ECCERRADDR3_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for MPAHBRAM_ADDR */ 235 #define _MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCERRADDR3 */ 236 #define MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT (_MPAHBRAM_ECCERRADDR3_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCERRADDR3*/ 237 238 /* Bit fields for MPAHBRAM ECCMERRIND */ 239 #define _MPAHBRAM_ECCMERRIND_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_ECCMERRIND */ 240 #define _MPAHBRAM_ECCMERRIND_MASK 0x0000000FUL /**< Mask for MPAHBRAM_ECCMERRIND */ 241 #define MPAHBRAM_ECCMERRIND_P0 (0x1UL << 0) /**< Multiple ECC errors on AHB port 0 */ 242 #define _MPAHBRAM_ECCMERRIND_P0_SHIFT 0 /**< Shift value for MPAHBRAM_P0 */ 243 #define _MPAHBRAM_ECCMERRIND_P0_MASK 0x1UL /**< Bit mask for MPAHBRAM_P0 */ 244 #define _MPAHBRAM_ECCMERRIND_P0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 245 #define MPAHBRAM_ECCMERRIND_P0_DEFAULT (_MPAHBRAM_ECCMERRIND_P0_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 246 #define MPAHBRAM_ECCMERRIND_P1 (0x1UL << 1) /**< Multiple ECC errors on AHB port 1 */ 247 #define _MPAHBRAM_ECCMERRIND_P1_SHIFT 1 /**< Shift value for MPAHBRAM_P1 */ 248 #define _MPAHBRAM_ECCMERRIND_P1_MASK 0x2UL /**< Bit mask for MPAHBRAM_P1 */ 249 #define _MPAHBRAM_ECCMERRIND_P1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 250 #define MPAHBRAM_ECCMERRIND_P1_DEFAULT (_MPAHBRAM_ECCMERRIND_P1_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 251 #define MPAHBRAM_ECCMERRIND_P2 (0x1UL << 2) /**< Multiple ECC errors on AHB port 2 */ 252 #define _MPAHBRAM_ECCMERRIND_P2_SHIFT 2 /**< Shift value for MPAHBRAM_P2 */ 253 #define _MPAHBRAM_ECCMERRIND_P2_MASK 0x4UL /**< Bit mask for MPAHBRAM_P2 */ 254 #define _MPAHBRAM_ECCMERRIND_P2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 255 #define MPAHBRAM_ECCMERRIND_P2_DEFAULT (_MPAHBRAM_ECCMERRIND_P2_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 256 #define MPAHBRAM_ECCMERRIND_P3 (0x1UL << 3) /**< Multiple ECC errors on AHB port 2 */ 257 #define _MPAHBRAM_ECCMERRIND_P3_SHIFT 3 /**< Shift value for MPAHBRAM_P3 */ 258 #define _MPAHBRAM_ECCMERRIND_P3_MASK 0x8UL /**< Bit mask for MPAHBRAM_P3 */ 259 #define _MPAHBRAM_ECCMERRIND_P3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_ECCMERRIND */ 260 #define MPAHBRAM_ECCMERRIND_P3_DEFAULT (_MPAHBRAM_ECCMERRIND_P3_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_ECCMERRIND*/ 261 262 /* Bit fields for MPAHBRAM IF */ 263 #define _MPAHBRAM_IF_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IF */ 264 #define _MPAHBRAM_IF_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IF */ 265 #define MPAHBRAM_IF_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Flag */ 266 #define _MPAHBRAM_IF_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ 267 #define _MPAHBRAM_IF_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ 268 #define _MPAHBRAM_IF_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 269 #define MPAHBRAM_IF_AHB0ERR1B_DEFAULT (_MPAHBRAM_IF_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 270 #define MPAHBRAM_IF_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Flag */ 271 #define _MPAHBRAM_IF_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ 272 #define _MPAHBRAM_IF_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ 273 #define _MPAHBRAM_IF_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 274 #define MPAHBRAM_IF_AHB1ERR1B_DEFAULT (_MPAHBRAM_IF_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 275 #define MPAHBRAM_IF_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Flag */ 276 #define _MPAHBRAM_IF_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ 277 #define _MPAHBRAM_IF_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ 278 #define _MPAHBRAM_IF_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 279 #define MPAHBRAM_IF_AHB2ERR1B_DEFAULT (_MPAHBRAM_IF_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 280 #define MPAHBRAM_IF_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Flag */ 281 #define _MPAHBRAM_IF_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ 282 #define _MPAHBRAM_IF_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ 283 #define _MPAHBRAM_IF_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 284 #define MPAHBRAM_IF_AHB3ERR1B_DEFAULT (_MPAHBRAM_IF_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 285 #define MPAHBRAM_IF_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Flag */ 286 #define _MPAHBRAM_IF_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ 287 #define _MPAHBRAM_IF_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ 288 #define _MPAHBRAM_IF_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 289 #define MPAHBRAM_IF_AHB0ERR2B_DEFAULT (_MPAHBRAM_IF_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 290 #define MPAHBRAM_IF_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Flag */ 291 #define _MPAHBRAM_IF_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ 292 #define _MPAHBRAM_IF_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ 293 #define _MPAHBRAM_IF_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 294 #define MPAHBRAM_IF_AHB1ERR2B_DEFAULT (_MPAHBRAM_IF_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 295 #define MPAHBRAM_IF_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Flag */ 296 #define _MPAHBRAM_IF_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ 297 #define _MPAHBRAM_IF_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ 298 #define _MPAHBRAM_IF_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 299 #define MPAHBRAM_IF_AHB2ERR2B_DEFAULT (_MPAHBRAM_IF_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 300 #define MPAHBRAM_IF_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Flag */ 301 #define _MPAHBRAM_IF_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ 302 #define _MPAHBRAM_IF_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ 303 #define _MPAHBRAM_IF_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IF */ 304 #define MPAHBRAM_IF_AHB3ERR2B_DEFAULT (_MPAHBRAM_IF_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IF */ 305 306 /* Bit fields for MPAHBRAM IEN */ 307 #define _MPAHBRAM_IEN_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_IEN */ 308 #define _MPAHBRAM_IEN_MASK 0x000000FFUL /**< Mask for MPAHBRAM_IEN */ 309 #define MPAHBRAM_IEN_AHB0ERR1B (0x1UL << 0) /**< AHB0 1-bit ECC Error Interrupt Enable */ 310 #define _MPAHBRAM_IEN_AHB0ERR1B_SHIFT 0 /**< Shift value for MPAHBRAM_AHB0ERR1B */ 311 #define _MPAHBRAM_IEN_AHB0ERR1B_MASK 0x1UL /**< Bit mask for MPAHBRAM_AHB0ERR1B */ 312 #define _MPAHBRAM_IEN_AHB0ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 313 #define MPAHBRAM_IEN_AHB0ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR1B_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 314 #define MPAHBRAM_IEN_AHB1ERR1B (0x1UL << 1) /**< AHB1 1-bit ECC Error Interrupt Enable */ 315 #define _MPAHBRAM_IEN_AHB1ERR1B_SHIFT 1 /**< Shift value for MPAHBRAM_AHB1ERR1B */ 316 #define _MPAHBRAM_IEN_AHB1ERR1B_MASK 0x2UL /**< Bit mask for MPAHBRAM_AHB1ERR1B */ 317 #define _MPAHBRAM_IEN_AHB1ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 318 #define MPAHBRAM_IEN_AHB1ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR1B_DEFAULT << 1) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 319 #define MPAHBRAM_IEN_AHB2ERR1B (0x1UL << 2) /**< AHB2 1-bit ECC Error Interrupt Enable */ 320 #define _MPAHBRAM_IEN_AHB2ERR1B_SHIFT 2 /**< Shift value for MPAHBRAM_AHB2ERR1B */ 321 #define _MPAHBRAM_IEN_AHB2ERR1B_MASK 0x4UL /**< Bit mask for MPAHBRAM_AHB2ERR1B */ 322 #define _MPAHBRAM_IEN_AHB2ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 323 #define MPAHBRAM_IEN_AHB2ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR1B_DEFAULT << 2) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 324 #define MPAHBRAM_IEN_AHB3ERR1B (0x1UL << 3) /**< AHB3 1-bit ECC Error Interrupt Enable */ 325 #define _MPAHBRAM_IEN_AHB3ERR1B_SHIFT 3 /**< Shift value for MPAHBRAM_AHB3ERR1B */ 326 #define _MPAHBRAM_IEN_AHB3ERR1B_MASK 0x8UL /**< Bit mask for MPAHBRAM_AHB3ERR1B */ 327 #define _MPAHBRAM_IEN_AHB3ERR1B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 328 #define MPAHBRAM_IEN_AHB3ERR1B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR1B_DEFAULT << 3) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 329 #define MPAHBRAM_IEN_AHB0ERR2B (0x1UL << 4) /**< AHB0 2-bit ECC Error Interrupt Enable */ 330 #define _MPAHBRAM_IEN_AHB0ERR2B_SHIFT 4 /**< Shift value for MPAHBRAM_AHB0ERR2B */ 331 #define _MPAHBRAM_IEN_AHB0ERR2B_MASK 0x10UL /**< Bit mask for MPAHBRAM_AHB0ERR2B */ 332 #define _MPAHBRAM_IEN_AHB0ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 333 #define MPAHBRAM_IEN_AHB0ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB0ERR2B_DEFAULT << 4) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 334 #define MPAHBRAM_IEN_AHB1ERR2B (0x1UL << 5) /**< AHB1 2-bit ECC Error Interrupt Enable */ 335 #define _MPAHBRAM_IEN_AHB1ERR2B_SHIFT 5 /**< Shift value for MPAHBRAM_AHB1ERR2B */ 336 #define _MPAHBRAM_IEN_AHB1ERR2B_MASK 0x20UL /**< Bit mask for MPAHBRAM_AHB1ERR2B */ 337 #define _MPAHBRAM_IEN_AHB1ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 338 #define MPAHBRAM_IEN_AHB1ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB1ERR2B_DEFAULT << 5) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 339 #define MPAHBRAM_IEN_AHB2ERR2B (0x1UL << 6) /**< AHB2 2-bit ECC Error Interrupt Enable */ 340 #define _MPAHBRAM_IEN_AHB2ERR2B_SHIFT 6 /**< Shift value for MPAHBRAM_AHB2ERR2B */ 341 #define _MPAHBRAM_IEN_AHB2ERR2B_MASK 0x40UL /**< Bit mask for MPAHBRAM_AHB2ERR2B */ 342 #define _MPAHBRAM_IEN_AHB2ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 343 #define MPAHBRAM_IEN_AHB2ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB2ERR2B_DEFAULT << 6) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 344 #define MPAHBRAM_IEN_AHB3ERR2B (0x1UL << 7) /**< AHB3 2-bit ECC Error Interrupt Enable */ 345 #define _MPAHBRAM_IEN_AHB3ERR2B_SHIFT 7 /**< Shift value for MPAHBRAM_AHB3ERR2B */ 346 #define _MPAHBRAM_IEN_AHB3ERR2B_MASK 0x80UL /**< Bit mask for MPAHBRAM_AHB3ERR2B */ 347 #define _MPAHBRAM_IEN_AHB3ERR2B_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_IEN */ 348 #define MPAHBRAM_IEN_AHB3ERR2B_DEFAULT (_MPAHBRAM_IEN_AHB3ERR2B_DEFAULT << 7) /**< Shifted mode DEFAULT for MPAHBRAM_IEN */ 349 350 /* Bit fields for MPAHBRAM RAMBANKSVALID */ 351 #define _MPAHBRAM_RAMBANKSVALID_RESETVALUE 0xFFFFFFFFUL /**< Default value for MPAHBRAM_RAMBANKSVALID */ 352 #define _MPAHBRAM_RAMBANKSVALID_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_RAMBANKSVALID */ 353 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_SHIFT 0 /**< Shift value for MPAHBRAM_RAMBANKSVALID */ 354 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_RAMBANKSVALID */ 355 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for MPAHBRAM_RAMBANKSVALID */ 356 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 0x00000001UL /**< Mode BLK0 for MPAHBRAM_RAMBANKSVALID */ 357 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for MPAHBRAM_RAMBANKSVALID */ 358 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 0x00000007UL /**< Mode BLK0TO2 for MPAHBRAM_RAMBANKSVALID */ 359 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for MPAHBRAM_RAMBANKSVALID */ 360 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 0x0000001FUL /**< Mode BLK0TO4 for MPAHBRAM_RAMBANKSVALID */ 361 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 0x0000003FUL /**< Mode BLK0TO5 for MPAHBRAM_RAMBANKSVALID */ 362 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 0x0000007FUL /**< Mode BLK0TO6 for MPAHBRAM_RAMBANKSVALID */ 363 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for MPAHBRAM_RAMBANKSVALID */ 364 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 0x000001FFUL /**< Mode BLK0TO8 for MPAHBRAM_RAMBANKSVALID */ 365 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 0x000003FFUL /**< Mode BLK0TO9 for MPAHBRAM_RAMBANKSVALID */ 366 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 0x000007FFUL /**< Mode BLK0TO10 for MPAHBRAM_RAMBANKSVALID */ 367 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 0x00000FFFUL /**< Mode BLK0TO11 for MPAHBRAM_RAMBANKSVALID */ 368 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 0x00001FFFUL /**< Mode BLK0TO12 for MPAHBRAM_RAMBANKSVALID */ 369 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 0x00003FFFUL /**< Mode BLK0TO13 for MPAHBRAM_RAMBANKSVALID */ 370 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 0x00007FFFUL /**< Mode BLK0TO14 for MPAHBRAM_RAMBANKSVALID */ 371 #define _MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 0x0000FFFFUL /**< Mode BLK0TO15 for MPAHBRAM_RAMBANKSVALID */ 372 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_RAMBANKSVALID*/ 373 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0 << 0) /**< Shifted mode BLK0 for MPAHBRAM_RAMBANKSVALID*/ 374 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for MPAHBRAM_RAMBANKSVALID*/ 375 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO2 << 0) /**< Shifted mode BLK0TO2 for MPAHBRAM_RAMBANKSVALID*/ 376 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for MPAHBRAM_RAMBANKSVALID*/ 377 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO4 << 0) /**< Shifted mode BLK0TO4 for MPAHBRAM_RAMBANKSVALID*/ 378 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO5 << 0) /**< Shifted mode BLK0TO5 for MPAHBRAM_RAMBANKSVALID*/ 379 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO6 << 0) /**< Shifted mode BLK0TO6 for MPAHBRAM_RAMBANKSVALID*/ 380 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for MPAHBRAM_RAMBANKSVALID*/ 381 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO8 << 0) /**< Shifted mode BLK0TO8 for MPAHBRAM_RAMBANKSVALID*/ 382 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO9 << 0) /**< Shifted mode BLK0TO9 for MPAHBRAM_RAMBANKSVALID*/ 383 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO10 << 0) /**< Shifted mode BLK0TO10 for MPAHBRAM_RAMBANKSVALID*/ 384 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO11 << 0) /**< Shifted mode BLK0TO11 for MPAHBRAM_RAMBANKSVALID*/ 385 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO12 << 0) /**< Shifted mode BLK0TO12 for MPAHBRAM_RAMBANKSVALID*/ 386 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO13 << 0) /**< Shifted mode BLK0TO13 for MPAHBRAM_RAMBANKSVALID*/ 387 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO14 << 0) /**< Shifted mode BLK0TO14 for MPAHBRAM_RAMBANKSVALID*/ 388 #define MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 (_MPAHBRAM_RAMBANKSVALID_RAMBANKSVALID_BLK0TO15 << 0) /**< Shifted mode BLK0TO15 for MPAHBRAM_RAMBANKSVALID*/ 389 390 /* Bit fields for MPAHBRAM CFGSRTOP */ 391 #define _MPAHBRAM_CFGSRTOP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGSRTOP */ 392 #define _MPAHBRAM_CFGSRTOP_MASK 0x00000001UL /**< Mask for MPAHBRAM_CFGSRTOP */ 393 #define MPAHBRAM_CFGSRTOP_SRTOP (0x1UL << 0) /**< Sequential region on top */ 394 #define _MPAHBRAM_CFGSRTOP_SRTOP_SHIFT 0 /**< Shift value for MPAHBRAM_SRTOP */ 395 #define _MPAHBRAM_CFGSRTOP_SRTOP_MASK 0x1UL /**< Bit mask for MPAHBRAM_SRTOP */ 396 #define _MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGSRTOP */ 397 #define MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT (_MPAHBRAM_CFGSRTOP_SRTOP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGSRTOP */ 398 399 /* Bit fields for MPAHBRAM CFGSRMAP */ 400 #define _MPAHBRAM_CFGSRMAP_RESETVALUE 0xFFFFFFFFUL /**< Default value for MPAHBRAM_CFGSRMAP */ 401 #define _MPAHBRAM_CFGSRMAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGSRMAP */ 402 #define _MPAHBRAM_CFGSRMAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ 403 #define _MPAHBRAM_CFGSRMAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ 404 #define _MPAHBRAM_CFGSRMAP_MAP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for MPAHBRAM_CFGSRMAP */ 405 #define MPAHBRAM_CFGSRMAP_MAP_DEFAULT (_MPAHBRAM_CFGSRMAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGSRMAP */ 406 407 /* Bit fields for MPAHBRAM CFGIU0MAP */ 408 #define _MPAHBRAM_CFGIU0MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU0MAP */ 409 #define _MPAHBRAM_CFGIU0MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU0MAP */ 410 #define _MPAHBRAM_CFGIU0MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ 411 #define _MPAHBRAM_CFGIU0MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ 412 #define _MPAHBRAM_CFGIU0MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU0MAP */ 413 #define MPAHBRAM_CFGIU0MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU0MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU0MAP */ 414 415 /* Bit fields for MPAHBRAM CFGIU1MAP */ 416 #define _MPAHBRAM_CFGIU1MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU1MAP */ 417 #define _MPAHBRAM_CFGIU1MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU1MAP */ 418 #define _MPAHBRAM_CFGIU1MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ 419 #define _MPAHBRAM_CFGIU1MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ 420 #define _MPAHBRAM_CFGIU1MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU1MAP */ 421 #define MPAHBRAM_CFGIU1MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU1MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU1MAP */ 422 423 /* Bit fields for MPAHBRAM CFGIU2MAP */ 424 #define _MPAHBRAM_CFGIU2MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU2MAP */ 425 #define _MPAHBRAM_CFGIU2MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU2MAP */ 426 #define _MPAHBRAM_CFGIU2MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ 427 #define _MPAHBRAM_CFGIU2MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ 428 #define _MPAHBRAM_CFGIU2MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU2MAP */ 429 #define MPAHBRAM_CFGIU2MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU2MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU2MAP */ 430 431 /* Bit fields for MPAHBRAM CFGIU3MAP */ 432 #define _MPAHBRAM_CFGIU3MAP_RESETVALUE 0x00000000UL /**< Default value for MPAHBRAM_CFGIU3MAP */ 433 #define _MPAHBRAM_CFGIU3MAP_MASK 0x0000FFFFUL /**< Mask for MPAHBRAM_CFGIU3MAP */ 434 #define _MPAHBRAM_CFGIU3MAP_MAP_SHIFT 0 /**< Shift value for MPAHBRAM_MAP */ 435 #define _MPAHBRAM_CFGIU3MAP_MAP_MASK 0xFFFFUL /**< Bit mask for MPAHBRAM_MAP */ 436 #define _MPAHBRAM_CFGIU3MAP_MAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for MPAHBRAM_CFGIU3MAP */ 437 #define MPAHBRAM_CFGIU3MAP_MAP_DEFAULT (_MPAHBRAM_CFGIU3MAP_MAP_DEFAULT << 0) /**< Shifted mode DEFAULT for MPAHBRAM_CFGIU3MAP */ 438 439 /** @} End of group EFR32MG24_MPAHBRAM_BitFields */ 440 /** @} End of group EFR32MG24_MPAHBRAM */ 441 /** @} End of group Parts */ 442 443 #endif /* EFR32MG24_MPAHBRAM_H */ 444
