1 /***************************************************************************//**
2 * @file
3 * @brief HFXO Manager HAL series 2 Devices.
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2019 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30 #include "em_device.h"
31 #if defined(_SILICON_LABS_32B_SERIES_2)
32 #include "sl_assert.h"
33 #include "sli_hfxo_manager.h"
34 #include "sl_hfxo_manager.h"
35 #include "sl_hfxo_manager_config.h"
36 #include "sl_status.h"
37
38 #include <stdbool.h>
39
40 /*******************************************************************************
41 ********************************* DEFINES *********************************
42 ******************************************************************************/
43
44 // Defines for hidden field FORCERAWCLK in HFXO_CTRL register
45 #define _HFXO_MANAGER_CTRL_FORCERAWCLK_SHIFT 31
46 #define _HFXO_MANAGER_CTRL_FORCERAWCLK_MASK 0x80000000UL
47 #define HFXO_MANAGER_CTRL_FORCERAWCLK (0x1UL << _HFXO_MANAGER_CTRL_FORCERAWCLK_SHIFT)
48
49 // Defines for hidden PKDETCTRL register
50 #ifndef _HFXO_PKDETCTRL_MASK
51 #if (_SILICON_LABS_32B_SERIES_2_CONFIG <= 2)
52 #define PKDETCTRL RESERVED4[2]
53 #else
54 #define PKDETCTRL RESERVED3[0]
55 #endif
56 #endif
57 #define _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT 8
58 #define _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK 0xF00UL
59 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V105MV (0x00000000UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
60 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V132MV (0x00000001UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
61 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V157MV (0x00000002UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
62 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V184MV (0x00000003UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
63 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V210MV (0x00000004UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
64 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V236MV (0x00000005UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
65 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V262MV (0x00000006UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
66 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V289MV (0x00000007UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
67 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V315MV (0x00000008UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
68 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V341MV (0x00000009UL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
69 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V367MV (0x0000000AUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
70 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V394MV (0x0000000BUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
71 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V420MV (0x0000000CUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
72 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V446MV (0x0000000DUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
73 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V472MV (0x0000000EUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
74 #define HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V499MV (0x0000000FUL << _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_SHIFT)
75
76 // IRQ Name depending on devices
77 #if defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
78 #define HFXO_IRQ_NUMBER HFXO00_IRQn
79 #define HFXO_IRQ_HANDLER_FUNCTION HFXO00_IRQHandler
80 #else
81 #define HFXO_IRQ_NUMBER HFXO0_IRQn
82 #define HFXO_IRQ_HANDLER_FUNCTION HFXO0_IRQHandler
83 #endif
84
85 // Default values for the Sleepy Crystal settings
86 // Should be enough to guaranty HFXO startup
87 #define SLEEPY_XTAL_SETTING_DEFAULT_PKDETTHSTARTUPI HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_V157MV
88 #define SLEEPY_XTAL_SETTING_DEFAULT_CTUNEANA 100u
89 #define SLEEPY_XTAL_SETTING_DEFAULT_COREBIAS 255u
90
91 /*******************************************************************************
92 *************************** LOCAL VARIABLES ********************************
93 ******************************************************************************/
94
95 // Error flag to indicate if we failed the startup process
96 static bool error_flag = false;
97 #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1)
98 // Error retry counter
99 static uint8_t error_try_cnt = 0;
100
101 // Error State status
102 static bool in_error_state = false;
103
104 // Variables to save normal settings
105 static uint32_t pkdettusstartupi_saved;
106 static uint32_t ctunexiana_saved;
107 static uint32_t ctunexoana_saved;
108 static uint32_t corebiasana_saved;
109 static uint32_t corebiasstartup_saved;
110 static uint32_t corebiasstartupi_saved;
111
112 // Variables for Sleepy Crystal settings
113 static uint32_t sleepy_xtal_settings_pkdettusstartupi = SLEEPY_XTAL_SETTING_DEFAULT_PKDETTHSTARTUPI; // Value already shifted
114 static uint32_t sleepy_xtal_settings_ctuneana = SLEEPY_XTAL_SETTING_DEFAULT_CTUNEANA;
115 static uint32_t sleepy_xtal_settings_corebias = SLEEPY_XTAL_SETTING_DEFAULT_COREBIAS;
116 #endif
117
118 /***************************************************************************//**
119 * HFXO ready notification callback for internal use with power manager
120 ******************************************************************************/
121 __WEAK void sli_hfxo_manager_notify_ready_for_power_manager(void);
122
123 /***************************************************************************//**
124 * Hardware specific initialization.
125 ******************************************************************************/
sli_hfxo_manager_init_hardware(void)126 void sli_hfxo_manager_init_hardware(void)
127 {
128 // Increase HFXO Interrupt priority so that it won't be masked by BASEPRI
129 // and will preempt other interrupts.
130 NVIC_SetPriority(HFXO_IRQ_NUMBER, 2);
131
132 // Enable HFXO Interrupt if HFXO is used
133 #if _SILICON_LABS_32B_SERIES_2_CONFIG >= 2
134 CMU->CLKEN0_SET = CMU_CLKEN0_HFXO0;
135 #endif
136
137 HFXO0->IEN_CLR = HFXO_IEN_RDY | HFXO_IEN_DNSERR | HFXO_IEN_COREBIASOPTERR;
138 HFXO0->IF_CLR = HFXO_IF_RDY | HFXO_IF_DNSERR | HFXO_IEN_COREBIASOPTERR;
139
140 NVIC_ClearPendingIRQ(HFXO_IRQ_NUMBER);
141 NVIC_EnableIRQ(HFXO_IRQ_NUMBER);
142
143 HFXO0->IEN_SET = HFXO_IEN_RDY | HFXO_IEN_DNSERR | HFXO_IEN_COREBIASOPTERR;
144 }
145
146 /***************************************************************************//**
147 * Updates sleepy crystal settings in specific hardware registers.
148 ******************************************************************************/
sli_hfxo_manager_update_sleepy_xtal_settings_hardware(sl_hfxo_manager_sleepy_xtal_settings_t * settings)149 sl_status_t sli_hfxo_manager_update_sleepy_xtal_settings_hardware(sl_hfxo_manager_sleepy_xtal_settings_t *settings)
150 {
151 (void)settings;
152
153 #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1)
154 EFM_ASSERT(settings->ana_ctune <= (_HFXO_XTALCTRL_CTUNEXIANA_MASK >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT));
155 EFM_ASSERT(settings->core_bias_current <= (_HFXO_XTALCTRL_COREBIASANA_MASK >> _HFXO_XTALCTRL_COREBIASANA_SHIFT));
156
157 sleepy_xtal_settings_ctuneana = settings->ana_ctune;
158 sleepy_xtal_settings_corebias = settings->core_bias_current;
159
160 return SL_STATUS_OK;
161 #else
162 return SL_STATUS_NOT_AVAILABLE;
163 #endif
164 }
165
166 /***************************************************************************//**
167 * Checks if HFXO is ready and, if needed, waits for it to be.
168 *
169 * @note This will also make sure we are not in the process of restarting HFXO
170 * with different settings.
171 ******************************************************************************/
sli_hfxo_manager_is_hfxo_ready(bool wait)172 bool sli_hfxo_manager_is_hfxo_ready(bool wait)
173 {
174 bool ready = false;
175
176 do {
177 ready = (((HFXO0->STATUS & HFXO_STATUS_RDY) != 0) && !error_flag) ? true : false;
178 } while (!ready && wait);
179
180 return ready;
181 }
182
183 #if (SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER == 0)
184 /*******************************************************************************
185 * HFXO interrupt handler.
186 *
187 * @note The HFXOx_IRQHandler provided by HFXO Manager will call
188 * @ref sl_hfxo_manager_irq_handler. Configure SL_HFXO_MANAGER_CUSTOM_HFXO_IRQ_HANDLER
189 * if the application wants to implement its own HFXOx_IRQHandler.
190 ******************************************************************************/
HFXO_IRQ_HANDLER_FUNCTION(void)191 void HFXO_IRQ_HANDLER_FUNCTION(void)
192 {
193 sl_hfxo_manager_irq_handler();
194 }
195 #endif
196
197 /*******************************************************************************
198 * HFXO Manager HFXO interrupt handler.
199 ******************************************************************************/
sl_hfxo_manager_irq_handler(void)200 void sl_hfxo_manager_irq_handler(void)
201 {
202 uint32_t irq_flag = HFXO0->IF;
203 #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1)
204 bool disondemand = (HFXO0->CTRL & _HFXO_CTRL_DISONDEMAND_MASK) ? true : false;
205 bool forceen = (HFXO0->CTRL & _HFXO_CTRL_FORCEEN_MASK) ? true : false;
206 #endif
207
208 // RDY Interrupt Flag Handling
209 if (irq_flag & HFXO_IF_RDY) {
210 // Clear Ready flag
211 HFXO0->IF_CLR = irq_flag & HFXO_IF_RDY;
212
213 #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1)
214 if (error_flag) {
215 // Clear error flag, i.e. we successfully stated HFXO with the modified settings
216 error_flag = false;
217
218 // If it's the first time we succeed after an error, try back the normal settings
219 if (error_try_cnt <= 1) {
220 // Disable HFXO.
221 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
222 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
223
224 while ((HFXO0->STATUS & HFXO_STATUS_ENS) != 0) {
225 }
226
227 // Put back normal settings
228 HFXO0->PKDETCTRL = (HFXO0->PKDETCTRL & ~_HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK) | pkdettusstartupi_saved;
229 HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXIANA_MASK | _HFXO_XTALCTRL_CTUNEXOANA_MASK))
230 | ctunexiana_saved
231 | ctunexoana_saved;
232 HFXO0->XTALCFG = (HFXO0->XTALCFG & ~(_HFXO_XTALCFG_COREBIASSTARTUPI_MASK | _HFXO_XTALCFG_COREBIASSTARTUP_MASK))
233 | corebiasstartup_saved
234 | corebiasstartupi_saved;
235 HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK) | corebiasana_saved;
236
237 // Put back FORCEEN and DISONDEMAND state
238 if (!disondemand) {
239 HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND;
240 } else {
241 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
242 }
243 if (forceen) {
244 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN;
245 } else {
246 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
247 }
248 } else {
249 // Call notification function to tell users that sleepy crystal settings are kept
250 // This should only happen if you are in test condition or if you have a bad crystal.
251 sl_hfxo_manager_notify_consecutive_failed_startups();
252 in_error_state = true;
253 }
254 } else {
255 sli_hfxo_manager_end_startup_measurement();
256
257 sli_hfxo_manager_notify_ready_for_power_manager();
258
259 // Clear counter since we successfully started HFXO with normal settings
260 // or we are just keeping sleepy crystal settings indefinitely.
261 error_try_cnt = 0;
262 }
263 #else
264 sli_hfxo_manager_end_startup_measurement();
265
266 sli_hfxo_manager_notify_ready_for_power_manager();
267 #endif
268 }
269
270 // DNSERR Interrupt Flag Handling
271 if (irq_flag & HFXO_IF_DNSERR) {
272 // Clear error flag
273 HFXO0->IF_CLR = irq_flag & HFXO_IF_DNSERR;
274
275 #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1)
276 // We should not fail twice in a row
277 EFM_ASSERT(error_flag == false);
278
279 // Update global variables related to error.
280 error_flag = true;
281 error_try_cnt++;
282
283 // Save current settings
284 pkdettusstartupi_saved = (HFXO0->PKDETCTRL & _HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK);
285 ctunexiana_saved = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXIANA_MASK);
286 ctunexoana_saved = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_CTUNEXOANA_MASK);
287 corebiasana_saved = (HFXO0->XTALCTRL & _HFXO_XTALCTRL_COREBIASANA_MASK);
288 corebiasstartup_saved = (HFXO0->XTALCFG & _HFXO_XTALCFG_COREBIASSTARTUP_MASK);
289 corebiasstartupi_saved = (HFXO0->XTALCFG & _HFXO_XTALCFG_COREBIASSTARTUPI_MASK);
290
291 // Disable HFXO.
292 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
293 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
294
295 // Use FORCERAWCLK bit to exit error state when disabling
296 HFXO0->CTRL_SET = HFXO_MANAGER_CTRL_FORCERAWCLK;
297 while ((HFXO0->STATUS & _HFXO_STATUS_ENS_MASK) != 0U) {
298 }
299 HFXO0->CTRL_CLR = HFXO_MANAGER_CTRL_FORCERAWCLK;
300
301 // Change settings:
302 //Reduce Peak Detection Threshold for Startup Intermediate stage to 2 (V157MV)
303 HFXO0->PKDETCTRL = (HFXO0->PKDETCTRL & ~_HFXO_MANAGER_PKDETCTRL_PKDETTHSTARTUPI_MASK) | sleepy_xtal_settings_pkdettusstartupi;
304 // Reduce CTUNE values for steady stage
305 if (((ctunexiana_saved >> _HFXO_XTALCTRL_CTUNEXIANA_SHIFT) > 100)
306 || ((ctunexoana_saved >> _HFXO_XTALCTRL_CTUNEXOANA_SHIFT) > 100)) {
307 HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~(_HFXO_XTALCTRL_CTUNEXIANA_MASK | _HFXO_XTALCTRL_CTUNEXOANA_MASK))
308 | (sleepy_xtal_settings_ctuneana << _HFXO_XTALCTRL_CTUNEXIANA_SHIFT)
309 | (sleepy_xtal_settings_ctuneana << _HFXO_XTALCTRL_CTUNEXOANA_SHIFT);
310 }
311 // Increase core bias current at all stages
312 HFXO0->XTALCFG = (HFXO0->XTALCFG & ~(_HFXO_XTALCFG_COREBIASSTARTUPI_MASK | _HFXO_XTALCFG_COREBIASSTARTUP_MASK))
313 | ((sleepy_xtal_settings_corebias >> 2) << _HFXO_XTALCFG_COREBIASSTARTUPI_SHIFT)
314 | ((sleepy_xtal_settings_corebias >> 2) << _HFXO_XTALCFG_COREBIASSTARTUP_SHIFT);
315 HFXO0->XTALCTRL = (HFXO0->XTALCTRL & ~_HFXO_XTALCTRL_COREBIASANA_MASK)
316 | (sleepy_xtal_settings_corebias << _HFXO_XTALCTRL_COREBIASANA_SHIFT);
317
318 // Put back FORCEEN and DISONDEMAND state
319 if (!disondemand) {
320 HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND;
321 } else {
322 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
323 }
324 if (forceen) {
325 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN;
326 } else {
327 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
328 }
329 #endif
330 }
331
332 if (irq_flag & HFXO_IF_COREBIASOPTERR) {
333 // Clear Core Bias Optimization error flag
334 HFXO0->IF_CLR = irq_flag & HFXO_IF_COREBIASOPTERR;
335
336 #if (SL_HFXO_MANAGER_SLEEPY_CRYSTAL_SUPPORT == 1)
337 // In case the Core Bias Optimization fails during error handling,
338 // we disable it
339 if (in_error_state == true) {
340 // Disable HFXO.
341 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
342 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
343
344 while ((HFXO0->STATUS & HFXO_STATUS_ENS) != 0) {
345 }
346
347 // Skip Core Bias Optimization in case of error
348 HFXO0->XTALCTRL_SET = HFXO_XTALCTRL_SKIPCOREBIASOPT;
349
350 // Put back FORCEEN and DISONDEMAND state
351 if (!disondemand) {
352 HFXO0->CTRL_CLR = HFXO_CTRL_DISONDEMAND;
353 } else {
354 HFXO0->CTRL_SET = HFXO_CTRL_DISONDEMAND;
355 }
356 if (forceen) {
357 HFXO0->CTRL_SET = HFXO_CTRL_FORCEEN;
358 } else {
359 HFXO0->CTRL_CLR = HFXO_CTRL_FORCEEN;
360 }
361 }
362 #endif
363 }
364 }
365 #endif // _SILICON_LABS_32B_SERIES_2
366
