1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG22 EUSART register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG22_EUSART_H 31 #define EFR32BG22_EUSART_H 32 #define EUSART_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG22_EUSART EUSART 40 * @{ 41 * @brief EFR32BG22 EUSART Register Declaration. 42 *****************************************************************************/ 43 44 /** EUSART Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t EN; /**< Enable Register */ 48 __IOM uint32_t CFG0; /**< Configuration 0 Register */ 49 __IOM uint32_t CFG1; /**< Configuration 1 Register */ 50 __IOM uint32_t FRAMECFG; /**< Frame Format Register */ 51 __IOM uint32_t IRHFCFG; /**< HF IrDA Mod Config Register */ 52 __IOM uint32_t IRLFCFG; /**< LF IrDA Pulse Config Register */ 53 __IOM uint32_t TIMINGCFG; /**< Timing Register */ 54 __IOM uint32_t STARTFRAMECFG; /**< Start Frame Register */ 55 __IOM uint32_t SIGFRAMECFG; /**< Signal Frame Register */ 56 __IOM uint32_t CLKDIV; /**< Clock Divider Register */ 57 __IOM uint32_t TRIGCTRL; /**< Trigger Control Register */ 58 __IOM uint32_t CMD; /**< Command Register */ 59 __IM uint32_t RXDATA; /**< RX Data Register */ 60 __IM uint32_t RXDATAP; /**< RX Data Peek Register */ 61 __IOM uint32_t TXDATA; /**< TX Data Register */ 62 __IM uint32_t STATUS; /**< Status Register */ 63 __IOM uint32_t IF; /**< Interrupt Flag Register */ 64 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 65 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 66 uint32_t RESERVED0[1004U]; /**< Reserved for future use */ 67 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 68 __IOM uint32_t EN_SET; /**< Enable Register */ 69 __IOM uint32_t CFG0_SET; /**< Configuration 0 Register */ 70 __IOM uint32_t CFG1_SET; /**< Configuration 1 Register */ 71 __IOM uint32_t FRAMECFG_SET; /**< Frame Format Register */ 72 __IOM uint32_t IRHFCFG_SET; /**< HF IrDA Mod Config Register */ 73 __IOM uint32_t IRLFCFG_SET; /**< LF IrDA Pulse Config Register */ 74 __IOM uint32_t TIMINGCFG_SET; /**< Timing Register */ 75 __IOM uint32_t STARTFRAMECFG_SET; /**< Start Frame Register */ 76 __IOM uint32_t SIGFRAMECFG_SET; /**< Signal Frame Register */ 77 __IOM uint32_t CLKDIV_SET; /**< Clock Divider Register */ 78 __IOM uint32_t TRIGCTRL_SET; /**< Trigger Control Register */ 79 __IOM uint32_t CMD_SET; /**< Command Register */ 80 __IM uint32_t RXDATA_SET; /**< RX Data Register */ 81 __IM uint32_t RXDATAP_SET; /**< RX Data Peek Register */ 82 __IOM uint32_t TXDATA_SET; /**< TX Data Register */ 83 __IM uint32_t STATUS_SET; /**< Status Register */ 84 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 85 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 86 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 87 uint32_t RESERVED1[1004U]; /**< Reserved for future use */ 88 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 89 __IOM uint32_t EN_CLR; /**< Enable Register */ 90 __IOM uint32_t CFG0_CLR; /**< Configuration 0 Register */ 91 __IOM uint32_t CFG1_CLR; /**< Configuration 1 Register */ 92 __IOM uint32_t FRAMECFG_CLR; /**< Frame Format Register */ 93 __IOM uint32_t IRHFCFG_CLR; /**< HF IrDA Mod Config Register */ 94 __IOM uint32_t IRLFCFG_CLR; /**< LF IrDA Pulse Config Register */ 95 __IOM uint32_t TIMINGCFG_CLR; /**< Timing Register */ 96 __IOM uint32_t STARTFRAMECFG_CLR; /**< Start Frame Register */ 97 __IOM uint32_t SIGFRAMECFG_CLR; /**< Signal Frame Register */ 98 __IOM uint32_t CLKDIV_CLR; /**< Clock Divider Register */ 99 __IOM uint32_t TRIGCTRL_CLR; /**< Trigger Control Register */ 100 __IOM uint32_t CMD_CLR; /**< Command Register */ 101 __IM uint32_t RXDATA_CLR; /**< RX Data Register */ 102 __IM uint32_t RXDATAP_CLR; /**< RX Data Peek Register */ 103 __IOM uint32_t TXDATA_CLR; /**< TX Data Register */ 104 __IM uint32_t STATUS_CLR; /**< Status Register */ 105 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 106 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 107 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 108 uint32_t RESERVED2[1004U]; /**< Reserved for future use */ 109 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 110 __IOM uint32_t EN_TGL; /**< Enable Register */ 111 __IOM uint32_t CFG0_TGL; /**< Configuration 0 Register */ 112 __IOM uint32_t CFG1_TGL; /**< Configuration 1 Register */ 113 __IOM uint32_t FRAMECFG_TGL; /**< Frame Format Register */ 114 __IOM uint32_t IRHFCFG_TGL; /**< HF IrDA Mod Config Register */ 115 __IOM uint32_t IRLFCFG_TGL; /**< LF IrDA Pulse Config Register */ 116 __IOM uint32_t TIMINGCFG_TGL; /**< Timing Register */ 117 __IOM uint32_t STARTFRAMECFG_TGL; /**< Start Frame Register */ 118 __IOM uint32_t SIGFRAMECFG_TGL; /**< Signal Frame Register */ 119 __IOM uint32_t CLKDIV_TGL; /**< Clock Divider Register */ 120 __IOM uint32_t TRIGCTRL_TGL; /**< Trigger Control Register */ 121 __IOM uint32_t CMD_TGL; /**< Command Register */ 122 __IM uint32_t RXDATA_TGL; /**< RX Data Register */ 123 __IM uint32_t RXDATAP_TGL; /**< RX Data Peek Register */ 124 __IOM uint32_t TXDATA_TGL; /**< TX Data Register */ 125 __IM uint32_t STATUS_TGL; /**< Status Register */ 126 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 127 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 128 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 129 } EUSART_TypeDef; 130 /** @} End of group EFR32BG22_EUSART */ 131 132 /**************************************************************************//** 133 * @addtogroup EFR32BG22_EUSART 134 * @{ 135 * @defgroup EFR32BG22_EUSART_BitFields EUSART Bit Fields 136 * @{ 137 *****************************************************************************/ 138 139 /* Bit fields for EUSART IPVERSION */ 140 #define _EUSART_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for EUSART_IPVERSION */ 141 #define _EUSART_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for EUSART_IPVERSION */ 142 #define _EUSART_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for EUSART_IPVERSION */ 143 #define _EUSART_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for EUSART_IPVERSION */ 144 #define _EUSART_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IPVERSION */ 145 #define EUSART_IPVERSION_IPVERSION_DEFAULT (_EUSART_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IPVERSION */ 146 147 /* Bit fields for EUSART EN */ 148 #define _EUSART_EN_RESETVALUE 0x00000000UL /**< Default value for EUSART_EN */ 149 #define _EUSART_EN_MASK 0x00000001UL /**< Mask for EUSART_EN */ 150 #define EUSART_EN_EN (0x1UL << 0) /**< Module enable */ 151 #define _EUSART_EN_EN_SHIFT 0 /**< Shift value for EUSART_EN */ 152 #define _EUSART_EN_EN_MASK 0x1UL /**< Bit mask for EUSART_EN */ 153 #define _EUSART_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_EN */ 154 #define EUSART_EN_EN_DEFAULT (_EUSART_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_EN */ 155 156 /* Bit fields for EUSART CFG0 */ 157 #define _EUSART_CFG0_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG0 */ 158 #define _EUSART_CFG0_MASK 0xC1D264FEUL /**< Mask for EUSART_CFG0 */ 159 #define EUSART_CFG0_LOOPBK (0x1UL << 1) /**< Loopback Enable */ 160 #define _EUSART_CFG0_LOOPBK_SHIFT 1 /**< Shift value for EUSART_LOOPBK */ 161 #define _EUSART_CFG0_LOOPBK_MASK 0x2UL /**< Bit mask for EUSART_LOOPBK */ 162 #define _EUSART_CFG0_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 163 #define _EUSART_CFG0_LOOPBK_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 164 #define _EUSART_CFG0_LOOPBK_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 165 #define EUSART_CFG0_LOOPBK_DEFAULT (_EUSART_CFG0_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 166 #define EUSART_CFG0_LOOPBK_DISABLE (_EUSART_CFG0_LOOPBK_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG0 */ 167 #define EUSART_CFG0_LOOPBK_ENABLE (_EUSART_CFG0_LOOPBK_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG0 */ 168 #define EUSART_CFG0_CCEN (0x1UL << 2) /**< Collision Check Enable */ 169 #define _EUSART_CFG0_CCEN_SHIFT 2 /**< Shift value for EUSART_CCEN */ 170 #define _EUSART_CFG0_CCEN_MASK 0x4UL /**< Bit mask for EUSART_CCEN */ 171 #define _EUSART_CFG0_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 172 #define _EUSART_CFG0_CCEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 173 #define _EUSART_CFG0_CCEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 174 #define EUSART_CFG0_CCEN_DEFAULT (_EUSART_CFG0_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 175 #define EUSART_CFG0_CCEN_DISABLE (_EUSART_CFG0_CCEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG0 */ 176 #define EUSART_CFG0_CCEN_ENABLE (_EUSART_CFG0_CCEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG0 */ 177 #define EUSART_CFG0_MPM (0x1UL << 3) /**< Multi-Processor Mode */ 178 #define _EUSART_CFG0_MPM_SHIFT 3 /**< Shift value for EUSART_MPM */ 179 #define _EUSART_CFG0_MPM_MASK 0x8UL /**< Bit mask for EUSART_MPM */ 180 #define _EUSART_CFG0_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 181 #define _EUSART_CFG0_MPM_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 182 #define _EUSART_CFG0_MPM_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 183 #define EUSART_CFG0_MPM_DEFAULT (_EUSART_CFG0_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 184 #define EUSART_CFG0_MPM_DISABLE (_EUSART_CFG0_MPM_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG0 */ 185 #define EUSART_CFG0_MPM_ENABLE (_EUSART_CFG0_MPM_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG0 */ 186 #define EUSART_CFG0_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */ 187 #define _EUSART_CFG0_MPAB_SHIFT 4 /**< Shift value for EUSART_MPAB */ 188 #define _EUSART_CFG0_MPAB_MASK 0x10UL /**< Bit mask for EUSART_MPAB */ 189 #define _EUSART_CFG0_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 190 #define EUSART_CFG0_MPAB_DEFAULT (_EUSART_CFG0_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 191 #define _EUSART_CFG0_OVS_SHIFT 5 /**< Shift value for EUSART_OVS */ 192 #define _EUSART_CFG0_OVS_MASK 0xE0UL /**< Bit mask for EUSART_OVS */ 193 #define _EUSART_CFG0_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 194 #define _EUSART_CFG0_OVS_X16 0x00000000UL /**< Mode X16 for EUSART_CFG0 */ 195 #define _EUSART_CFG0_OVS_X8 0x00000001UL /**< Mode X8 for EUSART_CFG0 */ 196 #define _EUSART_CFG0_OVS_X6 0x00000002UL /**< Mode X6 for EUSART_CFG0 */ 197 #define _EUSART_CFG0_OVS_X4 0x00000003UL /**< Mode X4 for EUSART_CFG0 */ 198 #define _EUSART_CFG0_OVS_DISABLE 0x00000004UL /**< Mode DISABLE for EUSART_CFG0 */ 199 #define EUSART_CFG0_OVS_DEFAULT (_EUSART_CFG0_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 200 #define EUSART_CFG0_OVS_X16 (_EUSART_CFG0_OVS_X16 << 5) /**< Shifted mode X16 for EUSART_CFG0 */ 201 #define EUSART_CFG0_OVS_X8 (_EUSART_CFG0_OVS_X8 << 5) /**< Shifted mode X8 for EUSART_CFG0 */ 202 #define EUSART_CFG0_OVS_X6 (_EUSART_CFG0_OVS_X6 << 5) /**< Shifted mode X6 for EUSART_CFG0 */ 203 #define EUSART_CFG0_OVS_X4 (_EUSART_CFG0_OVS_X4 << 5) /**< Shifted mode X4 for EUSART_CFG0 */ 204 #define EUSART_CFG0_OVS_DISABLE (_EUSART_CFG0_OVS_DISABLE << 5) /**< Shifted mode DISABLE for EUSART_CFG0 */ 205 #define EUSART_CFG0_MSBF (0x1UL << 10) /**< Most Significant Bit First */ 206 #define _EUSART_CFG0_MSBF_SHIFT 10 /**< Shift value for EUSART_MSBF */ 207 #define _EUSART_CFG0_MSBF_MASK 0x400UL /**< Bit mask for EUSART_MSBF */ 208 #define _EUSART_CFG0_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 209 #define _EUSART_CFG0_MSBF_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 210 #define _EUSART_CFG0_MSBF_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 211 #define EUSART_CFG0_MSBF_DEFAULT (_EUSART_CFG0_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 212 #define EUSART_CFG0_MSBF_DISABLE (_EUSART_CFG0_MSBF_DISABLE << 10) /**< Shifted mode DISABLE for EUSART_CFG0 */ 213 #define EUSART_CFG0_MSBF_ENABLE (_EUSART_CFG0_MSBF_ENABLE << 10) /**< Shifted mode ENABLE for EUSART_CFG0 */ 214 #define EUSART_CFG0_RXINV (0x1UL << 13) /**< Receiver Input Invert */ 215 #define _EUSART_CFG0_RXINV_SHIFT 13 /**< Shift value for EUSART_RXINV */ 216 #define _EUSART_CFG0_RXINV_MASK 0x2000UL /**< Bit mask for EUSART_RXINV */ 217 #define _EUSART_CFG0_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 218 #define _EUSART_CFG0_RXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 219 #define _EUSART_CFG0_RXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 220 #define EUSART_CFG0_RXINV_DEFAULT (_EUSART_CFG0_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 221 #define EUSART_CFG0_RXINV_DISABLE (_EUSART_CFG0_RXINV_DISABLE << 13) /**< Shifted mode DISABLE for EUSART_CFG0 */ 222 #define EUSART_CFG0_RXINV_ENABLE (_EUSART_CFG0_RXINV_ENABLE << 13) /**< Shifted mode ENABLE for EUSART_CFG0 */ 223 #define EUSART_CFG0_TXINV (0x1UL << 14) /**< Transmitter output Invert */ 224 #define _EUSART_CFG0_TXINV_SHIFT 14 /**< Shift value for EUSART_TXINV */ 225 #define _EUSART_CFG0_TXINV_MASK 0x4000UL /**< Bit mask for EUSART_TXINV */ 226 #define _EUSART_CFG0_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 227 #define _EUSART_CFG0_TXINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 228 #define _EUSART_CFG0_TXINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 229 #define EUSART_CFG0_TXINV_DEFAULT (_EUSART_CFG0_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 230 #define EUSART_CFG0_TXINV_DISABLE (_EUSART_CFG0_TXINV_DISABLE << 14) /**< Shifted mode DISABLE for EUSART_CFG0 */ 231 #define EUSART_CFG0_TXINV_ENABLE (_EUSART_CFG0_TXINV_ENABLE << 14) /**< Shifted mode ENABLE for EUSART_CFG0 */ 232 #define EUSART_CFG0_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */ 233 #define _EUSART_CFG0_AUTOTRI_SHIFT 17 /**< Shift value for EUSART_AUTOTRI */ 234 #define _EUSART_CFG0_AUTOTRI_MASK 0x20000UL /**< Bit mask for EUSART_AUTOTRI */ 235 #define _EUSART_CFG0_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 236 #define _EUSART_CFG0_AUTOTRI_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 237 #define _EUSART_CFG0_AUTOTRI_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 238 #define EUSART_CFG0_AUTOTRI_DEFAULT (_EUSART_CFG0_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 239 #define EUSART_CFG0_AUTOTRI_DISABLE (_EUSART_CFG0_AUTOTRI_DISABLE << 17) /**< Shifted mode DISABLE for EUSART_CFG0 */ 240 #define EUSART_CFG0_AUTOTRI_ENABLE (_EUSART_CFG0_AUTOTRI_ENABLE << 17) /**< Shifted mode ENABLE for EUSART_CFG0 */ 241 #define EUSART_CFG0_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */ 242 #define _EUSART_CFG0_SKIPPERRF_SHIFT 20 /**< Shift value for EUSART_SKIPPERRF */ 243 #define _EUSART_CFG0_SKIPPERRF_MASK 0x100000UL /**< Bit mask for EUSART_SKIPPERRF */ 244 #define _EUSART_CFG0_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 245 #define EUSART_CFG0_SKIPPERRF_DEFAULT (_EUSART_CFG0_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 246 #define EUSART_CFG0_ERRSDMA (0x1UL << 22) /**< Halt DMA Read On Error */ 247 #define _EUSART_CFG0_ERRSDMA_SHIFT 22 /**< Shift value for EUSART_ERRSDMA */ 248 #define _EUSART_CFG0_ERRSDMA_MASK 0x400000UL /**< Bit mask for EUSART_ERRSDMA */ 249 #define _EUSART_CFG0_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 250 #define _EUSART_CFG0_ERRSDMA_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 251 #define _EUSART_CFG0_ERRSDMA_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 252 #define EUSART_CFG0_ERRSDMA_DEFAULT (_EUSART_CFG0_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 253 #define EUSART_CFG0_ERRSDMA_DISABLE (_EUSART_CFG0_ERRSDMA_DISABLE << 22) /**< Shifted mode DISABLE for EUSART_CFG0 */ 254 #define EUSART_CFG0_ERRSDMA_ENABLE (_EUSART_CFG0_ERRSDMA_ENABLE << 22) /**< Shifted mode ENABLE for EUSART_CFG0 */ 255 #define EUSART_CFG0_ERRSRX (0x1UL << 23) /**< Disable RX On Error */ 256 #define _EUSART_CFG0_ERRSRX_SHIFT 23 /**< Shift value for EUSART_ERRSRX */ 257 #define _EUSART_CFG0_ERRSRX_MASK 0x800000UL /**< Bit mask for EUSART_ERRSRX */ 258 #define _EUSART_CFG0_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 259 #define _EUSART_CFG0_ERRSRX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 260 #define _EUSART_CFG0_ERRSRX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 261 #define EUSART_CFG0_ERRSRX_DEFAULT (_EUSART_CFG0_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 262 #define EUSART_CFG0_ERRSRX_DISABLE (_EUSART_CFG0_ERRSRX_DISABLE << 23) /**< Shifted mode DISABLE for EUSART_CFG0 */ 263 #define EUSART_CFG0_ERRSRX_ENABLE (_EUSART_CFG0_ERRSRX_ENABLE << 23) /**< Shifted mode ENABLE for EUSART_CFG0 */ 264 #define EUSART_CFG0_ERRSTX (0x1UL << 24) /**< Disable TX On Error */ 265 #define _EUSART_CFG0_ERRSTX_SHIFT 24 /**< Shift value for EUSART_ERRSTX */ 266 #define _EUSART_CFG0_ERRSTX_MASK 0x1000000UL /**< Bit mask for EUSART_ERRSTX */ 267 #define _EUSART_CFG0_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 268 #define _EUSART_CFG0_ERRSTX_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG0 */ 269 #define _EUSART_CFG0_ERRSTX_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG0 */ 270 #define EUSART_CFG0_ERRSTX_DEFAULT (_EUSART_CFG0_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 271 #define EUSART_CFG0_ERRSTX_DISABLE (_EUSART_CFG0_ERRSTX_DISABLE << 24) /**< Shifted mode DISABLE for EUSART_CFG0 */ 272 #define EUSART_CFG0_ERRSTX_ENABLE (_EUSART_CFG0_ERRSTX_ENABLE << 24) /**< Shifted mode ENABLE for EUSART_CFG0 */ 273 #define EUSART_CFG0_MVDIS (0x1UL << 30) /**< Majority Vote Disable */ 274 #define _EUSART_CFG0_MVDIS_SHIFT 30 /**< Shift value for EUSART_MVDIS */ 275 #define _EUSART_CFG0_MVDIS_MASK 0x40000000UL /**< Bit mask for EUSART_MVDIS */ 276 #define _EUSART_CFG0_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 277 #define EUSART_CFG0_MVDIS_DEFAULT (_EUSART_CFG0_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 278 #define EUSART_CFG0_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */ 279 #define _EUSART_CFG0_AUTOBAUDEN_SHIFT 31 /**< Shift value for EUSART_AUTOBAUDEN */ 280 #define _EUSART_CFG0_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for EUSART_AUTOBAUDEN */ 281 #define _EUSART_CFG0_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG0 */ 282 #define EUSART_CFG0_AUTOBAUDEN_DEFAULT (_EUSART_CFG0_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for EUSART_CFG0 */ 283 284 /* Bit fields for EUSART CFG1 */ 285 #define _EUSART_CFG1_RESETVALUE 0x00000000UL /**< Default value for EUSART_CFG1 */ 286 #define _EUSART_CFG1_MASK 0x00DB8E0FUL /**< Mask for EUSART_CFG1 */ 287 #define EUSART_CFG1_DBGHALT (0x1UL << 0) /**< Debug halt */ 288 #define _EUSART_CFG1_DBGHALT_SHIFT 0 /**< Shift value for EUSART_DBGHALT */ 289 #define _EUSART_CFG1_DBGHALT_MASK 0x1UL /**< Bit mask for EUSART_DBGHALT */ 290 #define _EUSART_CFG1_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 291 #define _EUSART_CFG1_DBGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 292 #define _EUSART_CFG1_DBGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 293 #define EUSART_CFG1_DBGHALT_DEFAULT (_EUSART_CFG1_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 294 #define EUSART_CFG1_DBGHALT_DISABLE (_EUSART_CFG1_DBGHALT_DISABLE << 0) /**< Shifted mode DISABLE for EUSART_CFG1 */ 295 #define EUSART_CFG1_DBGHALT_ENABLE (_EUSART_CFG1_DBGHALT_ENABLE << 0) /**< Shifted mode ENABLE for EUSART_CFG1 */ 296 #define EUSART_CFG1_CTSINV (0x1UL << 1) /**< Clear-to-send Invert Enable */ 297 #define _EUSART_CFG1_CTSINV_SHIFT 1 /**< Shift value for EUSART_CTSINV */ 298 #define _EUSART_CFG1_CTSINV_MASK 0x2UL /**< Bit mask for EUSART_CTSINV */ 299 #define _EUSART_CFG1_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 300 #define _EUSART_CFG1_CTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 301 #define _EUSART_CFG1_CTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 302 #define EUSART_CFG1_CTSINV_DEFAULT (_EUSART_CFG1_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 303 #define EUSART_CFG1_CTSINV_DISABLE (_EUSART_CFG1_CTSINV_DISABLE << 1) /**< Shifted mode DISABLE for EUSART_CFG1 */ 304 #define EUSART_CFG1_CTSINV_ENABLE (_EUSART_CFG1_CTSINV_ENABLE << 1) /**< Shifted mode ENABLE for EUSART_CFG1 */ 305 #define EUSART_CFG1_CTSEN (0x1UL << 2) /**< Clear-to-send Enable */ 306 #define _EUSART_CFG1_CTSEN_SHIFT 2 /**< Shift value for EUSART_CTSEN */ 307 #define _EUSART_CFG1_CTSEN_MASK 0x4UL /**< Bit mask for EUSART_CTSEN */ 308 #define _EUSART_CFG1_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 309 #define _EUSART_CFG1_CTSEN_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 310 #define _EUSART_CFG1_CTSEN_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 311 #define EUSART_CFG1_CTSEN_DEFAULT (_EUSART_CFG1_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 312 #define EUSART_CFG1_CTSEN_DISABLE (_EUSART_CFG1_CTSEN_DISABLE << 2) /**< Shifted mode DISABLE for EUSART_CFG1 */ 313 #define EUSART_CFG1_CTSEN_ENABLE (_EUSART_CFG1_CTSEN_ENABLE << 2) /**< Shifted mode ENABLE for EUSART_CFG1 */ 314 #define EUSART_CFG1_RTSINV (0x1UL << 3) /**< Request-to-send Invert Enable */ 315 #define _EUSART_CFG1_RTSINV_SHIFT 3 /**< Shift value for EUSART_RTSINV */ 316 #define _EUSART_CFG1_RTSINV_MASK 0x8UL /**< Bit mask for EUSART_RTSINV */ 317 #define _EUSART_CFG1_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 318 #define _EUSART_CFG1_RTSINV_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_CFG1 */ 319 #define _EUSART_CFG1_RTSINV_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_CFG1 */ 320 #define EUSART_CFG1_RTSINV_DEFAULT (_EUSART_CFG1_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 321 #define EUSART_CFG1_RTSINV_DISABLE (_EUSART_CFG1_RTSINV_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_CFG1 */ 322 #define EUSART_CFG1_RTSINV_ENABLE (_EUSART_CFG1_RTSINV_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_CFG1 */ 323 #define EUSART_CFG1_TXDMAWU (0x1UL << 9) /**< Transmitter DMA Wakeup */ 324 #define _EUSART_CFG1_TXDMAWU_SHIFT 9 /**< Shift value for EUSART_TXDMAWU */ 325 #define _EUSART_CFG1_TXDMAWU_MASK 0x200UL /**< Bit mask for EUSART_TXDMAWU */ 326 #define _EUSART_CFG1_TXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 327 #define EUSART_CFG1_TXDMAWU_DEFAULT (_EUSART_CFG1_TXDMAWU_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 328 #define EUSART_CFG1_RXDMAWU (0x1UL << 10) /**< Receiver DMA Wakeup */ 329 #define _EUSART_CFG1_RXDMAWU_SHIFT 10 /**< Shift value for EUSART_RXDMAWU */ 330 #define _EUSART_CFG1_RXDMAWU_MASK 0x400UL /**< Bit mask for EUSART_RXDMAWU */ 331 #define _EUSART_CFG1_RXDMAWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 332 #define EUSART_CFG1_RXDMAWU_DEFAULT (_EUSART_CFG1_RXDMAWU_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 333 #define EUSART_CFG1_SFUBRX (0x1UL << 11) /**< Start Frame Unblock Receiver */ 334 #define _EUSART_CFG1_SFUBRX_SHIFT 11 /**< Shift value for EUSART_SFUBRX */ 335 #define _EUSART_CFG1_SFUBRX_MASK 0x800UL /**< Bit mask for EUSART_SFUBRX */ 336 #define _EUSART_CFG1_SFUBRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 337 #define EUSART_CFG1_SFUBRX_DEFAULT (_EUSART_CFG1_SFUBRX_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 338 #define EUSART_CFG1_RXPRSEN (0x1UL << 15) /**< PRS RX Enable */ 339 #define _EUSART_CFG1_RXPRSEN_SHIFT 15 /**< Shift value for EUSART_RXPRSEN */ 340 #define _EUSART_CFG1_RXPRSEN_MASK 0x8000UL /**< Bit mask for EUSART_RXPRSEN */ 341 #define _EUSART_CFG1_RXPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 342 #define EUSART_CFG1_RXPRSEN_DEFAULT (_EUSART_CFG1_RXPRSEN_DEFAULT << 15) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 343 #define _EUSART_CFG1_TXFIW_SHIFT 16 /**< Shift value for EUSART_TXFIW */ 344 #define _EUSART_CFG1_TXFIW_MASK 0x30000UL /**< Bit mask for EUSART_TXFIW */ 345 #define _EUSART_CFG1_TXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 346 #define _EUSART_CFG1_TXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ 347 #define _EUSART_CFG1_TXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 348 #define _EUSART_CFG1_TXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 349 #define _EUSART_CFG1_TXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 350 #define EUSART_CFG1_TXFIW_DEFAULT (_EUSART_CFG1_TXFIW_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 351 #define EUSART_CFG1_TXFIW_ONEFRAME (_EUSART_CFG1_TXFIW_ONEFRAME << 16) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 352 #define EUSART_CFG1_TXFIW_TWOFRAMES (_EUSART_CFG1_TXFIW_TWOFRAMES << 16) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 353 #define EUSART_CFG1_TXFIW_THREEFRAMES (_EUSART_CFG1_TXFIW_THREEFRAMES << 16) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 354 #define EUSART_CFG1_TXFIW_FOURFRAMES (_EUSART_CFG1_TXFIW_FOURFRAMES << 16) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 355 #define _EUSART_CFG1_RXFIW_SHIFT 19 /**< Shift value for EUSART_RXFIW */ 356 #define _EUSART_CFG1_RXFIW_MASK 0x180000UL /**< Bit mask for EUSART_RXFIW */ 357 #define _EUSART_CFG1_RXFIW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 358 #define _EUSART_CFG1_RXFIW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ 359 #define _EUSART_CFG1_RXFIW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 360 #define _EUSART_CFG1_RXFIW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 361 #define _EUSART_CFG1_RXFIW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 362 #define EUSART_CFG1_RXFIW_DEFAULT (_EUSART_CFG1_RXFIW_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 363 #define EUSART_CFG1_RXFIW_ONEFRAME (_EUSART_CFG1_RXFIW_ONEFRAME << 19) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 364 #define EUSART_CFG1_RXFIW_TWOFRAMES (_EUSART_CFG1_RXFIW_TWOFRAMES << 19) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 365 #define EUSART_CFG1_RXFIW_THREEFRAMES (_EUSART_CFG1_RXFIW_THREEFRAMES << 19) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 366 #define EUSART_CFG1_RXFIW_FOURFRAMES (_EUSART_CFG1_RXFIW_FOURFRAMES << 19) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 367 #define _EUSART_CFG1_RTSRXFW_SHIFT 22 /**< Shift value for EUSART_RTSRXFW */ 368 #define _EUSART_CFG1_RTSRXFW_MASK 0xC00000UL /**< Bit mask for EUSART_RTSRXFW */ 369 #define _EUSART_CFG1_RTSRXFW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CFG1 */ 370 #define _EUSART_CFG1_RTSRXFW_ONEFRAME 0x00000000UL /**< Mode ONEFRAME for EUSART_CFG1 */ 371 #define _EUSART_CFG1_RTSRXFW_TWOFRAMES 0x00000001UL /**< Mode TWOFRAMES for EUSART_CFG1 */ 372 #define _EUSART_CFG1_RTSRXFW_THREEFRAMES 0x00000002UL /**< Mode THREEFRAMES for EUSART_CFG1 */ 373 #define _EUSART_CFG1_RTSRXFW_FOURFRAMES 0x00000003UL /**< Mode FOURFRAMES for EUSART_CFG1 */ 374 #define EUSART_CFG1_RTSRXFW_DEFAULT (_EUSART_CFG1_RTSRXFW_DEFAULT << 22) /**< Shifted mode DEFAULT for EUSART_CFG1 */ 375 #define EUSART_CFG1_RTSRXFW_ONEFRAME (_EUSART_CFG1_RTSRXFW_ONEFRAME << 22) /**< Shifted mode ONEFRAME for EUSART_CFG1 */ 376 #define EUSART_CFG1_RTSRXFW_TWOFRAMES (_EUSART_CFG1_RTSRXFW_TWOFRAMES << 22) /**< Shifted mode TWOFRAMES for EUSART_CFG1 */ 377 #define EUSART_CFG1_RTSRXFW_THREEFRAMES (_EUSART_CFG1_RTSRXFW_THREEFRAMES << 22) /**< Shifted mode THREEFRAMES for EUSART_CFG1 */ 378 #define EUSART_CFG1_RTSRXFW_FOURFRAMES (_EUSART_CFG1_RTSRXFW_FOURFRAMES << 22) /**< Shifted mode FOURFRAMES for EUSART_CFG1 */ 379 380 /* Bit fields for EUSART FRAMECFG */ 381 #define _EUSART_FRAMECFG_RESETVALUE 0x00001002UL /**< Default value for EUSART_FRAMECFG */ 382 #define _EUSART_FRAMECFG_MASK 0x00003303UL /**< Mask for EUSART_FRAMECFG */ 383 #define _EUSART_FRAMECFG_DATABITS_SHIFT 0 /**< Shift value for EUSART_DATABITS */ 384 #define _EUSART_FRAMECFG_DATABITS_MASK 0x3UL /**< Bit mask for EUSART_DATABITS */ 385 #define _EUSART_FRAMECFG_DATABITS_DEFAULT 0x00000002UL /**< Mode DEFAULT for EUSART_FRAMECFG */ 386 #define _EUSART_FRAMECFG_DATABITS_SEVEN 0x00000001UL /**< Mode SEVEN for EUSART_FRAMECFG */ 387 #define _EUSART_FRAMECFG_DATABITS_EIGHT 0x00000002UL /**< Mode EIGHT for EUSART_FRAMECFG */ 388 #define _EUSART_FRAMECFG_DATABITS_NINE 0x00000003UL /**< Mode NINE for EUSART_FRAMECFG */ 389 #define EUSART_FRAMECFG_DATABITS_DEFAULT (_EUSART_FRAMECFG_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ 390 #define EUSART_FRAMECFG_DATABITS_SEVEN (_EUSART_FRAMECFG_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for EUSART_FRAMECFG */ 391 #define EUSART_FRAMECFG_DATABITS_EIGHT (_EUSART_FRAMECFG_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for EUSART_FRAMECFG */ 392 #define EUSART_FRAMECFG_DATABITS_NINE (_EUSART_FRAMECFG_DATABITS_NINE << 0) /**< Shifted mode NINE for EUSART_FRAMECFG */ 393 #define _EUSART_FRAMECFG_PARITY_SHIFT 8 /**< Shift value for EUSART_PARITY */ 394 #define _EUSART_FRAMECFG_PARITY_MASK 0x300UL /**< Bit mask for EUSART_PARITY */ 395 #define _EUSART_FRAMECFG_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_FRAMECFG */ 396 #define _EUSART_FRAMECFG_PARITY_NONE 0x00000000UL /**< Mode NONE for EUSART_FRAMECFG */ 397 #define _EUSART_FRAMECFG_PARITY_EVEN 0x00000002UL /**< Mode EVEN for EUSART_FRAMECFG */ 398 #define _EUSART_FRAMECFG_PARITY_ODD 0x00000003UL /**< Mode ODD for EUSART_FRAMECFG */ 399 #define EUSART_FRAMECFG_PARITY_DEFAULT (_EUSART_FRAMECFG_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ 400 #define EUSART_FRAMECFG_PARITY_NONE (_EUSART_FRAMECFG_PARITY_NONE << 8) /**< Shifted mode NONE for EUSART_FRAMECFG */ 401 #define EUSART_FRAMECFG_PARITY_EVEN (_EUSART_FRAMECFG_PARITY_EVEN << 8) /**< Shifted mode EVEN for EUSART_FRAMECFG */ 402 #define EUSART_FRAMECFG_PARITY_ODD (_EUSART_FRAMECFG_PARITY_ODD << 8) /**< Shifted mode ODD for EUSART_FRAMECFG */ 403 #define _EUSART_FRAMECFG_STOPBITS_SHIFT 12 /**< Shift value for EUSART_STOPBITS */ 404 #define _EUSART_FRAMECFG_STOPBITS_MASK 0x3000UL /**< Bit mask for EUSART_STOPBITS */ 405 #define _EUSART_FRAMECFG_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_FRAMECFG */ 406 #define _EUSART_FRAMECFG_STOPBITS_HALF 0x00000000UL /**< Mode HALF for EUSART_FRAMECFG */ 407 #define _EUSART_FRAMECFG_STOPBITS_ONE 0x00000001UL /**< Mode ONE for EUSART_FRAMECFG */ 408 #define _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for EUSART_FRAMECFG */ 409 #define _EUSART_FRAMECFG_STOPBITS_TWO 0x00000003UL /**< Mode TWO for EUSART_FRAMECFG */ 410 #define EUSART_FRAMECFG_STOPBITS_DEFAULT (_EUSART_FRAMECFG_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_FRAMECFG */ 411 #define EUSART_FRAMECFG_STOPBITS_HALF (_EUSART_FRAMECFG_STOPBITS_HALF << 12) /**< Shifted mode HALF for EUSART_FRAMECFG */ 412 #define EUSART_FRAMECFG_STOPBITS_ONE (_EUSART_FRAMECFG_STOPBITS_ONE << 12) /**< Shifted mode ONE for EUSART_FRAMECFG */ 413 #define EUSART_FRAMECFG_STOPBITS_ONEANDAHALF (_EUSART_FRAMECFG_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for EUSART_FRAMECFG*/ 414 #define EUSART_FRAMECFG_STOPBITS_TWO (_EUSART_FRAMECFG_STOPBITS_TWO << 12) /**< Shifted mode TWO for EUSART_FRAMECFG */ 415 416 /* Bit fields for EUSART IRHFCFG */ 417 #define _EUSART_IRHFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRHFCFG */ 418 #define _EUSART_IRHFCFG_MASK 0x0000000FUL /**< Mask for EUSART_IRHFCFG */ 419 #define EUSART_IRHFCFG_IRHFEN (0x1UL << 0) /**< Enable IrDA Module */ 420 #define _EUSART_IRHFCFG_IRHFEN_SHIFT 0 /**< Shift value for EUSART_IRHFEN */ 421 #define _EUSART_IRHFCFG_IRHFEN_MASK 0x1UL /**< Bit mask for EUSART_IRHFEN */ 422 #define _EUSART_IRHFCFG_IRHFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ 423 #define EUSART_IRHFCFG_IRHFEN_DEFAULT (_EUSART_IRHFCFG_IRHFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ 424 #define _EUSART_IRHFCFG_IRHFPW_SHIFT 1 /**< Shift value for EUSART_IRHFPW */ 425 #define _EUSART_IRHFCFG_IRHFPW_MASK 0x6UL /**< Bit mask for EUSART_IRHFPW */ 426 #define _EUSART_IRHFCFG_IRHFPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ 427 #define _EUSART_IRHFCFG_IRHFPW_ONE 0x00000000UL /**< Mode ONE for EUSART_IRHFCFG */ 428 #define _EUSART_IRHFCFG_IRHFPW_TWO 0x00000001UL /**< Mode TWO for EUSART_IRHFCFG */ 429 #define _EUSART_IRHFCFG_IRHFPW_THREE 0x00000002UL /**< Mode THREE for EUSART_IRHFCFG */ 430 #define _EUSART_IRHFCFG_IRHFPW_FOUR 0x00000003UL /**< Mode FOUR for EUSART_IRHFCFG */ 431 #define EUSART_IRHFCFG_IRHFPW_DEFAULT (_EUSART_IRHFCFG_IRHFPW_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ 432 #define EUSART_IRHFCFG_IRHFPW_ONE (_EUSART_IRHFCFG_IRHFPW_ONE << 1) /**< Shifted mode ONE for EUSART_IRHFCFG */ 433 #define EUSART_IRHFCFG_IRHFPW_TWO (_EUSART_IRHFCFG_IRHFPW_TWO << 1) /**< Shifted mode TWO for EUSART_IRHFCFG */ 434 #define EUSART_IRHFCFG_IRHFPW_THREE (_EUSART_IRHFCFG_IRHFPW_THREE << 1) /**< Shifted mode THREE for EUSART_IRHFCFG */ 435 #define EUSART_IRHFCFG_IRHFPW_FOUR (_EUSART_IRHFCFG_IRHFPW_FOUR << 1) /**< Shifted mode FOUR for EUSART_IRHFCFG */ 436 #define EUSART_IRHFCFG_IRHFFILT (0x1UL << 3) /**< IrDA RX Filter */ 437 #define _EUSART_IRHFCFG_IRHFFILT_SHIFT 3 /**< Shift value for EUSART_IRHFFILT */ 438 #define _EUSART_IRHFCFG_IRHFFILT_MASK 0x8UL /**< Bit mask for EUSART_IRHFFILT */ 439 #define _EUSART_IRHFCFG_IRHFFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRHFCFG */ 440 #define _EUSART_IRHFCFG_IRHFFILT_DISABLE 0x00000000UL /**< Mode DISABLE for EUSART_IRHFCFG */ 441 #define _EUSART_IRHFCFG_IRHFFILT_ENABLE 0x00000001UL /**< Mode ENABLE for EUSART_IRHFCFG */ 442 #define EUSART_IRHFCFG_IRHFFILT_DEFAULT (_EUSART_IRHFCFG_IRHFFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IRHFCFG */ 443 #define EUSART_IRHFCFG_IRHFFILT_DISABLE (_EUSART_IRHFCFG_IRHFFILT_DISABLE << 3) /**< Shifted mode DISABLE for EUSART_IRHFCFG */ 444 #define EUSART_IRHFCFG_IRHFFILT_ENABLE (_EUSART_IRHFCFG_IRHFFILT_ENABLE << 3) /**< Shifted mode ENABLE for EUSART_IRHFCFG */ 445 446 /* Bit fields for EUSART IRLFCFG */ 447 #define _EUSART_IRLFCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_IRLFCFG */ 448 #define _EUSART_IRLFCFG_MASK 0x00000001UL /**< Mask for EUSART_IRLFCFG */ 449 #define EUSART_IRLFCFG_IRLFEN (0x1UL << 0) /**< Pulse Generator/Extender Enable */ 450 #define _EUSART_IRLFCFG_IRLFEN_SHIFT 0 /**< Shift value for EUSART_IRLFEN */ 451 #define _EUSART_IRLFCFG_IRLFEN_MASK 0x1UL /**< Bit mask for EUSART_IRLFEN */ 452 #define _EUSART_IRLFCFG_IRLFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IRLFCFG */ 453 #define EUSART_IRLFCFG_IRLFEN_DEFAULT (_EUSART_IRLFCFG_IRLFEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IRLFCFG */ 454 455 /* Bit fields for EUSART TIMINGCFG */ 456 #define _EUSART_TIMINGCFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_TIMINGCFG */ 457 #define _EUSART_TIMINGCFG_MASK 0x00000003UL /**< Mask for EUSART_TIMINGCFG */ 458 #define _EUSART_TIMINGCFG_TXDELAY_SHIFT 0 /**< Shift value for EUSART_TXDELAY */ 459 #define _EUSART_TIMINGCFG_TXDELAY_MASK 0x3UL /**< Bit mask for EUSART_TXDELAY */ 460 #define _EUSART_TIMINGCFG_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TIMINGCFG */ 461 #define _EUSART_TIMINGCFG_TXDELAY_NONE 0x00000000UL /**< Mode NONE for EUSART_TIMINGCFG */ 462 #define _EUSART_TIMINGCFG_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for EUSART_TIMINGCFG */ 463 #define _EUSART_TIMINGCFG_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for EUSART_TIMINGCFG */ 464 #define _EUSART_TIMINGCFG_TXDELAY_TRIPPLE 0x00000003UL /**< Mode TRIPPLE for EUSART_TIMINGCFG */ 465 #define EUSART_TIMINGCFG_TXDELAY_DEFAULT (_EUSART_TIMINGCFG_TXDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TIMINGCFG */ 466 #define EUSART_TIMINGCFG_TXDELAY_NONE (_EUSART_TIMINGCFG_TXDELAY_NONE << 0) /**< Shifted mode NONE for EUSART_TIMINGCFG */ 467 #define EUSART_TIMINGCFG_TXDELAY_SINGLE (_EUSART_TIMINGCFG_TXDELAY_SINGLE << 0) /**< Shifted mode SINGLE for EUSART_TIMINGCFG */ 468 #define EUSART_TIMINGCFG_TXDELAY_DOUBLE (_EUSART_TIMINGCFG_TXDELAY_DOUBLE << 0) /**< Shifted mode DOUBLE for EUSART_TIMINGCFG */ 469 #define EUSART_TIMINGCFG_TXDELAY_TRIPPLE (_EUSART_TIMINGCFG_TXDELAY_TRIPPLE << 0) /**< Shifted mode TRIPPLE for EUSART_TIMINGCFG */ 470 471 /* Bit fields for EUSART STARTFRAMECFG */ 472 #define _EUSART_STARTFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_STARTFRAMECFG */ 473 #define _EUSART_STARTFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_STARTFRAMECFG */ 474 #define _EUSART_STARTFRAMECFG_STARTFRAME_SHIFT 0 /**< Shift value for EUSART_STARTFRAME */ 475 #define _EUSART_STARTFRAMECFG_STARTFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_STARTFRAME */ 476 #define _EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STARTFRAMECFG */ 477 #define EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT (_EUSART_STARTFRAMECFG_STARTFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STARTFRAMECFG*/ 478 479 /* Bit fields for EUSART SIGFRAMECFG */ 480 #define _EUSART_SIGFRAMECFG_RESETVALUE 0x00000000UL /**< Default value for EUSART_SIGFRAMECFG */ 481 #define _EUSART_SIGFRAMECFG_MASK 0x000001FFUL /**< Mask for EUSART_SIGFRAMECFG */ 482 #define _EUSART_SIGFRAMECFG_SIGFRAME_SHIFT 0 /**< Shift value for EUSART_SIGFRAME */ 483 #define _EUSART_SIGFRAMECFG_SIGFRAME_MASK 0x1FFUL /**< Bit mask for EUSART_SIGFRAME */ 484 #define _EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SIGFRAMECFG */ 485 #define EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT (_EUSART_SIGFRAMECFG_SIGFRAME_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SIGFRAMECFG */ 486 487 /* Bit fields for EUSART CLKDIV */ 488 #define _EUSART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for EUSART_CLKDIV */ 489 #define _EUSART_CLKDIV_MASK 0x007FFFF8UL /**< Mask for EUSART_CLKDIV */ 490 #define _EUSART_CLKDIV_DIV_SHIFT 3 /**< Shift value for EUSART_DIV */ 491 #define _EUSART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for EUSART_DIV */ 492 #define _EUSART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CLKDIV */ 493 #define EUSART_CLKDIV_DIV_DEFAULT (_EUSART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CLKDIV */ 494 495 /* Bit fields for EUSART TRIGCTRL */ 496 #define _EUSART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for EUSART_TRIGCTRL */ 497 #define _EUSART_TRIGCTRL_MASK 0x00000003UL /**< Mask for EUSART_TRIGCTRL */ 498 #define EUSART_TRIGCTRL_RXTEN (0x1UL << 0) /**< Receive Trigger Enable */ 499 #define _EUSART_TRIGCTRL_RXTEN_SHIFT 0 /**< Shift value for EUSART_RXTEN */ 500 #define _EUSART_TRIGCTRL_RXTEN_MASK 0x1UL /**< Bit mask for EUSART_RXTEN */ 501 #define _EUSART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ 502 #define EUSART_TRIGCTRL_RXTEN_DEFAULT (_EUSART_TRIGCTRL_RXTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ 503 #define EUSART_TRIGCTRL_TXTEN (0x1UL << 1) /**< Transmit Trigger Enable */ 504 #define _EUSART_TRIGCTRL_TXTEN_SHIFT 1 /**< Shift value for EUSART_TXTEN */ 505 #define _EUSART_TRIGCTRL_TXTEN_MASK 0x2UL /**< Bit mask for EUSART_TXTEN */ 506 #define _EUSART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TRIGCTRL */ 507 #define EUSART_TRIGCTRL_TXTEN_DEFAULT (_EUSART_TRIGCTRL_TXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_TRIGCTRL */ 508 509 /* Bit fields for EUSART CMD */ 510 #define _EUSART_CMD_RESETVALUE 0x00000000UL /**< Default value for EUSART_CMD */ 511 #define _EUSART_CMD_MASK 0x000001FFUL /**< Mask for EUSART_CMD */ 512 #define EUSART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */ 513 #define _EUSART_CMD_RXEN_SHIFT 0 /**< Shift value for EUSART_RXEN */ 514 #define _EUSART_CMD_RXEN_MASK 0x1UL /**< Bit mask for EUSART_RXEN */ 515 #define _EUSART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 516 #define EUSART_CMD_RXEN_DEFAULT (_EUSART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_CMD */ 517 #define EUSART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */ 518 #define _EUSART_CMD_RXDIS_SHIFT 1 /**< Shift value for EUSART_RXDIS */ 519 #define _EUSART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for EUSART_RXDIS */ 520 #define _EUSART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 521 #define EUSART_CMD_RXDIS_DEFAULT (_EUSART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_CMD */ 522 #define EUSART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */ 523 #define _EUSART_CMD_TXEN_SHIFT 2 /**< Shift value for EUSART_TXEN */ 524 #define _EUSART_CMD_TXEN_MASK 0x4UL /**< Bit mask for EUSART_TXEN */ 525 #define _EUSART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 526 #define EUSART_CMD_TXEN_DEFAULT (_EUSART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_CMD */ 527 #define EUSART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */ 528 #define _EUSART_CMD_TXDIS_SHIFT 3 /**< Shift value for EUSART_TXDIS */ 529 #define _EUSART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for EUSART_TXDIS */ 530 #define _EUSART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 531 #define EUSART_CMD_TXDIS_DEFAULT (_EUSART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_CMD */ 532 #define EUSART_CMD_RXBLOCKEN (0x1UL << 4) /**< Receiver Block Enable */ 533 #define _EUSART_CMD_RXBLOCKEN_SHIFT 4 /**< Shift value for EUSART_RXBLOCKEN */ 534 #define _EUSART_CMD_RXBLOCKEN_MASK 0x10UL /**< Bit mask for EUSART_RXBLOCKEN */ 535 #define _EUSART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 536 #define EUSART_CMD_RXBLOCKEN_DEFAULT (_EUSART_CMD_RXBLOCKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_CMD */ 537 #define EUSART_CMD_RXBLOCKDIS (0x1UL << 5) /**< Receiver Block Disable */ 538 #define _EUSART_CMD_RXBLOCKDIS_SHIFT 5 /**< Shift value for EUSART_RXBLOCKDIS */ 539 #define _EUSART_CMD_RXBLOCKDIS_MASK 0x20UL /**< Bit mask for EUSART_RXBLOCKDIS */ 540 #define _EUSART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 541 #define EUSART_CMD_RXBLOCKDIS_DEFAULT (_EUSART_CMD_RXBLOCKDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_CMD */ 542 #define EUSART_CMD_TXTRIEN (0x1UL << 6) /**< Transmitter Tristate Enable */ 543 #define _EUSART_CMD_TXTRIEN_SHIFT 6 /**< Shift value for EUSART_TXTRIEN */ 544 #define _EUSART_CMD_TXTRIEN_MASK 0x40UL /**< Bit mask for EUSART_TXTRIEN */ 545 #define _EUSART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 546 #define EUSART_CMD_TXTRIEN_DEFAULT (_EUSART_CMD_TXTRIEN_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_CMD */ 547 #define EUSART_CMD_TXTRIDIS (0x1UL << 7) /**< Transmitter Tristate Disable */ 548 #define _EUSART_CMD_TXTRIDIS_SHIFT 7 /**< Shift value for EUSART_TXTRIDIS */ 549 #define _EUSART_CMD_TXTRIDIS_MASK 0x80UL /**< Bit mask for EUSART_TXTRIDIS */ 550 #define _EUSART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 551 #define EUSART_CMD_TXTRIDIS_DEFAULT (_EUSART_CMD_TXTRIDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_CMD */ 552 #define EUSART_CMD_CLEARTX (0x1UL << 8) /**< Clear TX FIFO */ 553 #define _EUSART_CMD_CLEARTX_SHIFT 8 /**< Shift value for EUSART_CLEARTX */ 554 #define _EUSART_CMD_CLEARTX_MASK 0x100UL /**< Bit mask for EUSART_CLEARTX */ 555 #define _EUSART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_CMD */ 556 #define EUSART_CMD_CLEARTX_DEFAULT (_EUSART_CMD_CLEARTX_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_CMD */ 557 558 /* Bit fields for EUSART RXDATA */ 559 #define _EUSART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATA */ 560 #define _EUSART_RXDATA_MASK 0x000007FFUL /**< Mask for EUSART_RXDATA */ 561 #define _EUSART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for EUSART_RXDATA */ 562 #define _EUSART_RXDATA_RXDATA_MASK 0x1FFUL /**< Bit mask for EUSART_RXDATA */ 563 #define _EUSART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ 564 #define EUSART_RXDATA_RXDATA_DEFAULT (_EUSART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATA */ 565 #define EUSART_RXDATA_PERR (0x1UL << 9) /**< Parity Error */ 566 #define _EUSART_RXDATA_PERR_SHIFT 9 /**< Shift value for EUSART_PERR */ 567 #define _EUSART_RXDATA_PERR_MASK 0x200UL /**< Bit mask for EUSART_PERR */ 568 #define _EUSART_RXDATA_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ 569 #define EUSART_RXDATA_PERR_DEFAULT (_EUSART_RXDATA_PERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_RXDATA */ 570 #define EUSART_RXDATA_FERR (0x1UL << 10) /**< Framing Error */ 571 #define _EUSART_RXDATA_FERR_SHIFT 10 /**< Shift value for EUSART_FERR */ 572 #define _EUSART_RXDATA_FERR_MASK 0x400UL /**< Bit mask for EUSART_FERR */ 573 #define _EUSART_RXDATA_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATA */ 574 #define EUSART_RXDATA_FERR_DEFAULT (_EUSART_RXDATA_FERR_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_RXDATA */ 575 576 /* Bit fields for EUSART RXDATAP */ 577 #define _EUSART_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for EUSART_RXDATAP */ 578 #define _EUSART_RXDATAP_MASK 0x000007FFUL /**< Mask for EUSART_RXDATAP */ 579 #define _EUSART_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for EUSART_RXDATAP */ 580 #define _EUSART_RXDATAP_RXDATAP_MASK 0x1FFUL /**< Bit mask for EUSART_RXDATAP */ 581 #define _EUSART_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ 582 #define EUSART_RXDATAP_RXDATAP_DEFAULT (_EUSART_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ 583 #define EUSART_RXDATAP_PERRP (0x1UL << 9) /**< Parity Error Peek */ 584 #define _EUSART_RXDATAP_PERRP_SHIFT 9 /**< Shift value for EUSART_PERRP */ 585 #define _EUSART_RXDATAP_PERRP_MASK 0x200UL /**< Bit mask for EUSART_PERRP */ 586 #define _EUSART_RXDATAP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ 587 #define EUSART_RXDATAP_PERRP_DEFAULT (_EUSART_RXDATAP_PERRP_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ 588 #define EUSART_RXDATAP_FERRP (0x1UL << 10) /**< Framing Error Peek */ 589 #define _EUSART_RXDATAP_FERRP_SHIFT 10 /**< Shift value for EUSART_FERRP */ 590 #define _EUSART_RXDATAP_FERRP_MASK 0x400UL /**< Bit mask for EUSART_FERRP */ 591 #define _EUSART_RXDATAP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_RXDATAP */ 592 #define EUSART_RXDATAP_FERRP_DEFAULT (_EUSART_RXDATAP_FERRP_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_RXDATAP */ 593 594 /* Bit fields for EUSART TXDATA */ 595 #define _EUSART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for EUSART_TXDATA */ 596 #define _EUSART_TXDATA_MASK 0x00003FFFUL /**< Mask for EUSART_TXDATA */ 597 #define _EUSART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for EUSART_TXDATA */ 598 #define _EUSART_TXDATA_TXDATA_MASK 0x1FFUL /**< Bit mask for EUSART_TXDATA */ 599 #define _EUSART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 600 #define EUSART_TXDATA_TXDATA_DEFAULT (_EUSART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 601 #define EUSART_TXDATA_UBRXAT (0x1UL << 9) /**< Unblock RX After Transmission */ 602 #define _EUSART_TXDATA_UBRXAT_SHIFT 9 /**< Shift value for EUSART_UBRXAT */ 603 #define _EUSART_TXDATA_UBRXAT_MASK 0x200UL /**< Bit mask for EUSART_UBRXAT */ 604 #define _EUSART_TXDATA_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 605 #define EUSART_TXDATA_UBRXAT_DEFAULT (_EUSART_TXDATA_UBRXAT_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 606 #define EUSART_TXDATA_TXTRIAT (0x1UL << 10) /**< Set TXTRI After Transmisssion */ 607 #define _EUSART_TXDATA_TXTRIAT_SHIFT 10 /**< Shift value for EUSART_TXTRIAT */ 608 #define _EUSART_TXDATA_TXTRIAT_MASK 0x400UL /**< Bit mask for EUSART_TXTRIAT */ 609 #define _EUSART_TXDATA_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 610 #define EUSART_TXDATA_TXTRIAT_DEFAULT (_EUSART_TXDATA_TXTRIAT_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 611 #define EUSART_TXDATA_TXBREAK (0x1UL << 11) /**< Transit Data as Break */ 612 #define _EUSART_TXDATA_TXBREAK_SHIFT 11 /**< Shift value for EUSART_TXBREAK */ 613 #define _EUSART_TXDATA_TXBREAK_MASK 0x800UL /**< Bit mask for EUSART_TXBREAK */ 614 #define _EUSART_TXDATA_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 615 #define EUSART_TXDATA_TXBREAK_DEFAULT (_EUSART_TXDATA_TXBREAK_DEFAULT << 11) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 616 #define EUSART_TXDATA_TXDISAT (0x1UL << 12) /**< Clear TXEN After Transmission */ 617 #define _EUSART_TXDATA_TXDISAT_SHIFT 12 /**< Shift value for EUSART_TXDISAT */ 618 #define _EUSART_TXDATA_TXDISAT_MASK 0x1000UL /**< Bit mask for EUSART_TXDISAT */ 619 #define _EUSART_TXDATA_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 620 #define EUSART_TXDATA_TXDISAT_DEFAULT (_EUSART_TXDATA_TXDISAT_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 621 #define EUSART_TXDATA_RXENAT (0x1UL << 13) /**< Enable RXEN After Transmission */ 622 #define _EUSART_TXDATA_RXENAT_SHIFT 13 /**< Shift value for EUSART_RXENAT */ 623 #define _EUSART_TXDATA_RXENAT_MASK 0x2000UL /**< Bit mask for EUSART_RXENAT */ 624 #define _EUSART_TXDATA_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_TXDATA */ 625 #define EUSART_TXDATA_RXENAT_DEFAULT (_EUSART_TXDATA_RXENAT_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_TXDATA */ 626 627 /* Bit fields for EUSART STATUS */ 628 #define _EUSART_STATUS_RESETVALUE 0x00003040UL /**< Default value for EUSART_STATUS */ 629 #define _EUSART_STATUS_MASK 0x010F31FBUL /**< Mask for EUSART_STATUS */ 630 #define EUSART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */ 631 #define _EUSART_STATUS_RXENS_SHIFT 0 /**< Shift value for EUSART_RXENS */ 632 #define _EUSART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for EUSART_RXENS */ 633 #define _EUSART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 634 #define EUSART_STATUS_RXENS_DEFAULT (_EUSART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_STATUS */ 635 #define EUSART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */ 636 #define _EUSART_STATUS_TXENS_SHIFT 1 /**< Shift value for EUSART_TXENS */ 637 #define _EUSART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for EUSART_TXENS */ 638 #define _EUSART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 639 #define EUSART_STATUS_TXENS_DEFAULT (_EUSART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_STATUS */ 640 #define EUSART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */ 641 #define _EUSART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for EUSART_RXBLOCK */ 642 #define _EUSART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for EUSART_RXBLOCK */ 643 #define _EUSART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 644 #define EUSART_STATUS_RXBLOCK_DEFAULT (_EUSART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_STATUS */ 645 #define EUSART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */ 646 #define _EUSART_STATUS_TXTRI_SHIFT 4 /**< Shift value for EUSART_TXTRI */ 647 #define _EUSART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for EUSART_TXTRI */ 648 #define _EUSART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 649 #define EUSART_STATUS_TXTRI_DEFAULT (_EUSART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_STATUS */ 650 #define EUSART_STATUS_TXC (0x1UL << 5) /**< TX Complete */ 651 #define _EUSART_STATUS_TXC_SHIFT 5 /**< Shift value for EUSART_TXC */ 652 #define _EUSART_STATUS_TXC_MASK 0x20UL /**< Bit mask for EUSART_TXC */ 653 #define _EUSART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 654 #define EUSART_STATUS_TXC_DEFAULT (_EUSART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_STATUS */ 655 #define EUSART_STATUS_TXFL (0x1UL << 6) /**< TX FIFO Level */ 656 #define _EUSART_STATUS_TXFL_SHIFT 6 /**< Shift value for EUSART_TXFL */ 657 #define _EUSART_STATUS_TXFL_MASK 0x40UL /**< Bit mask for EUSART_TXFL */ 658 #define _EUSART_STATUS_TXFL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ 659 #define EUSART_STATUS_TXFL_DEFAULT (_EUSART_STATUS_TXFL_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_STATUS */ 660 #define EUSART_STATUS_RXFL (0x1UL << 7) /**< RX FIFO Level */ 661 #define _EUSART_STATUS_RXFL_SHIFT 7 /**< Shift value for EUSART_RXFL */ 662 #define _EUSART_STATUS_RXFL_MASK 0x80UL /**< Bit mask for EUSART_RXFL */ 663 #define _EUSART_STATUS_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 664 #define EUSART_STATUS_RXFL_DEFAULT (_EUSART_STATUS_RXFL_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_STATUS */ 665 #define EUSART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */ 666 #define _EUSART_STATUS_RXFULL_SHIFT 8 /**< Shift value for EUSART_RXFULL */ 667 #define _EUSART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for EUSART_RXFULL */ 668 #define _EUSART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 669 #define EUSART_STATUS_RXFULL_DEFAULT (_EUSART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_STATUS */ 670 #define EUSART_STATUS_RXIDLE (0x1UL << 12) /**< RX Idle */ 671 #define _EUSART_STATUS_RXIDLE_SHIFT 12 /**< Shift value for EUSART_RXIDLE */ 672 #define _EUSART_STATUS_RXIDLE_MASK 0x1000UL /**< Bit mask for EUSART_RXIDLE */ 673 #define _EUSART_STATUS_RXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ 674 #define EUSART_STATUS_RXIDLE_DEFAULT (_EUSART_STATUS_RXIDLE_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_STATUS */ 675 #define EUSART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */ 676 #define _EUSART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ 677 #define _EUSART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ 678 #define _EUSART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EUSART_STATUS */ 679 #define EUSART_STATUS_TXIDLE_DEFAULT (_EUSART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_STATUS */ 680 #define _EUSART_STATUS_TXFCNT_SHIFT 16 /**< Shift value for EUSART_TXFCNT */ 681 #define _EUSART_STATUS_TXFCNT_MASK 0x70000UL /**< Bit mask for EUSART_TXFCNT */ 682 #define _EUSART_STATUS_TXFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 683 #define EUSART_STATUS_TXFCNT_DEFAULT (_EUSART_STATUS_TXFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for EUSART_STATUS */ 684 #define EUSART_STATUS_CLEARTXBUSY (0x1UL << 19) /**< TX FIFO Clear Busy */ 685 #define _EUSART_STATUS_CLEARTXBUSY_SHIFT 19 /**< Shift value for EUSART_CLEARTXBUSY */ 686 #define _EUSART_STATUS_CLEARTXBUSY_MASK 0x80000UL /**< Bit mask for EUSART_CLEARTXBUSY */ 687 #define _EUSART_STATUS_CLEARTXBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 688 #define EUSART_STATUS_CLEARTXBUSY_DEFAULT (_EUSART_STATUS_CLEARTXBUSY_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_STATUS */ 689 #define EUSART_STATUS_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Rate Detection Completed */ 690 #define _EUSART_STATUS_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ 691 #define _EUSART_STATUS_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ 692 #define _EUSART_STATUS_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_STATUS */ 693 #define EUSART_STATUS_AUTOBAUDDONE_DEFAULT (_EUSART_STATUS_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_STATUS */ 694 695 /* Bit fields for EUSART IF */ 696 #define _EUSART_IF_RESETVALUE 0x00000000UL /**< Default value for EUSART_IF */ 697 #define _EUSART_IF_MASK 0x010C377FUL /**< Mask for EUSART_IF */ 698 #define EUSART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */ 699 #define _EUSART_IF_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ 700 #define _EUSART_IF_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ 701 #define _EUSART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 702 #define EUSART_IF_TXC_DEFAULT (_EUSART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IF */ 703 #define EUSART_IF_TXFL (0x1UL << 1) /**< TX FIFO Level Interrupt Flag */ 704 #define _EUSART_IF_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ 705 #define _EUSART_IF_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ 706 #define _EUSART_IF_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 707 #define EUSART_IF_TXFL_DEFAULT (_EUSART_IF_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IF */ 708 #define EUSART_IF_RXFL (0x1UL << 2) /**< RX FIFO Level Interrupt Flag */ 709 #define _EUSART_IF_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ 710 #define _EUSART_IF_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ 711 #define _EUSART_IF_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 712 #define EUSART_IF_RXFL_DEFAULT (_EUSART_IF_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IF */ 713 #define EUSART_IF_RXFULL (0x1UL << 3) /**< RX FIFO Full Interrupt Flag */ 714 #define _EUSART_IF_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ 715 #define _EUSART_IF_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ 716 #define _EUSART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 717 #define EUSART_IF_RXFULL_DEFAULT (_EUSART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IF */ 718 #define EUSART_IF_RXOF (0x1UL << 4) /**< RX FIFO Overflow Interrupt Flag */ 719 #define _EUSART_IF_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ 720 #define _EUSART_IF_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ 721 #define _EUSART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 722 #define EUSART_IF_RXOF_DEFAULT (_EUSART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IF */ 723 #define EUSART_IF_RXUF (0x1UL << 5) /**< RX FIFO Underflow Interrupt Flag */ 724 #define _EUSART_IF_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ 725 #define _EUSART_IF_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ 726 #define _EUSART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 727 #define EUSART_IF_RXUF_DEFAULT (_EUSART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IF */ 728 #define EUSART_IF_TXOF (0x1UL << 6) /**< TX FIFO Overflow Interrupt Flag */ 729 #define _EUSART_IF_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ 730 #define _EUSART_IF_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ 731 #define _EUSART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 732 #define EUSART_IF_TXOF_DEFAULT (_EUSART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IF */ 733 #define EUSART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */ 734 #define _EUSART_IF_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ 735 #define _EUSART_IF_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ 736 #define _EUSART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 737 #define EUSART_IF_PERR_DEFAULT (_EUSART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IF */ 738 #define EUSART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */ 739 #define _EUSART_IF_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ 740 #define _EUSART_IF_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ 741 #define _EUSART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 742 #define EUSART_IF_FERR_DEFAULT (_EUSART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IF */ 743 #define EUSART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt */ 744 #define _EUSART_IF_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ 745 #define _EUSART_IF_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ 746 #define _EUSART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 747 #define EUSART_IF_MPAF_DEFAULT (_EUSART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IF */ 748 #define EUSART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */ 749 #define _EUSART_IF_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ 750 #define _EUSART_IF_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ 751 #define _EUSART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 752 #define EUSART_IF_CCF_DEFAULT (_EUSART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IF */ 753 #define EUSART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */ 754 #define _EUSART_IF_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ 755 #define _EUSART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ 756 #define _EUSART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 757 #define EUSART_IF_TXIDLE_DEFAULT (_EUSART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IF */ 758 #define EUSART_IF_STARTF (0x1UL << 18) /**< Start Frame Interrupt Flag */ 759 #define _EUSART_IF_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ 760 #define _EUSART_IF_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ 761 #define _EUSART_IF_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 762 #define EUSART_IF_STARTF_DEFAULT (_EUSART_IF_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IF */ 763 #define EUSART_IF_SIGF (0x1UL << 19) /**< Signal Frame Interrupt Flag */ 764 #define _EUSART_IF_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ 765 #define _EUSART_IF_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ 766 #define _EUSART_IF_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 767 #define EUSART_IF_SIGF_DEFAULT (_EUSART_IF_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IF */ 768 #define EUSART_IF_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete Interrupt Flag */ 769 #define _EUSART_IF_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ 770 #define _EUSART_IF_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ 771 #define _EUSART_IF_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IF */ 772 #define EUSART_IF_AUTOBAUDDONE_DEFAULT (_EUSART_IF_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IF */ 773 774 /* Bit fields for EUSART IEN */ 775 #define _EUSART_IEN_RESETVALUE 0x00000000UL /**< Default value for EUSART_IEN */ 776 #define _EUSART_IEN_MASK 0x010C377FUL /**< Mask for EUSART_IEN */ 777 #define EUSART_IEN_TXC (0x1UL << 0) /**< TX Complete IEN */ 778 #define _EUSART_IEN_TXC_SHIFT 0 /**< Shift value for EUSART_TXC */ 779 #define _EUSART_IEN_TXC_MASK 0x1UL /**< Bit mask for EUSART_TXC */ 780 #define _EUSART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 781 #define EUSART_IEN_TXC_DEFAULT (_EUSART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_IEN */ 782 #define EUSART_IEN_TXFL (0x1UL << 1) /**< TX FIFO Level IEN */ 783 #define _EUSART_IEN_TXFL_SHIFT 1 /**< Shift value for EUSART_TXFL */ 784 #define _EUSART_IEN_TXFL_MASK 0x2UL /**< Bit mask for EUSART_TXFL */ 785 #define _EUSART_IEN_TXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 786 #define EUSART_IEN_TXFL_DEFAULT (_EUSART_IEN_TXFL_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_IEN */ 787 #define EUSART_IEN_RXFL (0x1UL << 2) /**< RX FIFO Level IEN */ 788 #define _EUSART_IEN_RXFL_SHIFT 2 /**< Shift value for EUSART_RXFL */ 789 #define _EUSART_IEN_RXFL_MASK 0x4UL /**< Bit mask for EUSART_RXFL */ 790 #define _EUSART_IEN_RXFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 791 #define EUSART_IEN_RXFL_DEFAULT (_EUSART_IEN_RXFL_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_IEN */ 792 #define EUSART_IEN_RXFULL (0x1UL << 3) /**< RX FIFO Full IEN */ 793 #define _EUSART_IEN_RXFULL_SHIFT 3 /**< Shift value for EUSART_RXFULL */ 794 #define _EUSART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for EUSART_RXFULL */ 795 #define _EUSART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 796 #define EUSART_IEN_RXFULL_DEFAULT (_EUSART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_IEN */ 797 #define EUSART_IEN_RXOF (0x1UL << 4) /**< RX FIFO Overflow IEN */ 798 #define _EUSART_IEN_RXOF_SHIFT 4 /**< Shift value for EUSART_RXOF */ 799 #define _EUSART_IEN_RXOF_MASK 0x10UL /**< Bit mask for EUSART_RXOF */ 800 #define _EUSART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 801 #define EUSART_IEN_RXOF_DEFAULT (_EUSART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_IEN */ 802 #define EUSART_IEN_RXUF (0x1UL << 5) /**< RX FIFO Underflow IEN */ 803 #define _EUSART_IEN_RXUF_SHIFT 5 /**< Shift value for EUSART_RXUF */ 804 #define _EUSART_IEN_RXUF_MASK 0x20UL /**< Bit mask for EUSART_RXUF */ 805 #define _EUSART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 806 #define EUSART_IEN_RXUF_DEFAULT (_EUSART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_IEN */ 807 #define EUSART_IEN_TXOF (0x1UL << 6) /**< TX FIFO Overflow IEN */ 808 #define _EUSART_IEN_TXOF_SHIFT 6 /**< Shift value for EUSART_TXOF */ 809 #define _EUSART_IEN_TXOF_MASK 0x40UL /**< Bit mask for EUSART_TXOF */ 810 #define _EUSART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 811 #define EUSART_IEN_TXOF_DEFAULT (_EUSART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_IEN */ 812 #define EUSART_IEN_PERR (0x1UL << 8) /**< Parity Error IEN */ 813 #define _EUSART_IEN_PERR_SHIFT 8 /**< Shift value for EUSART_PERR */ 814 #define _EUSART_IEN_PERR_MASK 0x100UL /**< Bit mask for EUSART_PERR */ 815 #define _EUSART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 816 #define EUSART_IEN_PERR_DEFAULT (_EUSART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_IEN */ 817 #define EUSART_IEN_FERR (0x1UL << 9) /**< Framing Error IEN */ 818 #define _EUSART_IEN_FERR_SHIFT 9 /**< Shift value for EUSART_FERR */ 819 #define _EUSART_IEN_FERR_MASK 0x200UL /**< Bit mask for EUSART_FERR */ 820 #define _EUSART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 821 #define EUSART_IEN_FERR_DEFAULT (_EUSART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_IEN */ 822 #define EUSART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Addr Frame IEN */ 823 #define _EUSART_IEN_MPAF_SHIFT 10 /**< Shift value for EUSART_MPAF */ 824 #define _EUSART_IEN_MPAF_MASK 0x400UL /**< Bit mask for EUSART_MPAF */ 825 #define _EUSART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 826 #define EUSART_IEN_MPAF_DEFAULT (_EUSART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_IEN */ 827 #define EUSART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail IEN */ 828 #define _EUSART_IEN_CCF_SHIFT 12 /**< Shift value for EUSART_CCF */ 829 #define _EUSART_IEN_CCF_MASK 0x1000UL /**< Bit mask for EUSART_CCF */ 830 #define _EUSART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 831 #define EUSART_IEN_CCF_DEFAULT (_EUSART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for EUSART_IEN */ 832 #define EUSART_IEN_TXIDLE (0x1UL << 13) /**< TX IDLE IEN */ 833 #define _EUSART_IEN_TXIDLE_SHIFT 13 /**< Shift value for EUSART_TXIDLE */ 834 #define _EUSART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for EUSART_TXIDLE */ 835 #define _EUSART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 836 #define EUSART_IEN_TXIDLE_DEFAULT (_EUSART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for EUSART_IEN */ 837 #define EUSART_IEN_STARTF (0x1UL << 18) /**< Start Frame IEN */ 838 #define _EUSART_IEN_STARTF_SHIFT 18 /**< Shift value for EUSART_STARTF */ 839 #define _EUSART_IEN_STARTF_MASK 0x40000UL /**< Bit mask for EUSART_STARTF */ 840 #define _EUSART_IEN_STARTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 841 #define EUSART_IEN_STARTF_DEFAULT (_EUSART_IEN_STARTF_DEFAULT << 18) /**< Shifted mode DEFAULT for EUSART_IEN */ 842 #define EUSART_IEN_SIGF (0x1UL << 19) /**< Signal Frame IEN */ 843 #define _EUSART_IEN_SIGF_SHIFT 19 /**< Shift value for EUSART_SIGF */ 844 #define _EUSART_IEN_SIGF_MASK 0x80000UL /**< Bit mask for EUSART_SIGF */ 845 #define _EUSART_IEN_SIGF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 846 #define EUSART_IEN_SIGF_DEFAULT (_EUSART_IEN_SIGF_DEFAULT << 19) /**< Shifted mode DEFAULT for EUSART_IEN */ 847 #define EUSART_IEN_AUTOBAUDDONE (0x1UL << 24) /**< Auto Baud Complete IEN */ 848 #define _EUSART_IEN_AUTOBAUDDONE_SHIFT 24 /**< Shift value for EUSART_AUTOBAUDDONE */ 849 #define _EUSART_IEN_AUTOBAUDDONE_MASK 0x1000000UL /**< Bit mask for EUSART_AUTOBAUDDONE */ 850 #define _EUSART_IEN_AUTOBAUDDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_IEN */ 851 #define EUSART_IEN_AUTOBAUDDONE_DEFAULT (_EUSART_IEN_AUTOBAUDDONE_DEFAULT << 24) /**< Shifted mode DEFAULT for EUSART_IEN */ 852 853 /* Bit fields for EUSART SYNCBUSY */ 854 #define _EUSART_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for EUSART_SYNCBUSY */ 855 #define _EUSART_SYNCBUSY_MASK 0x000007FFUL /**< Mask for EUSART_SYNCBUSY */ 856 #define EUSART_SYNCBUSY_DIV (0x1UL << 0) /**< SYNCBUSY for DIV in CLKDIV */ 857 #define _EUSART_SYNCBUSY_DIV_SHIFT 0 /**< Shift value for EUSART_DIV */ 858 #define _EUSART_SYNCBUSY_DIV_MASK 0x1UL /**< Bit mask for EUSART_DIV */ 859 #define _EUSART_SYNCBUSY_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 860 #define EUSART_SYNCBUSY_DIV_DEFAULT (_EUSART_SYNCBUSY_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 861 #define EUSART_SYNCBUSY_RXTEN (0x1UL << 1) /**< SYNCBUSY for RXTEN in TRIGCTRL */ 862 #define _EUSART_SYNCBUSY_RXTEN_SHIFT 1 /**< Shift value for EUSART_RXTEN */ 863 #define _EUSART_SYNCBUSY_RXTEN_MASK 0x2UL /**< Bit mask for EUSART_RXTEN */ 864 #define _EUSART_SYNCBUSY_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 865 #define EUSART_SYNCBUSY_RXTEN_DEFAULT (_EUSART_SYNCBUSY_RXTEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 866 #define EUSART_SYNCBUSY_TXTEN (0x1UL << 2) /**< SYNCBUSY for TXTEN in TRIGCTRL */ 867 #define _EUSART_SYNCBUSY_TXTEN_SHIFT 2 /**< Shift value for EUSART_TXTEN */ 868 #define _EUSART_SYNCBUSY_TXTEN_MASK 0x4UL /**< Bit mask for EUSART_TXTEN */ 869 #define _EUSART_SYNCBUSY_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 870 #define EUSART_SYNCBUSY_TXTEN_DEFAULT (_EUSART_SYNCBUSY_TXTEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 871 #define EUSART_SYNCBUSY_RXEN (0x1UL << 3) /**< SYNCBUSY for RXEN in CMD */ 872 #define _EUSART_SYNCBUSY_RXEN_SHIFT 3 /**< Shift value for EUSART_RXEN */ 873 #define _EUSART_SYNCBUSY_RXEN_MASK 0x8UL /**< Bit mask for EUSART_RXEN */ 874 #define _EUSART_SYNCBUSY_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 875 #define EUSART_SYNCBUSY_RXEN_DEFAULT (_EUSART_SYNCBUSY_RXEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 876 #define EUSART_SYNCBUSY_RXDIS (0x1UL << 4) /**< SYNCBUSY for RXDIS in CMD */ 877 #define _EUSART_SYNCBUSY_RXDIS_SHIFT 4 /**< Shift value for EUSART_RXDIS */ 878 #define _EUSART_SYNCBUSY_RXDIS_MASK 0x10UL /**< Bit mask for EUSART_RXDIS */ 879 #define _EUSART_SYNCBUSY_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 880 #define EUSART_SYNCBUSY_RXDIS_DEFAULT (_EUSART_SYNCBUSY_RXDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 881 #define EUSART_SYNCBUSY_TXEN (0x1UL << 5) /**< SYNCBUSY for TXEN in CMD */ 882 #define _EUSART_SYNCBUSY_TXEN_SHIFT 5 /**< Shift value for EUSART_TXEN */ 883 #define _EUSART_SYNCBUSY_TXEN_MASK 0x20UL /**< Bit mask for EUSART_TXEN */ 884 #define _EUSART_SYNCBUSY_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 885 #define EUSART_SYNCBUSY_TXEN_DEFAULT (_EUSART_SYNCBUSY_TXEN_DEFAULT << 5) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 886 #define EUSART_SYNCBUSY_TXDIS (0x1UL << 6) /**< SYNCBUSY for TXDIS in CMD */ 887 #define _EUSART_SYNCBUSY_TXDIS_SHIFT 6 /**< Shift value for EUSART_TXDIS */ 888 #define _EUSART_SYNCBUSY_TXDIS_MASK 0x40UL /**< Bit mask for EUSART_TXDIS */ 889 #define _EUSART_SYNCBUSY_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 890 #define EUSART_SYNCBUSY_TXDIS_DEFAULT (_EUSART_SYNCBUSY_TXDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 891 #define EUSART_SYNCBUSY_RXBLOCKEN (0x1UL << 7) /**< SYNCBUSY for RXBLOCKEN in CMD */ 892 #define _EUSART_SYNCBUSY_RXBLOCKEN_SHIFT 7 /**< Shift value for EUSART_RXBLOCKEN */ 893 #define _EUSART_SYNCBUSY_RXBLOCKEN_MASK 0x80UL /**< Bit mask for EUSART_RXBLOCKEN */ 894 #define _EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 895 #define EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKEN_DEFAULT << 7) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 896 #define EUSART_SYNCBUSY_RXBLOCKDIS (0x1UL << 8) /**< SYNCBUSY for RXBLOCKDIS in CMD */ 897 #define _EUSART_SYNCBUSY_RXBLOCKDIS_SHIFT 8 /**< Shift value for EUSART_RXBLOCKDIS */ 898 #define _EUSART_SYNCBUSY_RXBLOCKDIS_MASK 0x100UL /**< Bit mask for EUSART_RXBLOCKDIS */ 899 #define _EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 900 #define EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT (_EUSART_SYNCBUSY_RXBLOCKDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 901 #define EUSART_SYNCBUSY_TXTRIEN (0x1UL << 9) /**< SYNCBUSY for TXTRIEN in CMD */ 902 #define _EUSART_SYNCBUSY_TXTRIEN_SHIFT 9 /**< Shift value for EUSART_TXTRIEN */ 903 #define _EUSART_SYNCBUSY_TXTRIEN_MASK 0x200UL /**< Bit mask for EUSART_TXTRIEN */ 904 #define _EUSART_SYNCBUSY_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 905 #define EUSART_SYNCBUSY_TXTRIEN_DEFAULT (_EUSART_SYNCBUSY_TXTRIEN_DEFAULT << 9) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 906 #define EUSART_SYNCBUSY_TXTRIDIS (0x1UL << 10) /**< SYNCBUSY in TXTRIDIS in CMD */ 907 #define _EUSART_SYNCBUSY_TXTRIDIS_SHIFT 10 /**< Shift value for EUSART_TXTRIDIS */ 908 #define _EUSART_SYNCBUSY_TXTRIDIS_MASK 0x400UL /**< Bit mask for EUSART_TXTRIDIS */ 909 #define _EUSART_SYNCBUSY_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EUSART_SYNCBUSY */ 910 #define EUSART_SYNCBUSY_TXTRIDIS_DEFAULT (_EUSART_SYNCBUSY_TXTRIDIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EUSART_SYNCBUSY */ 911 912 /** @} End of group EFR32BG22_EUSART_BitFields */ 913 /** @} End of group EFR32BG22_EUSART */ 914 /** @} End of group Parts */ 915 916 #endif /* EFR32BG22_EUSART_H */ 917
