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Searched refs:DMA_STATUS_STATE_WAITREQCLR (Results 1 – 25 of 35) sorted by relevance

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/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32HG/Include/
Defm32hg_dma.h115 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32hg321f32.h475 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32hg321f64.h475 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32hg108f32.h521 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32hg108f64.h521 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32hg308f32.h533 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32hg308f64.h533 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32WG/Include/
Defm32wg_dma.h123 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg360f128.h560 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg360f256.h560 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg360f64.h560 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg842f128.h640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg840f256.h640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg840f64.h640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg842f256.h640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg330f256.h648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg330f64.h648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg332f128.h648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg332f256.h648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg332f64.h648 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg840f128.h640 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg940f128.h653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg940f256.h653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg942f128.h653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro
Defm32wg942f256.h653 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< … macro

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