DMA_CHWAITSTATUS_CH5WAITSTATUS (reference) in projects: hal_silabs-3.5.0

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Searched refs:DMA_CHWAITSTATUS_CH5WAITSTATUS (Results 1 – 25 of 35) sorted by relevance

/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32HG/Include/
D	efm32hg_dma.h	`183 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32hg321f32.h	`543 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32hg321f64.h	`543 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32hg108f32.h	`589 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32hg108f64.h	`589 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32hg308f32.h	`601 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32hg308f64.h	`601 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
/hal_silabs-3.5.0/gecko/Device/SiliconLabs/EFM32WG/Include/
D	efm32wg_dma.h	`191 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg360f128.h	`628 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg360f256.h	`628 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg360f64.h	`628 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg842f128.h	`708 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg840f256.h	`708 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg840f64.h	`708 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg842f256.h	`708 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg330f256.h	`716 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg330f64.h	`716 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg332f128.h	`716 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg332f256.h	`716 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg332f64.h	`716 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg840f128.h	`708 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg940f128.h	`721 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg940f256.h	`721 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg942f128.h	`721 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`
D	efm32wg942f256.h	`721 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) … macro`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
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babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
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