1 /**************************************************************************//** 2 * @file 3 * @brief EFR32BG27 DCDC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32BG27_DCDC_H 31 #define EFR32BG27_DCDC_H 32 #define DCDC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32BG27_DCDC DCDC 40 * @{ 41 * @brief EFR32BG27 DCDC Register Declaration. 42 *****************************************************************************/ 43 44 /** DCDC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IPVERSION */ 47 __IOM uint32_t CTRL; /**< Control */ 48 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 49 __IOM uint32_t EM01CTRL0; /**< EM01 Control */ 50 __IOM uint32_t EM23CTRL0; /**< EM23 Control */ 51 uint32_t RESERVED1[3U]; /**< Reserved for future use */ 52 __IOM uint32_t BSTCTRL; /**< Boost Control Register */ 53 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 54 __IOM uint32_t BSTEM01CTRL; /**< EM01 Boost Control */ 55 __IOM uint32_t BSTEM23CTRL; /**< EM23 Boost Control */ 56 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 57 __IOM uint32_t IF; /**< Interrupt Flags */ 58 __IOM uint32_t IEN; /**< Interrupt Enable */ 59 __IM uint32_t STATUS; /**< Status Register */ 60 __IM uint32_t SYNCBUSY; /**< Syncbusy Status Register */ 61 uint32_t RESERVED4[7U]; /**< Reserved for future use */ 62 __IOM uint32_t CCCTRL; /**< Coulomb Counter Control */ 63 __IOM uint32_t CCCALCTRL; /**< Coulomb Counter Calibration Control */ 64 __IOM uint32_t CCCMD; /**< Coulomb Counter Command */ 65 __IM uint32_t CCEM0CNT; /**< Coulomb Counter EM0 Count Value */ 66 __IM uint32_t CCEM2CNT; /**< Coulomb Counter EM2 Count Value */ 67 __IOM uint32_t CCTHR; /**< Coulomb Counter Threshold */ 68 __IOM uint32_t CCIF; /**< Coulomb Counter Interrupt Flag */ 69 __IOM uint32_t CCIEN; /**< Coulomb Counter Interrupt Enable */ 70 __IM uint32_t CCSTATUS; /**< Coulomb Counter Status */ 71 uint32_t RESERVED5[3U]; /**< Reserved for future use */ 72 __IOM uint32_t LOCK; /**< Lock Register */ 73 __IM uint32_t LOCKSTATUS; /**< Lock Status Register */ 74 uint32_t RESERVED6[2U]; /**< Reserved for future use */ 75 uint32_t RESERVED7[1U]; /**< Reserved for future use */ 76 uint32_t RESERVED8[7U]; /**< Reserved for future use */ 77 uint32_t RESERVED9[1U]; /**< Reserved for future use */ 78 uint32_t RESERVED10[975U]; /**< Reserved for future use */ 79 __IM uint32_t IPVERSION_SET; /**< IPVERSION */ 80 __IOM uint32_t CTRL_SET; /**< Control */ 81 uint32_t RESERVED11[1U]; /**< Reserved for future use */ 82 __IOM uint32_t EM01CTRL0_SET; /**< EM01 Control */ 83 __IOM uint32_t EM23CTRL0_SET; /**< EM23 Control */ 84 uint32_t RESERVED12[3U]; /**< Reserved for future use */ 85 __IOM uint32_t BSTCTRL_SET; /**< Boost Control Register */ 86 uint32_t RESERVED13[1U]; /**< Reserved for future use */ 87 __IOM uint32_t BSTEM01CTRL_SET; /**< EM01 Boost Control */ 88 __IOM uint32_t BSTEM23CTRL_SET; /**< EM23 Boost Control */ 89 uint32_t RESERVED14[1U]; /**< Reserved for future use */ 90 __IOM uint32_t IF_SET; /**< Interrupt Flags */ 91 __IOM uint32_t IEN_SET; /**< Interrupt Enable */ 92 __IM uint32_t STATUS_SET; /**< Status Register */ 93 __IM uint32_t SYNCBUSY_SET; /**< Syncbusy Status Register */ 94 uint32_t RESERVED15[7U]; /**< Reserved for future use */ 95 __IOM uint32_t CCCTRL_SET; /**< Coulomb Counter Control */ 96 __IOM uint32_t CCCALCTRL_SET; /**< Coulomb Counter Calibration Control */ 97 __IOM uint32_t CCCMD_SET; /**< Coulomb Counter Command */ 98 __IM uint32_t CCEM0CNT_SET; /**< Coulomb Counter EM0 Count Value */ 99 __IM uint32_t CCEM2CNT_SET; /**< Coulomb Counter EM2 Count Value */ 100 __IOM uint32_t CCTHR_SET; /**< Coulomb Counter Threshold */ 101 __IOM uint32_t CCIF_SET; /**< Coulomb Counter Interrupt Flag */ 102 __IOM uint32_t CCIEN_SET; /**< Coulomb Counter Interrupt Enable */ 103 __IM uint32_t CCSTATUS_SET; /**< Coulomb Counter Status */ 104 uint32_t RESERVED16[3U]; /**< Reserved for future use */ 105 __IOM uint32_t LOCK_SET; /**< Lock Register */ 106 __IM uint32_t LOCKSTATUS_SET; /**< Lock Status Register */ 107 uint32_t RESERVED17[2U]; /**< Reserved for future use */ 108 uint32_t RESERVED18[1U]; /**< Reserved for future use */ 109 uint32_t RESERVED19[7U]; /**< Reserved for future use */ 110 uint32_t RESERVED20[1U]; /**< Reserved for future use */ 111 uint32_t RESERVED21[975U]; /**< Reserved for future use */ 112 __IM uint32_t IPVERSION_CLR; /**< IPVERSION */ 113 __IOM uint32_t CTRL_CLR; /**< Control */ 114 uint32_t RESERVED22[1U]; /**< Reserved for future use */ 115 __IOM uint32_t EM01CTRL0_CLR; /**< EM01 Control */ 116 __IOM uint32_t EM23CTRL0_CLR; /**< EM23 Control */ 117 uint32_t RESERVED23[3U]; /**< Reserved for future use */ 118 __IOM uint32_t BSTCTRL_CLR; /**< Boost Control Register */ 119 uint32_t RESERVED24[1U]; /**< Reserved for future use */ 120 __IOM uint32_t BSTEM01CTRL_CLR; /**< EM01 Boost Control */ 121 __IOM uint32_t BSTEM23CTRL_CLR; /**< EM23 Boost Control */ 122 uint32_t RESERVED25[1U]; /**< Reserved for future use */ 123 __IOM uint32_t IF_CLR; /**< Interrupt Flags */ 124 __IOM uint32_t IEN_CLR; /**< Interrupt Enable */ 125 __IM uint32_t STATUS_CLR; /**< Status Register */ 126 __IM uint32_t SYNCBUSY_CLR; /**< Syncbusy Status Register */ 127 uint32_t RESERVED26[7U]; /**< Reserved for future use */ 128 __IOM uint32_t CCCTRL_CLR; /**< Coulomb Counter Control */ 129 __IOM uint32_t CCCALCTRL_CLR; /**< Coulomb Counter Calibration Control */ 130 __IOM uint32_t CCCMD_CLR; /**< Coulomb Counter Command */ 131 __IM uint32_t CCEM0CNT_CLR; /**< Coulomb Counter EM0 Count Value */ 132 __IM uint32_t CCEM2CNT_CLR; /**< Coulomb Counter EM2 Count Value */ 133 __IOM uint32_t CCTHR_CLR; /**< Coulomb Counter Threshold */ 134 __IOM uint32_t CCIF_CLR; /**< Coulomb Counter Interrupt Flag */ 135 __IOM uint32_t CCIEN_CLR; /**< Coulomb Counter Interrupt Enable */ 136 __IM uint32_t CCSTATUS_CLR; /**< Coulomb Counter Status */ 137 uint32_t RESERVED27[3U]; /**< Reserved for future use */ 138 __IOM uint32_t LOCK_CLR; /**< Lock Register */ 139 __IM uint32_t LOCKSTATUS_CLR; /**< Lock Status Register */ 140 uint32_t RESERVED28[2U]; /**< Reserved for future use */ 141 uint32_t RESERVED29[1U]; /**< Reserved for future use */ 142 uint32_t RESERVED30[7U]; /**< Reserved for future use */ 143 uint32_t RESERVED31[1U]; /**< Reserved for future use */ 144 uint32_t RESERVED32[975U]; /**< Reserved for future use */ 145 __IM uint32_t IPVERSION_TGL; /**< IPVERSION */ 146 __IOM uint32_t CTRL_TGL; /**< Control */ 147 uint32_t RESERVED33[1U]; /**< Reserved for future use */ 148 __IOM uint32_t EM01CTRL0_TGL; /**< EM01 Control */ 149 __IOM uint32_t EM23CTRL0_TGL; /**< EM23 Control */ 150 uint32_t RESERVED34[3U]; /**< Reserved for future use */ 151 __IOM uint32_t BSTCTRL_TGL; /**< Boost Control Register */ 152 uint32_t RESERVED35[1U]; /**< Reserved for future use */ 153 __IOM uint32_t BSTEM01CTRL_TGL; /**< EM01 Boost Control */ 154 __IOM uint32_t BSTEM23CTRL_TGL; /**< EM23 Boost Control */ 155 uint32_t RESERVED36[1U]; /**< Reserved for future use */ 156 __IOM uint32_t IF_TGL; /**< Interrupt Flags */ 157 __IOM uint32_t IEN_TGL; /**< Interrupt Enable */ 158 __IM uint32_t STATUS_TGL; /**< Status Register */ 159 __IM uint32_t SYNCBUSY_TGL; /**< Syncbusy Status Register */ 160 uint32_t RESERVED37[7U]; /**< Reserved for future use */ 161 __IOM uint32_t CCCTRL_TGL; /**< Coulomb Counter Control */ 162 __IOM uint32_t CCCALCTRL_TGL; /**< Coulomb Counter Calibration Control */ 163 __IOM uint32_t CCCMD_TGL; /**< Coulomb Counter Command */ 164 __IM uint32_t CCEM0CNT_TGL; /**< Coulomb Counter EM0 Count Value */ 165 __IM uint32_t CCEM2CNT_TGL; /**< Coulomb Counter EM2 Count Value */ 166 __IOM uint32_t CCTHR_TGL; /**< Coulomb Counter Threshold */ 167 __IOM uint32_t CCIF_TGL; /**< Coulomb Counter Interrupt Flag */ 168 __IOM uint32_t CCIEN_TGL; /**< Coulomb Counter Interrupt Enable */ 169 __IM uint32_t CCSTATUS_TGL; /**< Coulomb Counter Status */ 170 uint32_t RESERVED38[3U]; /**< Reserved for future use */ 171 __IOM uint32_t LOCK_TGL; /**< Lock Register */ 172 __IM uint32_t LOCKSTATUS_TGL; /**< Lock Status Register */ 173 uint32_t RESERVED39[2U]; /**< Reserved for future use */ 174 uint32_t RESERVED40[1U]; /**< Reserved for future use */ 175 uint32_t RESERVED41[7U]; /**< Reserved for future use */ 176 uint32_t RESERVED42[1U]; /**< Reserved for future use */ 177 } DCDC_TypeDef; 178 /** @} End of group EFR32BG27_DCDC */ 179 180 /**************************************************************************//** 181 * @addtogroup EFR32BG27_DCDC 182 * @{ 183 * @defgroup EFR32BG27_DCDC_BitFields DCDC Bit Fields 184 * @{ 185 *****************************************************************************/ 186 187 /* Bit fields for DCDC IPVERSION */ 188 #define _DCDC_IPVERSION_RESETVALUE 0x00000003UL /**< Default value for DCDC_IPVERSION */ 189 #define _DCDC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for DCDC_IPVERSION */ 190 #define _DCDC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for DCDC_IPVERSION */ 191 #define _DCDC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_IPVERSION */ 192 #define _DCDC_IPVERSION_IPVERSION_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_IPVERSION */ 193 #define DCDC_IPVERSION_IPVERSION_DEFAULT (_DCDC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IPVERSION */ 194 195 /* Bit fields for DCDC CTRL */ 196 #define _DCDC_CTRL_RESETVALUE 0x00000040UL /**< Default value for DCDC_CTRL */ 197 #define _DCDC_CTRL_MASK 0x00000071UL /**< Mask for DCDC_CTRL */ 198 #define DCDC_CTRL_MODE (0x1UL << 0) /**< DCDC/Bypass Mode Control */ 199 #define _DCDC_CTRL_MODE_SHIFT 0 /**< Shift value for DCDC_MODE */ 200 #define _DCDC_CTRL_MODE_MASK 0x1UL /**< Bit mask for DCDC_MODE */ 201 #define _DCDC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CTRL */ 202 #define _DCDC_CTRL_MODE_BYPASS 0x00000000UL /**< Mode BYPASS for DCDC_CTRL */ 203 #define _DCDC_CTRL_MODE_DCDCREGULATION 0x00000001UL /**< Mode DCDCREGULATION for DCDC_CTRL */ 204 #define DCDC_CTRL_MODE_DEFAULT (_DCDC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CTRL */ 205 #define DCDC_CTRL_MODE_BYPASS (_DCDC_CTRL_MODE_BYPASS << 0) /**< Shifted mode BYPASS for DCDC_CTRL */ 206 #define DCDC_CTRL_MODE_DCDCREGULATION (_DCDC_CTRL_MODE_DCDCREGULATION << 0) /**< Shifted mode DCDCREGULATION for DCDC_CTRL */ 207 #define _DCDC_CTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ 208 #define _DCDC_CTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ 209 #define _DCDC_CTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_CTRL */ 210 #define _DCDC_CTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_CTRL */ 211 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_CTRL */ 212 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_CTRL */ 213 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_CTRL */ 214 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_CTRL */ 215 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_CTRL */ 216 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_CTRL */ 217 #define _DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_CTRL */ 218 #define DCDC_CTRL_IPKTMAXCTRL_DEFAULT (_DCDC_CTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_CTRL */ 219 #define DCDC_CTRL_IPKTMAXCTRL_OFF (_DCDC_CTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_CTRL */ 220 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_CTRL */ 221 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_CTRL */ 222 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_CTRL */ 223 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_CTRL */ 224 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_CTRL */ 225 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_CTRL */ 226 #define DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_CTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_CTRL */ 227 228 /* Bit fields for DCDC EM01CTRL0 */ 229 #define _DCDC_EM01CTRL0_RESETVALUE 0x00000109UL /**< Default value for DCDC_EM01CTRL0 */ 230 #define _DCDC_EM01CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM01CTRL0 */ 231 #define _DCDC_EM01CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 232 #define _DCDC_EM01CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 233 #define _DCDC_EM01CTRL0_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ 234 #define _DCDC_EM01CTRL0_IPKVAL_Load36mA 0x00000003UL /**< Mode Load36mA for DCDC_EM01CTRL0 */ 235 #define _DCDC_EM01CTRL0_IPKVAL_Load40mA 0x00000004UL /**< Mode Load40mA for DCDC_EM01CTRL0 */ 236 #define _DCDC_EM01CTRL0_IPKVAL_Load44mA 0x00000005UL /**< Mode Load44mA for DCDC_EM01CTRL0 */ 237 #define _DCDC_EM01CTRL0_IPKVAL_Load48mA 0x00000006UL /**< Mode Load48mA for DCDC_EM01CTRL0 */ 238 #define _DCDC_EM01CTRL0_IPKVAL_Load52mA 0x00000007UL /**< Mode Load52mA for DCDC_EM01CTRL0 */ 239 #define _DCDC_EM01CTRL0_IPKVAL_Load56mA 0x00000008UL /**< Mode Load56mA for DCDC_EM01CTRL0 */ 240 #define _DCDC_EM01CTRL0_IPKVAL_Load60mA 0x00000009UL /**< Mode Load60mA for DCDC_EM01CTRL0 */ 241 #define DCDC_EM01CTRL0_IPKVAL_DEFAULT (_DCDC_EM01CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ 242 #define DCDC_EM01CTRL0_IPKVAL_Load36mA (_DCDC_EM01CTRL0_IPKVAL_Load36mA << 0) /**< Shifted mode Load36mA for DCDC_EM01CTRL0 */ 243 #define DCDC_EM01CTRL0_IPKVAL_Load40mA (_DCDC_EM01CTRL0_IPKVAL_Load40mA << 0) /**< Shifted mode Load40mA for DCDC_EM01CTRL0 */ 244 #define DCDC_EM01CTRL0_IPKVAL_Load44mA (_DCDC_EM01CTRL0_IPKVAL_Load44mA << 0) /**< Shifted mode Load44mA for DCDC_EM01CTRL0 */ 245 #define DCDC_EM01CTRL0_IPKVAL_Load48mA (_DCDC_EM01CTRL0_IPKVAL_Load48mA << 0) /**< Shifted mode Load48mA for DCDC_EM01CTRL0 */ 246 #define DCDC_EM01CTRL0_IPKVAL_Load52mA (_DCDC_EM01CTRL0_IPKVAL_Load52mA << 0) /**< Shifted mode Load52mA for DCDC_EM01CTRL0 */ 247 #define DCDC_EM01CTRL0_IPKVAL_Load56mA (_DCDC_EM01CTRL0_IPKVAL_Load56mA << 0) /**< Shifted mode Load56mA for DCDC_EM01CTRL0 */ 248 #define DCDC_EM01CTRL0_IPKVAL_Load60mA (_DCDC_EM01CTRL0_IPKVAL_Load60mA << 0) /**< Shifted mode Load60mA for DCDC_EM01CTRL0 */ 249 #define _DCDC_EM01CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 250 #define _DCDC_EM01CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 251 #define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM01CTRL0 */ 252 #define _DCDC_EM01CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM01CTRL0 */ 253 #define _DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM01CTRL0 */ 254 #define _DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM01CTRL0 */ 255 #define _DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM01CTRL0 */ 256 #define DCDC_EM01CTRL0_DRVSPEED_DEFAULT (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM01CTRL0 */ 257 #define DCDC_EM01CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM01CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM01CTRL0 */ 258 #define DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM01CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM01CTRL0*/ 259 #define DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM01CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM01CTRL0*/ 260 #define DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM01CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM01CTRL0*/ 261 262 /* Bit fields for DCDC EM23CTRL0 */ 263 #define _DCDC_EM23CTRL0_RESETVALUE 0x00000103UL /**< Default value for DCDC_EM23CTRL0 */ 264 #define _DCDC_EM23CTRL0_MASK 0x0000030FUL /**< Mask for DCDC_EM23CTRL0 */ 265 #define _DCDC_EM23CTRL0_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 266 #define _DCDC_EM23CTRL0_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 267 #define _DCDC_EM23CTRL0_IPKVAL_DEFAULT 0x00000003UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ 268 #define _DCDC_EM23CTRL0_IPKVAL_Load5mA 0x00000003UL /**< Mode Load5mA for DCDC_EM23CTRL0 */ 269 #define _DCDC_EM23CTRL0_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_EM23CTRL0 */ 270 #define DCDC_EM23CTRL0_IPKVAL_DEFAULT (_DCDC_EM23CTRL0_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ 271 #define DCDC_EM23CTRL0_IPKVAL_Load5mA (_DCDC_EM23CTRL0_IPKVAL_Load5mA << 0) /**< Shifted mode Load5mA for DCDC_EM23CTRL0 */ 272 #define DCDC_EM23CTRL0_IPKVAL_Load10mA (_DCDC_EM23CTRL0_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_EM23CTRL0 */ 273 #define _DCDC_EM23CTRL0_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 274 #define _DCDC_EM23CTRL0_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 275 #define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_EM23CTRL0 */ 276 #define _DCDC_EM23CTRL0_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_EM23CTRL0 */ 277 #define _DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_EM23CTRL0 */ 278 #define _DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_EM23CTRL0 */ 279 #define _DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_EM23CTRL0 */ 280 #define DCDC_EM23CTRL0_DRVSPEED_DEFAULT (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_EM23CTRL0 */ 281 #define DCDC_EM23CTRL0_DRVSPEED_BEST_EMI (_DCDC_EM23CTRL0_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_EM23CTRL0 */ 282 #define DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING (_DCDC_EM23CTRL0_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_EM23CTRL0*/ 283 #define DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE (_DCDC_EM23CTRL0_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_EM23CTRL0*/ 284 #define DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY (_DCDC_EM23CTRL0_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_EM23CTRL0*/ 285 286 /* Bit fields for DCDC BSTCTRL */ 287 #define _DCDC_BSTCTRL_RESETVALUE 0x00000047UL /**< Default value for DCDC_BSTCTRL */ 288 #define _DCDC_BSTCTRL_MASK 0x00000077UL /**< Mask for DCDC_BSTCTRL */ 289 #define _DCDC_BSTCTRL_BSTTOFFMAX_SHIFT 0 /**< Shift value for DCDC_BSTTOFFMAX */ 290 #define _DCDC_BSTCTRL_BSTTOFFMAX_MASK 0x7UL /**< Bit mask for DCDC_BSTTOFFMAX */ 291 #define _DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT 0x00000007UL /**< Mode DEFAULT for DCDC_BSTCTRL */ 292 #define _DCDC_BSTCTRL_BSTTOFFMAX_OFF 0x00000000UL /**< Mode OFF for DCDC_BSTCTRL */ 293 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_BSTCTRL */ 294 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_BSTCTRL */ 295 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_BSTCTRL */ 296 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_BSTCTRL */ 297 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_BSTCTRL */ 298 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_BSTCTRL */ 299 #define _DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_BSTCTRL */ 300 #define DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT (_DCDC_BSTCTRL_BSTTOFFMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTCTRL */ 301 #define DCDC_BSTCTRL_BSTTOFFMAX_OFF (_DCDC_BSTCTRL_BSTTOFFMAX_OFF << 0) /**< Shifted mode OFF for DCDC_BSTCTRL */ 302 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P35us << 0) /**< Shifted mode TMAX_0P35us for DCDC_BSTCTRL */ 303 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P63us << 0) /**< Shifted mode TMAX_0P63us for DCDC_BSTCTRL */ 304 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_0P91us << 0) /**< Shifted mode TMAX_0P91us for DCDC_BSTCTRL */ 305 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P19us << 0) /**< Shifted mode TMAX_1P19us for DCDC_BSTCTRL */ 306 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P47us << 0) /**< Shifted mode TMAX_1P47us for DCDC_BSTCTRL */ 307 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_1P75us << 0) /**< Shifted mode TMAX_1P75us for DCDC_BSTCTRL */ 308 #define DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us (_DCDC_BSTCTRL_BSTTOFFMAX_TMAX_2P03us << 0) /**< Shifted mode TMAX_2P03us for DCDC_BSTCTRL */ 309 #define _DCDC_BSTCTRL_IPKTMAXCTRL_SHIFT 4 /**< Shift value for DCDC_IPKTMAXCTRL */ 310 #define _DCDC_BSTCTRL_IPKTMAXCTRL_MASK 0x70UL /**< Bit mask for DCDC_IPKTMAXCTRL */ 311 #define _DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT 0x00000004UL /**< Mode DEFAULT for DCDC_BSTCTRL */ 312 #define _DCDC_BSTCTRL_IPKTMAXCTRL_OFF 0x00000000UL /**< Mode OFF for DCDC_BSTCTRL */ 313 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us 0x00000001UL /**< Mode TMAX_0P35us for DCDC_BSTCTRL */ 314 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us 0x00000002UL /**< Mode TMAX_0P63us for DCDC_BSTCTRL */ 315 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us 0x00000003UL /**< Mode TMAX_0P91us for DCDC_BSTCTRL */ 316 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us 0x00000004UL /**< Mode TMAX_1P19us for DCDC_BSTCTRL */ 317 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us 0x00000005UL /**< Mode TMAX_1P47us for DCDC_BSTCTRL */ 318 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us 0x00000006UL /**< Mode TMAX_1P75us for DCDC_BSTCTRL */ 319 #define _DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us 0x00000007UL /**< Mode TMAX_2P03us for DCDC_BSTCTRL */ 320 #define DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT (_DCDC_BSTCTRL_IPKTMAXCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_BSTCTRL */ 321 #define DCDC_BSTCTRL_IPKTMAXCTRL_OFF (_DCDC_BSTCTRL_IPKTMAXCTRL_OFF << 4) /**< Shifted mode OFF for DCDC_BSTCTRL */ 322 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P35us << 4) /**< Shifted mode TMAX_0P35us for DCDC_BSTCTRL */ 323 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P63us << 4) /**< Shifted mode TMAX_0P63us for DCDC_BSTCTRL */ 324 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_0P91us << 4) /**< Shifted mode TMAX_0P91us for DCDC_BSTCTRL */ 325 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P19us << 4) /**< Shifted mode TMAX_1P19us for DCDC_BSTCTRL */ 326 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P47us << 4) /**< Shifted mode TMAX_1P47us for DCDC_BSTCTRL */ 327 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_1P75us << 4) /**< Shifted mode TMAX_1P75us for DCDC_BSTCTRL */ 328 #define DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us (_DCDC_BSTCTRL_IPKTMAXCTRL_TMAX_2P03us << 4) /**< Shifted mode TMAX_2P03us for DCDC_BSTCTRL */ 329 330 /* Bit fields for DCDC BSTEM01CTRL */ 331 #define _DCDC_BSTEM01CTRL_RESETVALUE 0x0000010CUL /**< Default value for DCDC_BSTEM01CTRL */ 332 #define _DCDC_BSTEM01CTRL_MASK 0x0000030FUL /**< Mask for DCDC_BSTEM01CTRL */ 333 #define _DCDC_BSTEM01CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 334 #define _DCDC_BSTEM01CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 335 #define _DCDC_BSTEM01CTRL_IPKVAL_DEFAULT 0x0000000CUL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ 336 #define _DCDC_BSTEM01CTRL_IPKVAL_Load10mA 0x00000003UL /**< Mode Load10mA for DCDC_BSTEM01CTRL */ 337 #define _DCDC_BSTEM01CTRL_IPKVAL_Load11mA 0x00000004UL /**< Mode Load11mA for DCDC_BSTEM01CTRL */ 338 #define _DCDC_BSTEM01CTRL_IPKVAL_Load13mA 0x00000005UL /**< Mode Load13mA for DCDC_BSTEM01CTRL */ 339 #define _DCDC_BSTEM01CTRL_IPKVAL_Load15mA 0x00000006UL /**< Mode Load15mA for DCDC_BSTEM01CTRL */ 340 #define _DCDC_BSTEM01CTRL_IPKVAL_Load16mA 0x00000007UL /**< Mode Load16mA for DCDC_BSTEM01CTRL */ 341 #define _DCDC_BSTEM01CTRL_IPKVAL_Load18mA 0x00000008UL /**< Mode Load18mA for DCDC_BSTEM01CTRL */ 342 #define _DCDC_BSTEM01CTRL_IPKVAL_Load20mA 0x00000009UL /**< Mode Load20mA for DCDC_BSTEM01CTRL */ 343 #define _DCDC_BSTEM01CTRL_IPKVAL_Load21mA 0x0000000AUL /**< Mode Load21mA for DCDC_BSTEM01CTRL */ 344 #define _DCDC_BSTEM01CTRL_IPKVAL_Load23mA 0x0000000BUL /**< Mode Load23mA for DCDC_BSTEM01CTRL */ 345 #define _DCDC_BSTEM01CTRL_IPKVAL_Load25mA 0x0000000CUL /**< Mode Load25mA for DCDC_BSTEM01CTRL */ 346 #define DCDC_BSTEM01CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM01CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ 347 #define DCDC_BSTEM01CTRL_IPKVAL_Load10mA (_DCDC_BSTEM01CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM01CTRL */ 348 #define DCDC_BSTEM01CTRL_IPKVAL_Load11mA (_DCDC_BSTEM01CTRL_IPKVAL_Load11mA << 0) /**< Shifted mode Load11mA for DCDC_BSTEM01CTRL */ 349 #define DCDC_BSTEM01CTRL_IPKVAL_Load13mA (_DCDC_BSTEM01CTRL_IPKVAL_Load13mA << 0) /**< Shifted mode Load13mA for DCDC_BSTEM01CTRL */ 350 #define DCDC_BSTEM01CTRL_IPKVAL_Load15mA (_DCDC_BSTEM01CTRL_IPKVAL_Load15mA << 0) /**< Shifted mode Load15mA for DCDC_BSTEM01CTRL */ 351 #define DCDC_BSTEM01CTRL_IPKVAL_Load16mA (_DCDC_BSTEM01CTRL_IPKVAL_Load16mA << 0) /**< Shifted mode Load16mA for DCDC_BSTEM01CTRL */ 352 #define DCDC_BSTEM01CTRL_IPKVAL_Load18mA (_DCDC_BSTEM01CTRL_IPKVAL_Load18mA << 0) /**< Shifted mode Load18mA for DCDC_BSTEM01CTRL */ 353 #define DCDC_BSTEM01CTRL_IPKVAL_Load20mA (_DCDC_BSTEM01CTRL_IPKVAL_Load20mA << 0) /**< Shifted mode Load20mA for DCDC_BSTEM01CTRL */ 354 #define DCDC_BSTEM01CTRL_IPKVAL_Load21mA (_DCDC_BSTEM01CTRL_IPKVAL_Load21mA << 0) /**< Shifted mode Load21mA for DCDC_BSTEM01CTRL */ 355 #define DCDC_BSTEM01CTRL_IPKVAL_Load23mA (_DCDC_BSTEM01CTRL_IPKVAL_Load23mA << 0) /**< Shifted mode Load23mA for DCDC_BSTEM01CTRL */ 356 #define DCDC_BSTEM01CTRL_IPKVAL_Load25mA (_DCDC_BSTEM01CTRL_IPKVAL_Load25mA << 0) /**< Shifted mode Load25mA for DCDC_BSTEM01CTRL */ 357 #define _DCDC_BSTEM01CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 358 #define _DCDC_BSTEM01CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 359 #define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM01CTRL */ 360 #define _DCDC_BSTEM01CTRL_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_BSTEM01CTRL */ 361 #define _DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_BSTEM01CTRL */ 362 #define _DCDC_BSTEM01CTRL_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_BSTEM01CTRL */ 363 #define _DCDC_BSTEM01CTRL_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_BSTEM01CTRL */ 364 #define DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT (_DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_BSTEM01CTRL */ 365 #define DCDC_BSTEM01CTRL_DRVSPEED_BEST_EMI (_DCDC_BSTEM01CTRL_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_BSTEM01CTRL */ 366 #define DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING (_DCDC_BSTEM01CTRL_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_BSTEM01CTRL*/ 367 #define DCDC_BSTEM01CTRL_DRVSPEED_INTERMEDIATE (_DCDC_BSTEM01CTRL_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_BSTEM01CTRL*/ 368 #define DCDC_BSTEM01CTRL_DRVSPEED_BEST_EFFICIENCY (_DCDC_BSTEM01CTRL_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_BSTEM01CTRL*/ 369 370 /* Bit fields for DCDC BSTEM23CTRL */ 371 #define _DCDC_BSTEM23CTRL_RESETVALUE 0x00000109UL /**< Default value for DCDC_BSTEM23CTRL */ 372 #define _DCDC_BSTEM23CTRL_MASK 0x0000030FUL /**< Mask for DCDC_BSTEM23CTRL */ 373 #define _DCDC_BSTEM23CTRL_IPKVAL_SHIFT 0 /**< Shift value for DCDC_IPKVAL */ 374 #define _DCDC_BSTEM23CTRL_IPKVAL_MASK 0xFUL /**< Bit mask for DCDC_IPKVAL */ 375 #define _DCDC_BSTEM23CTRL_IPKVAL_DEFAULT 0x00000009UL /**< Mode DEFAULT for DCDC_BSTEM23CTRL */ 376 #define _DCDC_BSTEM23CTRL_IPKVAL_Load10mA 0x00000009UL /**< Mode Load10mA for DCDC_BSTEM23CTRL */ 377 #define DCDC_BSTEM23CTRL_IPKVAL_DEFAULT (_DCDC_BSTEM23CTRL_IPKVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_BSTEM23CTRL */ 378 #define DCDC_BSTEM23CTRL_IPKVAL_Load10mA (_DCDC_BSTEM23CTRL_IPKVAL_Load10mA << 0) /**< Shifted mode Load10mA for DCDC_BSTEM23CTRL */ 379 #define _DCDC_BSTEM23CTRL_DRVSPEED_SHIFT 8 /**< Shift value for DCDC_DRVSPEED */ 380 #define _DCDC_BSTEM23CTRL_DRVSPEED_MASK 0x300UL /**< Bit mask for DCDC_DRVSPEED */ 381 #define _DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_BSTEM23CTRL */ 382 #define _DCDC_BSTEM23CTRL_DRVSPEED_BEST_EMI 0x00000000UL /**< Mode BEST_EMI for DCDC_BSTEM23CTRL */ 383 #define _DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING 0x00000001UL /**< Mode DEFAULT_SETTING for DCDC_BSTEM23CTRL */ 384 #define _DCDC_BSTEM23CTRL_DRVSPEED_INTERMEDIATE 0x00000002UL /**< Mode INTERMEDIATE for DCDC_BSTEM23CTRL */ 385 #define _DCDC_BSTEM23CTRL_DRVSPEED_BEST_EFFICIENCY 0x00000003UL /**< Mode BEST_EFFICIENCY for DCDC_BSTEM23CTRL */ 386 #define DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT (_DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_BSTEM23CTRL */ 387 #define DCDC_BSTEM23CTRL_DRVSPEED_BEST_EMI (_DCDC_BSTEM23CTRL_DRVSPEED_BEST_EMI << 8) /**< Shifted mode BEST_EMI for DCDC_BSTEM23CTRL */ 388 #define DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING (_DCDC_BSTEM23CTRL_DRVSPEED_DEFAULT_SETTING << 8) /**< Shifted mode DEFAULT_SETTING for DCDC_BSTEM23CTRL*/ 389 #define DCDC_BSTEM23CTRL_DRVSPEED_INTERMEDIATE (_DCDC_BSTEM23CTRL_DRVSPEED_INTERMEDIATE << 8) /**< Shifted mode INTERMEDIATE for DCDC_BSTEM23CTRL*/ 390 #define DCDC_BSTEM23CTRL_DRVSPEED_BEST_EFFICIENCY (_DCDC_BSTEM23CTRL_DRVSPEED_BEST_EFFICIENCY << 8) /**< Shifted mode BEST_EFFICIENCY for DCDC_BSTEM23CTRL*/ 391 392 /* Bit fields for DCDC IF */ 393 #define _DCDC_IF_RESETVALUE 0x00000000UL /**< Default value for DCDC_IF */ 394 #define _DCDC_IF_MASK 0x000000FFUL /**< Mask for DCDC_IF */ 395 #define DCDC_IF_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled */ 396 #define _DCDC_IF_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 397 #define _DCDC_IF_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 398 #define _DCDC_IF_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 399 #define DCDC_IF_BYPSW_DEFAULT (_DCDC_IF_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IF */ 400 #define DCDC_IF_WARM (0x1UL << 1) /**< DCDC Warmup Time Done */ 401 #define _DCDC_IF_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 402 #define _DCDC_IF_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 403 #define _DCDC_IF_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 404 #define DCDC_IF_WARM_DEFAULT (_DCDC_IF_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IF */ 405 #define DCDC_IF_RUNNING (0x1UL << 2) /**< DCDC Running */ 406 #define _DCDC_IF_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 407 #define _DCDC_IF_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 408 #define _DCDC_IF_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 409 #define DCDC_IF_RUNNING_DEFAULT (_DCDC_IF_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IF */ 410 #define DCDC_IF_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold */ 411 #define _DCDC_IF_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ 412 #define _DCDC_IF_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ 413 #define _DCDC_IF_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 414 #define DCDC_IF_VREGINLOW_DEFAULT (_DCDC_IF_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IF */ 415 #define DCDC_IF_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold */ 416 #define _DCDC_IF_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ 417 #define _DCDC_IF_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ 418 #define _DCDC_IF_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 419 #define DCDC_IF_VREGINHIGH_DEFAULT (_DCDC_IF_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IF */ 420 #define DCDC_IF_REGULATION (0x1UL << 5) /**< DCDC in regulation */ 421 #define _DCDC_IF_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ 422 #define _DCDC_IF_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ 423 #define _DCDC_IF_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 424 #define DCDC_IF_REGULATION_DEFAULT (_DCDC_IF_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IF */ 425 #define DCDC_IF_TMAX (0x1UL << 6) /**< Buck Max Ton/Boost Max Toff reached */ 426 #define _DCDC_IF_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ 427 #define _DCDC_IF_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ 428 #define _DCDC_IF_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 429 #define DCDC_IF_TMAX_DEFAULT (_DCDC_IF_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IF */ 430 #define DCDC_IF_EM4ERR (0x1UL << 7) /**< EM4 Entry Request Error */ 431 #define _DCDC_IF_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ 432 #define _DCDC_IF_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ 433 #define _DCDC_IF_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IF */ 434 #define DCDC_IF_EM4ERR_DEFAULT (_DCDC_IF_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IF */ 435 436 /* Bit fields for DCDC IEN */ 437 #define _DCDC_IEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_IEN */ 438 #define _DCDC_IEN_MASK 0x000000FFUL /**< Mask for DCDC_IEN */ 439 #define DCDC_IEN_BYPSW (0x1UL << 0) /**< Bypass Switch Enabled Interrupt Enable */ 440 #define _DCDC_IEN_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 441 #define _DCDC_IEN_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 442 #define _DCDC_IEN_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 443 #define DCDC_IEN_BYPSW_DEFAULT (_DCDC_IEN_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_IEN */ 444 #define DCDC_IEN_WARM (0x1UL << 1) /**< DCDC Warmup Time Done Interrupt Enable */ 445 #define _DCDC_IEN_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 446 #define _DCDC_IEN_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 447 #define _DCDC_IEN_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 448 #define DCDC_IEN_WARM_DEFAULT (_DCDC_IEN_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_IEN */ 449 #define DCDC_IEN_RUNNING (0x1UL << 2) /**< DCDC Running Interrupt Enable */ 450 #define _DCDC_IEN_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 451 #define _DCDC_IEN_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 452 #define _DCDC_IEN_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 453 #define DCDC_IEN_RUNNING_DEFAULT (_DCDC_IEN_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_IEN */ 454 #define DCDC_IEN_VREGINLOW (0x1UL << 3) /**< VREGVDD below threshold Interrupt Enable */ 455 #define _DCDC_IEN_VREGINLOW_SHIFT 3 /**< Shift value for DCDC_VREGINLOW */ 456 #define _DCDC_IEN_VREGINLOW_MASK 0x8UL /**< Bit mask for DCDC_VREGINLOW */ 457 #define _DCDC_IEN_VREGINLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 458 #define DCDC_IEN_VREGINLOW_DEFAULT (_DCDC_IEN_VREGINLOW_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_IEN */ 459 #define DCDC_IEN_VREGINHIGH (0x1UL << 4) /**< VREGVDD above threshold Interrupt Enable */ 460 #define _DCDC_IEN_VREGINHIGH_SHIFT 4 /**< Shift value for DCDC_VREGINHIGH */ 461 #define _DCDC_IEN_VREGINHIGH_MASK 0x10UL /**< Bit mask for DCDC_VREGINHIGH */ 462 #define _DCDC_IEN_VREGINHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 463 #define DCDC_IEN_VREGINHIGH_DEFAULT (_DCDC_IEN_VREGINHIGH_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_IEN */ 464 #define DCDC_IEN_REGULATION (0x1UL << 5) /**< DCDC in Regulation Interrupt Enable */ 465 #define _DCDC_IEN_REGULATION_SHIFT 5 /**< Shift value for DCDC_REGULATION */ 466 #define _DCDC_IEN_REGULATION_MASK 0x20UL /**< Bit mask for DCDC_REGULATION */ 467 #define _DCDC_IEN_REGULATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 468 #define DCDC_IEN_REGULATION_DEFAULT (_DCDC_IEN_REGULATION_DEFAULT << 5) /**< Shifted mode DEFAULT for DCDC_IEN */ 469 #define DCDC_IEN_TMAX (0x1UL << 6) /**< Ton_max Timeout Interrupt Enable */ 470 #define _DCDC_IEN_TMAX_SHIFT 6 /**< Shift value for DCDC_TMAX */ 471 #define _DCDC_IEN_TMAX_MASK 0x40UL /**< Bit mask for DCDC_TMAX */ 472 #define _DCDC_IEN_TMAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 473 #define DCDC_IEN_TMAX_DEFAULT (_DCDC_IEN_TMAX_DEFAULT << 6) /**< Shifted mode DEFAULT for DCDC_IEN */ 474 #define DCDC_IEN_EM4ERR (0x1UL << 7) /**< EM4 Entry Req Interrupt Enable */ 475 #define _DCDC_IEN_EM4ERR_SHIFT 7 /**< Shift value for DCDC_EM4ERR */ 476 #define _DCDC_IEN_EM4ERR_MASK 0x80UL /**< Bit mask for DCDC_EM4ERR */ 477 #define _DCDC_IEN_EM4ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_IEN */ 478 #define DCDC_IEN_EM4ERR_DEFAULT (_DCDC_IEN_EM4ERR_DEFAULT << 7) /**< Shifted mode DEFAULT for DCDC_IEN */ 479 480 /* Bit fields for DCDC STATUS */ 481 #define _DCDC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_STATUS */ 482 #define _DCDC_STATUS_MASK 0x0000001FUL /**< Mask for DCDC_STATUS */ 483 #define DCDC_STATUS_BYPSW (0x1UL << 0) /**< Bypass Switch is currently enabled */ 484 #define _DCDC_STATUS_BYPSW_SHIFT 0 /**< Shift value for DCDC_BYPSW */ 485 #define _DCDC_STATUS_BYPSW_MASK 0x1UL /**< Bit mask for DCDC_BYPSW */ 486 #define _DCDC_STATUS_BYPSW_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 487 #define DCDC_STATUS_BYPSW_DEFAULT (_DCDC_STATUS_BYPSW_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_STATUS */ 488 #define DCDC_STATUS_WARM (0x1UL << 1) /**< DCDC Warmup Done */ 489 #define _DCDC_STATUS_WARM_SHIFT 1 /**< Shift value for DCDC_WARM */ 490 #define _DCDC_STATUS_WARM_MASK 0x2UL /**< Bit mask for DCDC_WARM */ 491 #define _DCDC_STATUS_WARM_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 492 #define DCDC_STATUS_WARM_DEFAULT (_DCDC_STATUS_WARM_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_STATUS */ 493 #define DCDC_STATUS_RUNNING (0x1UL << 2) /**< DCDC is running */ 494 #define _DCDC_STATUS_RUNNING_SHIFT 2 /**< Shift value for DCDC_RUNNING */ 495 #define _DCDC_STATUS_RUNNING_MASK 0x4UL /**< Bit mask for DCDC_RUNNING */ 496 #define _DCDC_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 497 #define DCDC_STATUS_RUNNING_DEFAULT (_DCDC_STATUS_RUNNING_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_STATUS */ 498 #define DCDC_STATUS_VREGIN (0x1UL << 3) /**< VREGVDD comparator status */ 499 #define _DCDC_STATUS_VREGIN_SHIFT 3 /**< Shift value for DCDC_VREGIN */ 500 #define _DCDC_STATUS_VREGIN_MASK 0x8UL /**< Bit mask for DCDC_VREGIN */ 501 #define _DCDC_STATUS_VREGIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 502 #define DCDC_STATUS_VREGIN_DEFAULT (_DCDC_STATUS_VREGIN_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_STATUS */ 503 #define DCDC_STATUS_BYPCMPOUT (0x1UL << 4) /**< Bypass Comparator Output */ 504 #define _DCDC_STATUS_BYPCMPOUT_SHIFT 4 /**< Shift value for DCDC_BYPCMPOUT */ 505 #define _DCDC_STATUS_BYPCMPOUT_MASK 0x10UL /**< Bit mask for DCDC_BYPCMPOUT */ 506 #define _DCDC_STATUS_BYPCMPOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_STATUS */ 507 #define DCDC_STATUS_BYPCMPOUT_DEFAULT (_DCDC_STATUS_BYPCMPOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for DCDC_STATUS */ 508 509 /* Bit fields for DCDC SYNCBUSY */ 510 #define _DCDC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for DCDC_SYNCBUSY */ 511 #define _DCDC_SYNCBUSY_MASK 0x00000001UL /**< Mask for DCDC_SYNCBUSY */ 512 #define DCDC_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< Combined Sync Busy Status */ 513 #define _DCDC_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for DCDC_SYNCBUSY */ 514 #define _DCDC_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for DCDC_SYNCBUSY */ 515 #define _DCDC_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_SYNCBUSY */ 516 #define DCDC_SYNCBUSY_SYNCBUSY_DEFAULT (_DCDC_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_SYNCBUSY */ 517 518 /* Bit fields for DCDC CCCTRL */ 519 #define _DCDC_CCCTRL_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCTRL */ 520 #define _DCDC_CCCTRL_MASK 0x00000001UL /**< Mask for DCDC_CCCTRL */ 521 #define DCDC_CCCTRL_CCEN (0x1UL << 0) /**< Coulomb Counter Enable */ 522 #define _DCDC_CCCTRL_CCEN_SHIFT 0 /**< Shift value for DCDC_CCEN */ 523 #define _DCDC_CCCTRL_CCEN_MASK 0x1UL /**< Bit mask for DCDC_CCEN */ 524 #define _DCDC_CCCTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCTRL */ 525 #define DCDC_CCCTRL_CCEN_DEFAULT (_DCDC_CCCTRL_CCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCTRL */ 526 527 /* Bit fields for DCDC CCCALCTRL */ 528 #define _DCDC_CCCALCTRL_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCALCTRL */ 529 #define _DCDC_CCCALCTRL_MASK 0x0000030FUL /**< Mask for DCDC_CCCALCTRL */ 530 #define DCDC_CCCALCTRL_CCLOADEN (0x1UL << 0) /**< CC Load Circuit Enable */ 531 #define _DCDC_CCCALCTRL_CCLOADEN_SHIFT 0 /**< Shift value for DCDC_CCLOADEN */ 532 #define _DCDC_CCCALCTRL_CCLOADEN_MASK 0x1UL /**< Bit mask for DCDC_CCLOADEN */ 533 #define _DCDC_CCCALCTRL_CCLOADEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ 534 #define DCDC_CCCALCTRL_CCLOADEN_DEFAULT (_DCDC_CCCALCTRL_CCLOADEN_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ 535 #define _DCDC_CCCALCTRL_CCLVL_SHIFT 1 /**< Shift value for DCDC_CCLVL */ 536 #define _DCDC_CCCALCTRL_CCLVL_MASK 0xEUL /**< Bit mask for DCDC_CCLVL */ 537 #define _DCDC_CCCALCTRL_CCLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ 538 #define _DCDC_CCCALCTRL_CCLVL_LOAD0 0x00000000UL /**< Mode LOAD0 for DCDC_CCCALCTRL */ 539 #define _DCDC_CCCALCTRL_CCLVL_LOAD1 0x00000001UL /**< Mode LOAD1 for DCDC_CCCALCTRL */ 540 #define _DCDC_CCCALCTRL_CCLVL_LOAD2 0x00000002UL /**< Mode LOAD2 for DCDC_CCCALCTRL */ 541 #define _DCDC_CCCALCTRL_CCLVL_LOAD3 0x00000003UL /**< Mode LOAD3 for DCDC_CCCALCTRL */ 542 #define _DCDC_CCCALCTRL_CCLVL_LOAD4 0x00000004UL /**< Mode LOAD4 for DCDC_CCCALCTRL */ 543 #define _DCDC_CCCALCTRL_CCLVL_LOAD5 0x00000005UL /**< Mode LOAD5 for DCDC_CCCALCTRL */ 544 #define _DCDC_CCCALCTRL_CCLVL_LOAD6 0x00000006UL /**< Mode LOAD6 for DCDC_CCCALCTRL */ 545 #define _DCDC_CCCALCTRL_CCLVL_LOAD7 0x00000007UL /**< Mode LOAD7 for DCDC_CCCALCTRL */ 546 #define DCDC_CCCALCTRL_CCLVL_DEFAULT (_DCDC_CCCALCTRL_CCLVL_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ 547 #define DCDC_CCCALCTRL_CCLVL_LOAD0 (_DCDC_CCCALCTRL_CCLVL_LOAD0 << 1) /**< Shifted mode LOAD0 for DCDC_CCCALCTRL */ 548 #define DCDC_CCCALCTRL_CCLVL_LOAD1 (_DCDC_CCCALCTRL_CCLVL_LOAD1 << 1) /**< Shifted mode LOAD1 for DCDC_CCCALCTRL */ 549 #define DCDC_CCCALCTRL_CCLVL_LOAD2 (_DCDC_CCCALCTRL_CCLVL_LOAD2 << 1) /**< Shifted mode LOAD2 for DCDC_CCCALCTRL */ 550 #define DCDC_CCCALCTRL_CCLVL_LOAD3 (_DCDC_CCCALCTRL_CCLVL_LOAD3 << 1) /**< Shifted mode LOAD3 for DCDC_CCCALCTRL */ 551 #define DCDC_CCCALCTRL_CCLVL_LOAD4 (_DCDC_CCCALCTRL_CCLVL_LOAD4 << 1) /**< Shifted mode LOAD4 for DCDC_CCCALCTRL */ 552 #define DCDC_CCCALCTRL_CCLVL_LOAD5 (_DCDC_CCCALCTRL_CCLVL_LOAD5 << 1) /**< Shifted mode LOAD5 for DCDC_CCCALCTRL */ 553 #define DCDC_CCCALCTRL_CCLVL_LOAD6 (_DCDC_CCCALCTRL_CCLVL_LOAD6 << 1) /**< Shifted mode LOAD6 for DCDC_CCCALCTRL */ 554 #define DCDC_CCCALCTRL_CCLVL_LOAD7 (_DCDC_CCCALCTRL_CCLVL_LOAD7 << 1) /**< Shifted mode LOAD7 for DCDC_CCCALCTRL */ 555 #define DCDC_CCCALCTRL_CCCALEM2 (0x1UL << 8) /**< CC Calibrate EM2 */ 556 #define _DCDC_CCCALCTRL_CCCALEM2_SHIFT 8 /**< Shift value for DCDC_CCCALEM2 */ 557 #define _DCDC_CCCALCTRL_CCCALEM2_MASK 0x100UL /**< Bit mask for DCDC_CCCALEM2 */ 558 #define _DCDC_CCCALCTRL_CCCALEM2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ 559 #define DCDC_CCCALCTRL_CCCALEM2_DEFAULT (_DCDC_CCCALCTRL_CCCALEM2_DEFAULT << 8) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ 560 #define DCDC_CCCALCTRL_CCCALHALT (0x1UL << 9) /**< CC Calibration Halt Req */ 561 #define _DCDC_CCCALCTRL_CCCALHALT_SHIFT 9 /**< Shift value for DCDC_CCCALHALT */ 562 #define _DCDC_CCCALCTRL_CCCALHALT_MASK 0x200UL /**< Bit mask for DCDC_CCCALHALT */ 563 #define _DCDC_CCCALCTRL_CCCALHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCALCTRL */ 564 #define DCDC_CCCALCTRL_CCCALHALT_DEFAULT (_DCDC_CCCALCTRL_CCCALHALT_DEFAULT << 9) /**< Shifted mode DEFAULT for DCDC_CCCALCTRL */ 565 566 /* Bit fields for DCDC CCCMD */ 567 #define _DCDC_CCCMD_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCCMD */ 568 #define _DCDC_CCCMD_MASK 0x00000007UL /**< Mask for DCDC_CCCMD */ 569 #define DCDC_CCCMD_START (0x1UL << 0) /**< Start CC */ 570 #define _DCDC_CCCMD_START_SHIFT 0 /**< Shift value for DCDC_START */ 571 #define _DCDC_CCCMD_START_MASK 0x1UL /**< Bit mask for DCDC_START */ 572 #define _DCDC_CCCMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ 573 #define DCDC_CCCMD_START_DEFAULT (_DCDC_CCCMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCCMD */ 574 #define DCDC_CCCMD_STOP (0x1UL << 1) /**< Stop CC */ 575 #define _DCDC_CCCMD_STOP_SHIFT 1 /**< Shift value for DCDC_STOP */ 576 #define _DCDC_CCCMD_STOP_MASK 0x2UL /**< Bit mask for DCDC_STOP */ 577 #define _DCDC_CCCMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ 578 #define DCDC_CCCMD_STOP_DEFAULT (_DCDC_CCCMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCCMD */ 579 #define DCDC_CCCMD_CLR (0x1UL << 2) /**< Clear CC */ 580 #define _DCDC_CCCMD_CLR_SHIFT 2 /**< Shift value for DCDC_CLR */ 581 #define _DCDC_CCCMD_CLR_MASK 0x4UL /**< Bit mask for DCDC_CLR */ 582 #define _DCDC_CCCMD_CLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCCMD */ 583 #define DCDC_CCCMD_CLR_DEFAULT (_DCDC_CCCMD_CLR_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCCMD */ 584 585 /* Bit fields for DCDC CCEM0CNT */ 586 #define _DCDC_CCEM0CNT_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCEM0CNT */ 587 #define _DCDC_CCEM0CNT_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCEM0CNT */ 588 #define _DCDC_CCEM0CNT_CCCNT_SHIFT 0 /**< Shift value for DCDC_CCCNT */ 589 #define _DCDC_CCEM0CNT_CCCNT_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_CCCNT */ 590 #define _DCDC_CCEM0CNT_CCCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCEM0CNT */ 591 #define DCDC_CCEM0CNT_CCCNT_DEFAULT (_DCDC_CCEM0CNT_CCCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCEM0CNT */ 592 593 /* Bit fields for DCDC CCEM2CNT */ 594 #define _DCDC_CCEM2CNT_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCEM2CNT */ 595 #define _DCDC_CCEM2CNT_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCEM2CNT */ 596 #define _DCDC_CCEM2CNT_CCCNT_SHIFT 0 /**< Shift value for DCDC_CCCNT */ 597 #define _DCDC_CCEM2CNT_CCCNT_MASK 0xFFFFFFFFUL /**< Bit mask for DCDC_CCCNT */ 598 #define _DCDC_CCEM2CNT_CCCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCEM2CNT */ 599 #define DCDC_CCEM2CNT_CCCNT_DEFAULT (_DCDC_CCEM2CNT_CCCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCEM2CNT */ 600 601 /* Bit fields for DCDC CCTHR */ 602 #define _DCDC_CCTHR_RESETVALUE 0x00010001UL /**< Default value for DCDC_CCTHR */ 603 #define _DCDC_CCTHR_MASK 0xFFFFFFFFUL /**< Mask for DCDC_CCTHR */ 604 #define _DCDC_CCTHR_EM0CNT_SHIFT 0 /**< Shift value for DCDC_EM0CNT */ 605 #define _DCDC_CCTHR_EM0CNT_MASK 0xFFFFUL /**< Bit mask for DCDC_EM0CNT */ 606 #define _DCDC_CCTHR_EM0CNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CCTHR */ 607 #define DCDC_CCTHR_EM0CNT_DEFAULT (_DCDC_CCTHR_EM0CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCTHR */ 608 #define _DCDC_CCTHR_EM2CNT_SHIFT 16 /**< Shift value for DCDC_EM2CNT */ 609 #define _DCDC_CCTHR_EM2CNT_MASK 0xFFFF0000UL /**< Bit mask for DCDC_EM2CNT */ 610 #define _DCDC_CCTHR_EM2CNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for DCDC_CCTHR */ 611 #define DCDC_CCTHR_EM2CNT_DEFAULT (_DCDC_CCTHR_EM2CNT_DEFAULT << 16) /**< Shifted mode DEFAULT for DCDC_CCTHR */ 612 613 /* Bit fields for DCDC CCIF */ 614 #define _DCDC_CCIF_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCIF */ 615 #define _DCDC_CCIF_MASK 0x0000000FUL /**< Mask for DCDC_CCIF */ 616 #define DCDC_CCIF_EM0OF (0x1UL << 0) /**< EM0 Counter Overflow */ 617 #define _DCDC_CCIF_EM0OF_SHIFT 0 /**< Shift value for DCDC_EM0OF */ 618 #define _DCDC_CCIF_EM0OF_MASK 0x1UL /**< Bit mask for DCDC_EM0OF */ 619 #define _DCDC_CCIF_EM0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ 620 #define DCDC_CCIF_EM0OF_DEFAULT (_DCDC_CCIF_EM0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCIF */ 621 #define DCDC_CCIF_EM2OF (0x1UL << 1) /**< EM2 Counter Overflow */ 622 #define _DCDC_CCIF_EM2OF_SHIFT 1 /**< Shift value for DCDC_EM2OF */ 623 #define _DCDC_CCIF_EM2OF_MASK 0x2UL /**< Bit mask for DCDC_EM2OF */ 624 #define _DCDC_CCIF_EM2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ 625 #define DCDC_CCIF_EM2OF_DEFAULT (_DCDC_CCIF_EM2OF_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCIF */ 626 #define DCDC_CCIF_EM0CMP (0x1UL << 2) /**< EM0 Counter Compare Match */ 627 #define _DCDC_CCIF_EM0CMP_SHIFT 2 /**< Shift value for DCDC_EM0CMP */ 628 #define _DCDC_CCIF_EM0CMP_MASK 0x4UL /**< Bit mask for DCDC_EM0CMP */ 629 #define _DCDC_CCIF_EM0CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ 630 #define DCDC_CCIF_EM0CMP_DEFAULT (_DCDC_CCIF_EM0CMP_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCIF */ 631 #define DCDC_CCIF_EM2CMP (0x1UL << 3) /**< EM2 Counter Compare Match */ 632 #define _DCDC_CCIF_EM2CMP_SHIFT 3 /**< Shift value for DCDC_EM2CMP */ 633 #define _DCDC_CCIF_EM2CMP_MASK 0x8UL /**< Bit mask for DCDC_EM2CMP */ 634 #define _DCDC_CCIF_EM2CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIF */ 635 #define DCDC_CCIF_EM2CMP_DEFAULT (_DCDC_CCIF_EM2CMP_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_CCIF */ 636 637 /* Bit fields for DCDC CCIEN */ 638 #define _DCDC_CCIEN_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCIEN */ 639 #define _DCDC_CCIEN_MASK 0x0000000FUL /**< Mask for DCDC_CCIEN */ 640 #define DCDC_CCIEN_EM0OF (0x1UL << 0) /**< Clmb Cntr EM0 Overflow Interrupt Enable */ 641 #define _DCDC_CCIEN_EM0OF_SHIFT 0 /**< Shift value for DCDC_EM0OF */ 642 #define _DCDC_CCIEN_EM0OF_MASK 0x1UL /**< Bit mask for DCDC_EM0OF */ 643 #define _DCDC_CCIEN_EM0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ 644 #define DCDC_CCIEN_EM0OF_DEFAULT (_DCDC_CCIEN_EM0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCIEN */ 645 #define DCDC_CCIEN_EM2OF (0x1UL << 1) /**< Clmb Cntr EM2 Overflow Interrupt Enable */ 646 #define _DCDC_CCIEN_EM2OF_SHIFT 1 /**< Shift value for DCDC_EM2OF */ 647 #define _DCDC_CCIEN_EM2OF_MASK 0x2UL /**< Bit mask for DCDC_EM2OF */ 648 #define _DCDC_CCIEN_EM2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ 649 #define DCDC_CCIEN_EM2OF_DEFAULT (_DCDC_CCIEN_EM2OF_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCIEN */ 650 #define DCDC_CCIEN_EM0CMP (0x1UL << 2) /**< Clmb Cntr EM0 Cmp Match Interrupt Enable */ 651 #define _DCDC_CCIEN_EM0CMP_SHIFT 2 /**< Shift value for DCDC_EM0CMP */ 652 #define _DCDC_CCIEN_EM0CMP_MASK 0x4UL /**< Bit mask for DCDC_EM0CMP */ 653 #define _DCDC_CCIEN_EM0CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ 654 #define DCDC_CCIEN_EM0CMP_DEFAULT (_DCDC_CCIEN_EM0CMP_DEFAULT << 2) /**< Shifted mode DEFAULT for DCDC_CCIEN */ 655 #define DCDC_CCIEN_EM2CMP (0x1UL << 3) /**< Clmb Cntr EM2 Cmp Match Interrupt Enable */ 656 #define _DCDC_CCIEN_EM2CMP_SHIFT 3 /**< Shift value for DCDC_EM2CMP */ 657 #define _DCDC_CCIEN_EM2CMP_MASK 0x8UL /**< Bit mask for DCDC_EM2CMP */ 658 #define _DCDC_CCIEN_EM2CMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCIEN */ 659 #define DCDC_CCIEN_EM2CMP_DEFAULT (_DCDC_CCIEN_EM2CMP_DEFAULT << 3) /**< Shifted mode DEFAULT for DCDC_CCIEN */ 660 661 /* Bit fields for DCDC CCSTATUS */ 662 #define _DCDC_CCSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_CCSTATUS */ 663 #define _DCDC_CCSTATUS_MASK 0x00000003UL /**< Mask for DCDC_CCSTATUS */ 664 #define DCDC_CCSTATUS_CLRBSY (0x1UL << 0) /**< Coulomb Counter Clear Busy */ 665 #define _DCDC_CCSTATUS_CLRBSY_SHIFT 0 /**< Shift value for DCDC_CLRBSY */ 666 #define _DCDC_CCSTATUS_CLRBSY_MASK 0x1UL /**< Bit mask for DCDC_CLRBSY */ 667 #define _DCDC_CCSTATUS_CLRBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCSTATUS */ 668 #define DCDC_CCSTATUS_CLRBSY_DEFAULT (_DCDC_CCSTATUS_CLRBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_CCSTATUS */ 669 #define DCDC_CCSTATUS_CCRUNNING (0x1UL << 1) /**< Coulomb Counter Running */ 670 #define _DCDC_CCSTATUS_CCRUNNING_SHIFT 1 /**< Shift value for DCDC_CCRUNNING */ 671 #define _DCDC_CCSTATUS_CCRUNNING_MASK 0x2UL /**< Bit mask for DCDC_CCRUNNING */ 672 #define _DCDC_CCSTATUS_CCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_CCSTATUS */ 673 #define DCDC_CCSTATUS_CCRUNNING_DEFAULT (_DCDC_CCSTATUS_CCRUNNING_DEFAULT << 1) /**< Shifted mode DEFAULT for DCDC_CCSTATUS */ 674 675 /* Bit fields for DCDC LOCK */ 676 #define _DCDC_LOCK_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCK */ 677 #define _DCDC_LOCK_MASK 0x0000FFFFUL /**< Mask for DCDC_LOCK */ 678 #define _DCDC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for DCDC_LOCKKEY */ 679 #define _DCDC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for DCDC_LOCKKEY */ 680 #define _DCDC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCK */ 681 #define _DCDC_LOCK_LOCKKEY_UNLOCKKEY 0x0000ABCDUL /**< Mode UNLOCKKEY for DCDC_LOCK */ 682 #define DCDC_LOCK_LOCKKEY_DEFAULT (_DCDC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCK */ 683 #define DCDC_LOCK_LOCKKEY_UNLOCKKEY (_DCDC_LOCK_LOCKKEY_UNLOCKKEY << 0) /**< Shifted mode UNLOCKKEY for DCDC_LOCK */ 684 685 /* Bit fields for DCDC LOCKSTATUS */ 686 #define _DCDC_LOCKSTATUS_RESETVALUE 0x00000000UL /**< Default value for DCDC_LOCKSTATUS */ 687 #define _DCDC_LOCKSTATUS_MASK 0x00000001UL /**< Mask for DCDC_LOCKSTATUS */ 688 #define DCDC_LOCKSTATUS_LOCK (0x1UL << 0) /**< Lock Status */ 689 #define _DCDC_LOCKSTATUS_LOCK_SHIFT 0 /**< Shift value for DCDC_LOCK */ 690 #define _DCDC_LOCKSTATUS_LOCK_MASK 0x1UL /**< Bit mask for DCDC_LOCK */ 691 #define _DCDC_LOCKSTATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for DCDC_LOCKSTATUS */ 692 #define _DCDC_LOCKSTATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for DCDC_LOCKSTATUS */ 693 #define _DCDC_LOCKSTATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for DCDC_LOCKSTATUS */ 694 #define DCDC_LOCKSTATUS_LOCK_DEFAULT (_DCDC_LOCKSTATUS_LOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for DCDC_LOCKSTATUS */ 695 #define DCDC_LOCKSTATUS_LOCK_UNLOCKED (_DCDC_LOCKSTATUS_LOCK_UNLOCKED << 0) /**< Shifted mode UNLOCKED for DCDC_LOCKSTATUS */ 696 #define DCDC_LOCKSTATUS_LOCK_LOCKED (_DCDC_LOCKSTATUS_LOCK_LOCKED << 0) /**< Shifted mode LOCKED for DCDC_LOCKSTATUS */ 697 698 /** @} End of group EFR32BG27_DCDC_BitFields */ 699 /** @} End of group EFR32BG27_DCDC */ 700 /** @} End of group Parts */ 701 702 #endif /* EFR32BG27_DCDC_H */ 703
