1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG21 AES register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG21_AES_H 31 #define EFR32MG21_AES_H 32 33 /**************************************************************************//** 34 * @addtogroup Parts 35 * @{ 36 ******************************************************************************/ 37 /**************************************************************************//** 38 * @defgroup EFR32MG21_AES AES 39 * @{ 40 * @brief EFR32MG21 AES Register Declaration. 41 *****************************************************************************/ 42 43 /** AES Register Declaration. */ 44 typedef struct { 45 __IOM uint32_t FETCHADDR; /**< Fetcher Address */ 46 __IOM uint32_t FETCHDESCR; /**< Fetcher Descriptor */ 47 __IOM uint32_t FETCHLEN; /**< Fetcher Length */ 48 __IOM uint32_t FETCHTAG; /**< Fetcher Tag */ 49 __IOM uint32_t PUSHADDR; /**< Pusher Address */ 50 __IOM uint32_t PUSHDESCR; /**< Pusher Descriptor */ 51 __IOM uint32_t PUSHLEN; /**< Pusher Length */ 52 __IOM uint32_t IEN; /**< Interrupt Enable */ 53 uint32_t RESERVED0[2U]; /**< Reserved for future use */ 54 __IM uint32_t IF; /**< Interrupt Flags */ 55 uint32_t RESERVED1[1U]; /**< Reserved for future use */ 56 __IOM uint32_t IFC; /**< Interrupt status clear */ 57 __IOM uint32_t CTRL; /**< Control register */ 58 __IOM uint32_t CMD; /**< Command register */ 59 __IM uint32_t STATUS; /**< Status register */ 60 uint32_t RESERVED2[4079U]; /**< Reserved for future use */ 61 uint32_t RESERVED3[1U]; /**< Reserved for future use */ 62 } AES_TypeDef; 63 /** @} End of group EFR32MG21_AES */ 64 65 /**************************************************************************//** 66 * @addtogroup EFR32MG21_AES 67 * @{ 68 * @defgroup EFR32MG21_AES_BitFields AES Bit Fields 69 * @{ 70 *****************************************************************************/ 71 72 /* Bit fields for AES FETCHADDR */ 73 #define _AES_FETCHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHADDR */ 74 #define _AES_FETCHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHADDR */ 75 #define _AES_FETCHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ 76 #define _AES_FETCHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ 77 #define _AES_FETCHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHADDR */ 78 #define AES_FETCHADDR_ADDR_DEFAULT (_AES_FETCHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHADDR */ 79 80 /* Bit fields for AES FETCHDESCR */ 81 #define _AES_FETCHDESCR_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHDESCR */ 82 #define _AES_FETCHDESCR_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHDESCR */ 83 #define _AES_FETCHDESCR_DESCR_SHIFT 0 /**< Shift value for AES_DESCR */ 84 #define _AES_FETCHDESCR_DESCR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DESCR */ 85 #define _AES_FETCHDESCR_DESCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHDESCR */ 86 #define AES_FETCHDESCR_DESCR_DEFAULT (_AES_FETCHDESCR_DESCR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHDESCR */ 87 88 /* Bit fields for AES FETCHLEN */ 89 #define _AES_FETCHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHLEN */ 90 #define _AES_FETCHLEN_MASK 0x3FFFFFFFUL /**< Mask for AES_FETCHLEN */ 91 #define _AES_FETCHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ 92 #define _AES_FETCHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ 93 #define _AES_FETCHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ 94 #define AES_FETCHLEN_LENGTH_DEFAULT (_AES_FETCHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHLEN */ 95 #define AES_FETCHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ 96 #define _AES_FETCHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ 97 #define _AES_FETCHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ 98 #define _AES_FETCHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ 99 #define AES_FETCHLEN_CONSTADDR_DEFAULT (_AES_FETCHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_FETCHLEN */ 100 #define AES_FETCHLEN_REALIGN (0x1UL << 29) /**< Realign lengh */ 101 #define _AES_FETCHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ 102 #define _AES_FETCHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ 103 #define _AES_FETCHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHLEN */ 104 #define AES_FETCHLEN_REALIGN_DEFAULT (_AES_FETCHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_FETCHLEN */ 105 106 /* Bit fields for AES FETCHTAG */ 107 #define _AES_FETCHTAG_RESETVALUE 0x00000000UL /**< Default value for AES_FETCHTAG */ 108 #define _AES_FETCHTAG_MASK 0xFFFFFFFFUL /**< Mask for AES_FETCHTAG */ 109 #define _AES_FETCHTAG_TAG_SHIFT 0 /**< Shift value for AES_TAG */ 110 #define _AES_FETCHTAG_TAG_MASK 0xFFFFFFFFUL /**< Bit mask for AES_TAG */ 111 #define _AES_FETCHTAG_TAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_FETCHTAG */ 112 #define AES_FETCHTAG_TAG_DEFAULT (_AES_FETCHTAG_TAG_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_FETCHTAG */ 113 114 /* Bit fields for AES PUSHADDR */ 115 #define _AES_PUSHADDR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHADDR */ 116 #define _AES_PUSHADDR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHADDR */ 117 #define _AES_PUSHADDR_ADDR_SHIFT 0 /**< Shift value for AES_ADDR */ 118 #define _AES_PUSHADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_ADDR */ 119 #define _AES_PUSHADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHADDR */ 120 #define AES_PUSHADDR_ADDR_DEFAULT (_AES_PUSHADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHADDR */ 121 122 /* Bit fields for AES PUSHDESCR */ 123 #define _AES_PUSHDESCR_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHDESCR */ 124 #define _AES_PUSHDESCR_MASK 0xFFFFFFFFUL /**< Mask for AES_PUSHDESCR */ 125 #define _AES_PUSHDESCR_DESCR_SHIFT 0 /**< Shift value for AES_DESCR */ 126 #define _AES_PUSHDESCR_DESCR_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DESCR */ 127 #define _AES_PUSHDESCR_DESCR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHDESCR */ 128 #define AES_PUSHDESCR_DESCR_DEFAULT (_AES_PUSHDESCR_DESCR_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHDESCR */ 129 130 /* Bit fields for AES PUSHLEN */ 131 #define _AES_PUSHLEN_RESETVALUE 0x00000000UL /**< Default value for AES_PUSHLEN */ 132 #define _AES_PUSHLEN_MASK 0x7FFFFFFFUL /**< Mask for AES_PUSHLEN */ 133 #define _AES_PUSHLEN_LENGTH_SHIFT 0 /**< Shift value for AES_LENGTH */ 134 #define _AES_PUSHLEN_LENGTH_MASK 0xFFFFFFFUL /**< Bit mask for AES_LENGTH */ 135 #define _AES_PUSHLEN_LENGTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 136 #define AES_PUSHLEN_LENGTH_DEFAULT (_AES_PUSHLEN_LENGTH_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 137 #define AES_PUSHLEN_CONSTADDR (0x1UL << 28) /**< Constant address */ 138 #define _AES_PUSHLEN_CONSTADDR_SHIFT 28 /**< Shift value for AES_CONSTADDR */ 139 #define _AES_PUSHLEN_CONSTADDR_MASK 0x10000000UL /**< Bit mask for AES_CONSTADDR */ 140 #define _AES_PUSHLEN_CONSTADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 141 #define AES_PUSHLEN_CONSTADDR_DEFAULT (_AES_PUSHLEN_CONSTADDR_DEFAULT << 28) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 142 #define AES_PUSHLEN_REALIGN (0x1UL << 29) /**< Realign length */ 143 #define _AES_PUSHLEN_REALIGN_SHIFT 29 /**< Shift value for AES_REALIGN */ 144 #define _AES_PUSHLEN_REALIGN_MASK 0x20000000UL /**< Bit mask for AES_REALIGN */ 145 #define _AES_PUSHLEN_REALIGN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 146 #define AES_PUSHLEN_REALIGN_DEFAULT (_AES_PUSHLEN_REALIGN_DEFAULT << 29) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 147 #define AES_PUSHLEN_DISCARD (0x1UL << 30) /**< Discard data */ 148 #define _AES_PUSHLEN_DISCARD_SHIFT 30 /**< Shift value for AES_DISCARD */ 149 #define _AES_PUSHLEN_DISCARD_MASK 0x40000000UL /**< Bit mask for AES_DISCARD */ 150 #define _AES_PUSHLEN_DISCARD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_PUSHLEN */ 151 #define AES_PUSHLEN_DISCARD_DEFAULT (_AES_PUSHLEN_DISCARD_DEFAULT << 30) /**< Shifted mode DEFAULT for AES_PUSHLEN */ 152 153 /* Bit fields for AES IEN */ 154 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ 155 #define _AES_IEN_MASK 0x0000003FUL /**< Mask for AES_IEN */ 156 #define AES_IEN_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt enable */ 157 #define _AES_IEN_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ 158 #define _AES_IEN_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ 159 #define _AES_IEN_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 160 #define AES_IEN_FETCHERENDOFBLOCK_DEFAULT (_AES_IEN_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ 161 #define AES_IEN_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt enable */ 162 #define _AES_IEN_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ 163 #define _AES_IEN_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ 164 #define _AES_IEN_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 165 #define AES_IEN_FETCHERSTOPPED_DEFAULT (_AES_IEN_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IEN */ 166 #define AES_IEN_FETCHERERROR (0x1UL << 2) /**< Error interrupt enable */ 167 #define _AES_IEN_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ 168 #define _AES_IEN_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ 169 #define _AES_IEN_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 170 #define AES_IEN_FETCHERERROR_DEFAULT (_AES_IEN_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IEN */ 171 #define AES_IEN_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt enable */ 172 #define _AES_IEN_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ 173 #define _AES_IEN_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ 174 #define _AES_IEN_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 175 #define AES_IEN_PUSHERENDOFBLOCK_DEFAULT (_AES_IEN_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IEN */ 176 #define AES_IEN_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt enable */ 177 #define _AES_IEN_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ 178 #define _AES_IEN_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ 179 #define _AES_IEN_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 180 #define AES_IEN_PUSHERSTOPPED_DEFAULT (_AES_IEN_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IEN */ 181 #define AES_IEN_PUSHERERROR (0x1UL << 5) /**< Error interrupt enable */ 182 #define _AES_IEN_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ 183 #define _AES_IEN_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ 184 #define _AES_IEN_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 185 #define AES_IEN_PUSHERERROR_DEFAULT (_AES_IEN_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IEN */ 186 187 /* Bit fields for AES IF */ 188 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ 189 #define _AES_IF_MASK 0x0000003FUL /**< Mask for AES_IF */ 190 #define AES_IF_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag */ 191 #define _AES_IF_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ 192 #define _AES_IF_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ 193 #define _AES_IF_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 194 #define AES_IF_FETCHERENDOFBLOCK_DEFAULT (_AES_IF_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ 195 #define AES_IF_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag */ 196 #define _AES_IF_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ 197 #define _AES_IF_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ 198 #define _AES_IF_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 199 #define AES_IF_FETCHERSTOPPED_DEFAULT (_AES_IF_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IF */ 200 #define AES_IF_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag */ 201 #define _AES_IF_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ 202 #define _AES_IF_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ 203 #define _AES_IF_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 204 #define AES_IF_FETCHERERROR_DEFAULT (_AES_IF_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IF */ 205 #define AES_IF_PUSHERENDOFBLOCK (0x1UL << 3) /**< End of block interrupt flag */ 206 #define _AES_IF_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ 207 #define _AES_IF_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ 208 #define _AES_IF_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 209 #define AES_IF_PUSHERENDOFBLOCK_DEFAULT (_AES_IF_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IF */ 210 #define AES_IF_PUSHERSTOPPED (0x1UL << 4) /**< Stopped interrupt flag */ 211 #define _AES_IF_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ 212 #define _AES_IF_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ 213 #define _AES_IF_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 214 #define AES_IF_PUSHERSTOPPED_DEFAULT (_AES_IF_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IF */ 215 #define AES_IF_PUSHERERROR (0x1UL << 5) /**< Error interrupt flag */ 216 #define _AES_IF_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ 217 #define _AES_IF_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ 218 #define _AES_IF_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 219 #define AES_IF_PUSHERERROR_DEFAULT (_AES_IF_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IF */ 220 221 /* Bit fields for AES IFC */ 222 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */ 223 #define _AES_IFC_MASK 0x0000003FUL /**< Mask for AES_IFC */ 224 #define AES_IFC_FETCHERENDOFBLOCK (0x1UL << 0) /**< End of block interrupt flag clear */ 225 #define _AES_IFC_FETCHERENDOFBLOCK_SHIFT 0 /**< Shift value for AES_FETCHERENDOFBLOCK */ 226 #define _AES_IFC_FETCHERENDOFBLOCK_MASK 0x1UL /**< Bit mask for AES_FETCHERENDOFBLOCK */ 227 #define _AES_IFC_FETCHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 228 #define AES_IFC_FETCHERENDOFBLOCK_DEFAULT (_AES_IFC_FETCHERENDOFBLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */ 229 #define AES_IFC_FETCHERSTOPPED (0x1UL << 1) /**< Stopped interrupt flag clear */ 230 #define _AES_IFC_FETCHERSTOPPED_SHIFT 1 /**< Shift value for AES_FETCHERSTOPPED */ 231 #define _AES_IFC_FETCHERSTOPPED_MASK 0x2UL /**< Bit mask for AES_FETCHERSTOPPED */ 232 #define _AES_IFC_FETCHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 233 #define AES_IFC_FETCHERSTOPPED_DEFAULT (_AES_IFC_FETCHERSTOPPED_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_IFC */ 234 #define AES_IFC_FETCHERERROR (0x1UL << 2) /**< Error interrupt flag clear */ 235 #define _AES_IFC_FETCHERERROR_SHIFT 2 /**< Shift value for AES_FETCHERERROR */ 236 #define _AES_IFC_FETCHERERROR_MASK 0x4UL /**< Bit mask for AES_FETCHERERROR */ 237 #define _AES_IFC_FETCHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 238 #define AES_IFC_FETCHERERROR_DEFAULT (_AES_IFC_FETCHERERROR_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_IFC */ 239 #define AES_IFC_PUSHERENDOFBLOCK (0x1UL << 3) /**< New BitField */ 240 #define _AES_IFC_PUSHERENDOFBLOCK_SHIFT 3 /**< Shift value for AES_PUSHERENDOFBLOCK */ 241 #define _AES_IFC_PUSHERENDOFBLOCK_MASK 0x8UL /**< Bit mask for AES_PUSHERENDOFBLOCK */ 242 #define _AES_IFC_PUSHERENDOFBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 243 #define AES_IFC_PUSHERENDOFBLOCK_DEFAULT (_AES_IFC_PUSHERENDOFBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_IFC */ 244 #define AES_IFC_PUSHERSTOPPED (0x1UL << 4) /**< New BitField */ 245 #define _AES_IFC_PUSHERSTOPPED_SHIFT 4 /**< Shift value for AES_PUSHERSTOPPED */ 246 #define _AES_IFC_PUSHERSTOPPED_MASK 0x10UL /**< Bit mask for AES_PUSHERSTOPPED */ 247 #define _AES_IFC_PUSHERSTOPPED_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 248 #define AES_IFC_PUSHERSTOPPED_DEFAULT (_AES_IFC_PUSHERSTOPPED_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_IFC */ 249 #define AES_IFC_PUSHERERROR (0x1UL << 5) /**< New BitField */ 250 #define _AES_IFC_PUSHERERROR_SHIFT 5 /**< Shift value for AES_PUSHERERROR */ 251 #define _AES_IFC_PUSHERERROR_MASK 0x20UL /**< Bit mask for AES_PUSHERERROR */ 252 #define _AES_IFC_PUSHERERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 253 #define AES_IFC_PUSHERERROR_DEFAULT (_AES_IFC_PUSHERERROR_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_IFC */ 254 255 /* Bit fields for AES CTRL */ 256 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ 257 #define _AES_CTRL_MASK 0x0000001FUL /**< Mask for AES_CTRL */ 258 #define AES_CTRL_FETCHERSCATTERGATHER (0x1UL << 0) /**< Fetcher scatter/gather */ 259 #define _AES_CTRL_FETCHERSCATTERGATHER_SHIFT 0 /**< Shift value for AES_FETCHERSCATTERGATHER */ 260 #define _AES_CTRL_FETCHERSCATTERGATHER_MASK 0x1UL /**< Bit mask for AES_FETCHERSCATTERGATHER */ 261 #define _AES_CTRL_FETCHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 262 #define AES_CTRL_FETCHERSCATTERGATHER_DEFAULT (_AES_CTRL_FETCHERSCATTERGATHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ 263 #define AES_CTRL_PUSHERSCATTERGATHER (0x1UL << 1) /**< Pusher scatter/gather */ 264 #define _AES_CTRL_PUSHERSCATTERGATHER_SHIFT 1 /**< Shift value for AES_PUSHERSCATTERGATHER */ 265 #define _AES_CTRL_PUSHERSCATTERGATHER_MASK 0x2UL /**< Bit mask for AES_PUSHERSCATTERGATHER */ 266 #define _AES_CTRL_PUSHERSCATTERGATHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 267 #define AES_CTRL_PUSHERSCATTERGATHER_DEFAULT (_AES_CTRL_PUSHERSCATTERGATHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ 268 #define AES_CTRL_STOPFETCHER (0x1UL << 2) /**< Stop fetcher */ 269 #define _AES_CTRL_STOPFETCHER_SHIFT 2 /**< Shift value for AES_STOPFETCHER */ 270 #define _AES_CTRL_STOPFETCHER_MASK 0x4UL /**< Bit mask for AES_STOPFETCHER */ 271 #define _AES_CTRL_STOPFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 272 #define AES_CTRL_STOPFETCHER_DEFAULT (_AES_CTRL_STOPFETCHER_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ 273 #define AES_CTRL_STOPPUSHER (0x1UL << 3) /**< Stop pusher */ 274 #define _AES_CTRL_STOPPUSHER_SHIFT 3 /**< Shift value for AES_STOPPUSHER */ 275 #define _AES_CTRL_STOPPUSHER_MASK 0x8UL /**< Bit mask for AES_STOPPUSHER */ 276 #define _AES_CTRL_STOPPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 277 #define AES_CTRL_STOPPUSHER_DEFAULT (_AES_CTRL_STOPPUSHER_DEFAULT << 3) /**< Shifted mode DEFAULT for AES_CTRL */ 278 #define AES_CTRL_SWRESET (0x1UL << 4) /**< Software reset */ 279 #define _AES_CTRL_SWRESET_SHIFT 4 /**< Shift value for AES_SWRESET */ 280 #define _AES_CTRL_SWRESET_MASK 0x10UL /**< Bit mask for AES_SWRESET */ 281 #define _AES_CTRL_SWRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 282 #define AES_CTRL_SWRESET_DEFAULT (_AES_CTRL_SWRESET_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ 283 284 /* Bit fields for AES CMD */ 285 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ 286 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ 287 #define AES_CMD_STARTFETCHER (0x1UL << 0) /**< Start fetch */ 288 #define _AES_CMD_STARTFETCHER_SHIFT 0 /**< Shift value for AES_STARTFETCHER */ 289 #define _AES_CMD_STARTFETCHER_MASK 0x1UL /**< Bit mask for AES_STARTFETCHER */ 290 #define _AES_CMD_STARTFETCHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 291 #define AES_CMD_STARTFETCHER_DEFAULT (_AES_CMD_STARTFETCHER_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ 292 #define AES_CMD_STARTPUSHER (0x1UL << 1) /**< Start push */ 293 #define _AES_CMD_STARTPUSHER_SHIFT 1 /**< Shift value for AES_STARTPUSHER */ 294 #define _AES_CMD_STARTPUSHER_MASK 0x2UL /**< Bit mask for AES_STARTPUSHER */ 295 #define _AES_CMD_STARTPUSHER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 296 #define AES_CMD_STARTPUSHER_DEFAULT (_AES_CMD_STARTPUSHER_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ 297 298 /* Bit fields for AES STATUS */ 299 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ 300 #define _AES_STATUS_MASK 0xFFFF0073UL /**< Mask for AES_STATUS */ 301 #define AES_STATUS_FETCHERBSY (0x1UL << 0) /**< Fetcher busy */ 302 #define _AES_STATUS_FETCHERBSY_SHIFT 0 /**< Shift value for AES_FETCHERBSY */ 303 #define _AES_STATUS_FETCHERBSY_MASK 0x1UL /**< Bit mask for AES_FETCHERBSY */ 304 #define _AES_STATUS_FETCHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 305 #define AES_STATUS_FETCHERBSY_DEFAULT (_AES_STATUS_FETCHERBSY_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ 306 #define AES_STATUS_PUSHERBSY (0x1UL << 1) /**< Pusher busy */ 307 #define _AES_STATUS_PUSHERBSY_SHIFT 1 /**< Shift value for AES_PUSHERBSY */ 308 #define _AES_STATUS_PUSHERBSY_MASK 0x2UL /**< Bit mask for AES_PUSHERBSY */ 309 #define _AES_STATUS_PUSHERBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 310 #define AES_STATUS_PUSHERBSY_DEFAULT (_AES_STATUS_PUSHERBSY_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_STATUS */ 311 #define AES_STATUS_NOTEMPTY (0x1UL << 4) /**< Not empty flag from input FIFO (fetcher) */ 312 #define _AES_STATUS_NOTEMPTY_SHIFT 4 /**< Shift value for AES_NOTEMPTY */ 313 #define _AES_STATUS_NOTEMPTY_MASK 0x10UL /**< Bit mask for AES_NOTEMPTY */ 314 #define _AES_STATUS_NOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 315 #define AES_STATUS_NOTEMPTY_DEFAULT (_AES_STATUS_NOTEMPTY_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_STATUS */ 316 #define AES_STATUS_WAITING (0x1UL << 5) /**< Pusher waiting for FIFO */ 317 #define _AES_STATUS_WAITING_SHIFT 5 /**< Shift value for AES_WAITING */ 318 #define _AES_STATUS_WAITING_MASK 0x20UL /**< Bit mask for AES_WAITING */ 319 #define _AES_STATUS_WAITING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 320 #define AES_STATUS_WAITING_DEFAULT (_AES_STATUS_WAITING_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_STATUS */ 321 #define AES_STATUS_SOFTRSTBSY (0x1UL << 6) /**< Software reset busy */ 322 #define _AES_STATUS_SOFTRSTBSY_SHIFT 6 /**< Shift value for AES_SOFTRSTBSY */ 323 #define _AES_STATUS_SOFTRSTBSY_MASK 0x40UL /**< Bit mask for AES_SOFTRSTBSY */ 324 #define _AES_STATUS_SOFTRSTBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 325 #define AES_STATUS_SOFTRSTBSY_DEFAULT (_AES_STATUS_SOFTRSTBSY_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_STATUS */ 326 #define _AES_STATUS_FIFODATANUM_SHIFT 16 /**< Shift value for AES_FIFODATANUM */ 327 #define _AES_STATUS_FIFODATANUM_MASK 0xFFFF0000UL /**< Bit mask for AES_FIFODATANUM */ 328 #define _AES_STATUS_FIFODATANUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 329 #define AES_STATUS_FIFODATANUM_DEFAULT (_AES_STATUS_FIFODATANUM_DEFAULT << 16) /**< Shifted mode DEFAULT for AES_STATUS */ 330 331 /** @} End of group EFR32MG21_AES_BitFields */ 332 /** @} End of group EFR32MG21_AES */ 333 /** @} End of group Parts */ 334 335 #endif /* EFR32MG21_AES_H */ 336
