1 /***************************************************************************//** 2 * @file 3 * @brief EFM32WG_AES register and bit field definitions 4 ******************************************************************************* 5 * # License 6 * <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b> 7 ******************************************************************************* 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 ******************************************************************************/ 30 31 #if defined(__ICCARM__) 32 #pragma system_include /* Treat file as system include file. */ 33 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 34 #pragma clang system_header /* Treat file as system include file. */ 35 #endif 36 37 /***************************************************************************//** 38 * @addtogroup Parts 39 * @{ 40 ******************************************************************************/ 41 /***************************************************************************//** 42 * @defgroup EFM32WG_AES 43 * @{ 44 * @brief EFM32WG_AES Register Declaration 45 ******************************************************************************/ 46 typedef struct { 47 __IOM uint32_t CTRL; /**< Control Register */ 48 __IOM uint32_t CMD; /**< Command Register */ 49 __IM uint32_t STATUS; /**< Status Register */ 50 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 51 __IM uint32_t IF; /**< Interrupt Flag Register */ 52 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ 53 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ 54 __IOM uint32_t DATA; /**< DATA Register */ 55 __IOM uint32_t XORDATA; /**< XORDATA Register */ 56 uint32_t RESERVED0[3U]; /**< Reserved for future use **/ 57 __IOM uint32_t KEYLA; /**< KEY Low Register */ 58 __IOM uint32_t KEYLB; /**< KEY Low Register */ 59 __IOM uint32_t KEYLC; /**< KEY Low Register */ 60 __IOM uint32_t KEYLD; /**< KEY Low Register */ 61 __IOM uint32_t KEYHA; /**< KEY High Register */ 62 __IOM uint32_t KEYHB; /**< KEY High Register */ 63 __IOM uint32_t KEYHC; /**< KEY High Register */ 64 __IOM uint32_t KEYHD; /**< KEY High Register */ 65 } AES_TypeDef; /**< AES Register Declaration *//** @} */ 66 67 /***************************************************************************//** 68 * @defgroup EFM32WG_AES_BitFields 69 * @{ 70 ******************************************************************************/ 71 72 /* Bit fields for AES CTRL */ 73 #define _AES_CTRL_RESETVALUE 0x00000000UL /**< Default value for AES_CTRL */ 74 #define _AES_CTRL_MASK 0x00000077UL /**< Mask for AES_CTRL */ 75 #define AES_CTRL_DECRYPT (0x1UL << 0) /**< Decryption/Encryption Mode */ 76 #define _AES_CTRL_DECRYPT_SHIFT 0 /**< Shift value for AES_DECRYPT */ 77 #define _AES_CTRL_DECRYPT_MASK 0x1UL /**< Bit mask for AES_DECRYPT */ 78 #define _AES_CTRL_DECRYPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 79 #define AES_CTRL_DECRYPT_DEFAULT (_AES_CTRL_DECRYPT_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CTRL */ 80 #define AES_CTRL_AES256 (0x1UL << 1) /**< AES-256 Mode */ 81 #define _AES_CTRL_AES256_SHIFT 1 /**< Shift value for AES_AES256 */ 82 #define _AES_CTRL_AES256_MASK 0x2UL /**< Bit mask for AES_AES256 */ 83 #define _AES_CTRL_AES256_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 84 #define AES_CTRL_AES256_DEFAULT (_AES_CTRL_AES256_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CTRL */ 85 #define AES_CTRL_KEYBUFEN (0x1UL << 2) /**< Key Buffer Enable */ 86 #define _AES_CTRL_KEYBUFEN_SHIFT 2 /**< Shift value for AES_KEYBUFEN */ 87 #define _AES_CTRL_KEYBUFEN_MASK 0x4UL /**< Bit mask for AES_KEYBUFEN */ 88 #define _AES_CTRL_KEYBUFEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 89 #define AES_CTRL_KEYBUFEN_DEFAULT (_AES_CTRL_KEYBUFEN_DEFAULT << 2) /**< Shifted mode DEFAULT for AES_CTRL */ 90 #define AES_CTRL_DATASTART (0x1UL << 4) /**< AES_DATA Write Start */ 91 #define _AES_CTRL_DATASTART_SHIFT 4 /**< Shift value for AES_DATASTART */ 92 #define _AES_CTRL_DATASTART_MASK 0x10UL /**< Bit mask for AES_DATASTART */ 93 #define _AES_CTRL_DATASTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 94 #define AES_CTRL_DATASTART_DEFAULT (_AES_CTRL_DATASTART_DEFAULT << 4) /**< Shifted mode DEFAULT for AES_CTRL */ 95 #define AES_CTRL_XORSTART (0x1UL << 5) /**< AES_XORDATA Write Start */ 96 #define _AES_CTRL_XORSTART_SHIFT 5 /**< Shift value for AES_XORSTART */ 97 #define _AES_CTRL_XORSTART_MASK 0x20UL /**< Bit mask for AES_XORSTART */ 98 #define _AES_CTRL_XORSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 99 #define AES_CTRL_XORSTART_DEFAULT (_AES_CTRL_XORSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for AES_CTRL */ 100 #define AES_CTRL_BYTEORDER (0x1UL << 6) /**< Configure byte order in data and key registers */ 101 #define _AES_CTRL_BYTEORDER_SHIFT 6 /**< Shift value for AES_BYTEORDER */ 102 #define _AES_CTRL_BYTEORDER_MASK 0x40UL /**< Bit mask for AES_BYTEORDER */ 103 #define _AES_CTRL_BYTEORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CTRL */ 104 #define AES_CTRL_BYTEORDER_DEFAULT (_AES_CTRL_BYTEORDER_DEFAULT << 6) /**< Shifted mode DEFAULT for AES_CTRL */ 105 106 /* Bit fields for AES CMD */ 107 #define _AES_CMD_RESETVALUE 0x00000000UL /**< Default value for AES_CMD */ 108 #define _AES_CMD_MASK 0x00000003UL /**< Mask for AES_CMD */ 109 #define AES_CMD_START (0x1UL << 0) /**< Encryption/Decryption Start */ 110 #define _AES_CMD_START_SHIFT 0 /**< Shift value for AES_START */ 111 #define _AES_CMD_START_MASK 0x1UL /**< Bit mask for AES_START */ 112 #define _AES_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 113 #define AES_CMD_START_DEFAULT (_AES_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_CMD */ 114 #define AES_CMD_STOP (0x1UL << 1) /**< Encryption/Decryption Stop */ 115 #define _AES_CMD_STOP_SHIFT 1 /**< Shift value for AES_STOP */ 116 #define _AES_CMD_STOP_MASK 0x2UL /**< Bit mask for AES_STOP */ 117 #define _AES_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_CMD */ 118 #define AES_CMD_STOP_DEFAULT (_AES_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for AES_CMD */ 119 120 /* Bit fields for AES STATUS */ 121 #define _AES_STATUS_RESETVALUE 0x00000000UL /**< Default value for AES_STATUS */ 122 #define _AES_STATUS_MASK 0x00000001UL /**< Mask for AES_STATUS */ 123 #define AES_STATUS_RUNNING (0x1UL << 0) /**< AES Running */ 124 #define _AES_STATUS_RUNNING_SHIFT 0 /**< Shift value for AES_RUNNING */ 125 #define _AES_STATUS_RUNNING_MASK 0x1UL /**< Bit mask for AES_RUNNING */ 126 #define _AES_STATUS_RUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_STATUS */ 127 #define AES_STATUS_RUNNING_DEFAULT (_AES_STATUS_RUNNING_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_STATUS */ 128 129 /* Bit fields for AES IEN */ 130 #define _AES_IEN_RESETVALUE 0x00000000UL /**< Default value for AES_IEN */ 131 #define _AES_IEN_MASK 0x00000001UL /**< Mask for AES_IEN */ 132 #define AES_IEN_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Enable */ 133 #define _AES_IEN_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 134 #define _AES_IEN_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 135 #define _AES_IEN_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IEN */ 136 #define AES_IEN_DONE_DEFAULT (_AES_IEN_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IEN */ 137 138 /* Bit fields for AES IF */ 139 #define _AES_IF_RESETVALUE 0x00000000UL /**< Default value for AES_IF */ 140 #define _AES_IF_MASK 0x00000001UL /**< Mask for AES_IF */ 141 #define AES_IF_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag */ 142 #define _AES_IF_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 143 #define _AES_IF_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 144 #define _AES_IF_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IF */ 145 #define AES_IF_DONE_DEFAULT (_AES_IF_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IF */ 146 147 /* Bit fields for AES IFS */ 148 #define _AES_IFS_RESETVALUE 0x00000000UL /**< Default value for AES_IFS */ 149 #define _AES_IFS_MASK 0x00000001UL /**< Mask for AES_IFS */ 150 #define AES_IFS_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Set */ 151 #define _AES_IFS_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 152 #define _AES_IFS_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 153 #define _AES_IFS_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFS */ 154 #define AES_IFS_DONE_DEFAULT (_AES_IFS_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFS */ 155 156 /* Bit fields for AES IFC */ 157 #define _AES_IFC_RESETVALUE 0x00000000UL /**< Default value for AES_IFC */ 158 #define _AES_IFC_MASK 0x00000001UL /**< Mask for AES_IFC */ 159 #define AES_IFC_DONE (0x1UL << 0) /**< Encryption/Decryption Done Interrupt Flag Clear */ 160 #define _AES_IFC_DONE_SHIFT 0 /**< Shift value for AES_DONE */ 161 #define _AES_IFC_DONE_MASK 0x1UL /**< Bit mask for AES_DONE */ 162 #define _AES_IFC_DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_IFC */ 163 #define AES_IFC_DONE_DEFAULT (_AES_IFC_DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_IFC */ 164 165 /* Bit fields for AES DATA */ 166 #define _AES_DATA_RESETVALUE 0x00000000UL /**< Default value for AES_DATA */ 167 #define _AES_DATA_MASK 0xFFFFFFFFUL /**< Mask for AES_DATA */ 168 #define _AES_DATA_DATA_SHIFT 0 /**< Shift value for AES_DATA */ 169 #define _AES_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_DATA */ 170 #define _AES_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_DATA */ 171 #define AES_DATA_DATA_DEFAULT (_AES_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_DATA */ 172 173 /* Bit fields for AES XORDATA */ 174 #define _AES_XORDATA_RESETVALUE 0x00000000UL /**< Default value for AES_XORDATA */ 175 #define _AES_XORDATA_MASK 0xFFFFFFFFUL /**< Mask for AES_XORDATA */ 176 #define _AES_XORDATA_XORDATA_SHIFT 0 /**< Shift value for AES_XORDATA */ 177 #define _AES_XORDATA_XORDATA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_XORDATA */ 178 #define _AES_XORDATA_XORDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_XORDATA */ 179 #define AES_XORDATA_XORDATA_DEFAULT (_AES_XORDATA_XORDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_XORDATA */ 180 181 /* Bit fields for AES KEYLA */ 182 #define _AES_KEYLA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLA */ 183 #define _AES_KEYLA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLA */ 184 #define _AES_KEYLA_KEYLA_SHIFT 0 /**< Shift value for AES_KEYLA */ 185 #define _AES_KEYLA_KEYLA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLA */ 186 #define _AES_KEYLA_KEYLA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLA */ 187 #define AES_KEYLA_KEYLA_DEFAULT (_AES_KEYLA_KEYLA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLA */ 188 189 /* Bit fields for AES KEYLB */ 190 #define _AES_KEYLB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLB */ 191 #define _AES_KEYLB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLB */ 192 #define _AES_KEYLB_KEYLB_SHIFT 0 /**< Shift value for AES_KEYLB */ 193 #define _AES_KEYLB_KEYLB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLB */ 194 #define _AES_KEYLB_KEYLB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLB */ 195 #define AES_KEYLB_KEYLB_DEFAULT (_AES_KEYLB_KEYLB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLB */ 196 197 /* Bit fields for AES KEYLC */ 198 #define _AES_KEYLC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLC */ 199 #define _AES_KEYLC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLC */ 200 #define _AES_KEYLC_KEYLC_SHIFT 0 /**< Shift value for AES_KEYLC */ 201 #define _AES_KEYLC_KEYLC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLC */ 202 #define _AES_KEYLC_KEYLC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLC */ 203 #define AES_KEYLC_KEYLC_DEFAULT (_AES_KEYLC_KEYLC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLC */ 204 205 /* Bit fields for AES KEYLD */ 206 #define _AES_KEYLD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYLD */ 207 #define _AES_KEYLD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYLD */ 208 #define _AES_KEYLD_KEYLD_SHIFT 0 /**< Shift value for AES_KEYLD */ 209 #define _AES_KEYLD_KEYLD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYLD */ 210 #define _AES_KEYLD_KEYLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYLD */ 211 #define AES_KEYLD_KEYLD_DEFAULT (_AES_KEYLD_KEYLD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYLD */ 212 213 /* Bit fields for AES KEYHA */ 214 #define _AES_KEYHA_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHA */ 215 #define _AES_KEYHA_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHA */ 216 #define _AES_KEYHA_KEYHA_SHIFT 0 /**< Shift value for AES_KEYHA */ 217 #define _AES_KEYHA_KEYHA_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHA */ 218 #define _AES_KEYHA_KEYHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHA */ 219 #define AES_KEYHA_KEYHA_DEFAULT (_AES_KEYHA_KEYHA_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHA */ 220 221 /* Bit fields for AES KEYHB */ 222 #define _AES_KEYHB_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHB */ 223 #define _AES_KEYHB_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHB */ 224 #define _AES_KEYHB_KEYHB_SHIFT 0 /**< Shift value for AES_KEYHB */ 225 #define _AES_KEYHB_KEYHB_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHB */ 226 #define _AES_KEYHB_KEYHB_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHB */ 227 #define AES_KEYHB_KEYHB_DEFAULT (_AES_KEYHB_KEYHB_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHB */ 228 229 /* Bit fields for AES KEYHC */ 230 #define _AES_KEYHC_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHC */ 231 #define _AES_KEYHC_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHC */ 232 #define _AES_KEYHC_KEYHC_SHIFT 0 /**< Shift value for AES_KEYHC */ 233 #define _AES_KEYHC_KEYHC_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHC */ 234 #define _AES_KEYHC_KEYHC_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHC */ 235 #define AES_KEYHC_KEYHC_DEFAULT (_AES_KEYHC_KEYHC_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHC */ 236 237 /* Bit fields for AES KEYHD */ 238 #define _AES_KEYHD_RESETVALUE 0x00000000UL /**< Default value for AES_KEYHD */ 239 #define _AES_KEYHD_MASK 0xFFFFFFFFUL /**< Mask for AES_KEYHD */ 240 #define _AES_KEYHD_KEYHD_SHIFT 0 /**< Shift value for AES_KEYHD */ 241 #define _AES_KEYHD_KEYHD_MASK 0xFFFFFFFFUL /**< Bit mask for AES_KEYHD */ 242 #define _AES_KEYHD_KEYHD_DEFAULT 0x00000000UL /**< Mode DEFAULT for AES_KEYHD */ 243 #define AES_KEYHD_KEYHD_DEFAULT (_AES_KEYHD_KEYHD_DEFAULT << 0) /**< Shifted mode DEFAULT for AES_KEYHD */ 244 245 /** @} End of group EFM32WG_AES */ 246 /** @} End of group Parts */ 247
