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Searched refs:uint32_t (Results 1 – 25 of 205) sorted by relevance

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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/
DRP2350.h159 …__IOM uint32_t RESET; /*!< RESET …
160 …__IOM uint32_t WDSEL; /*!< WDSEL …
161 …__IOM uint32_t RESET_DONE; /*!< RESET_DONE …
176 …__IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) …
177 …__IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) …
178 …__IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this …
179 …__IOM uint32_t DONE; /*!< Is the subsystem ready? …
194 …__IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (excep…
195 …__IOM uint32_t CLK_GPOUT0_DIV; /*!< CLK_GPOUT0_DIV …
196 …__IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which src is currently selected (one-…
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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Device/RP2040/Include/
DRP2040.h131 …__IOM uint32_t RESET; /*!< Reset control. If a bit is set it means the per…
133 …__IOM uint32_t WDSEL; /*!< Watchdog select. If a bit is set then the watch…
135 …__IOM uint32_t RESET_DONE; /*!< Reset done. If a bit is set then a reset done s…
152 …__IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) …
153 …__IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) …
154 …__IOM uint32_t WDSEL; /*!< Set to 1 if this peripheral should be reset whe…
156 …__IOM uint32_t DONE; /*!< Indicates the peripheral's registers are ready …
171 …__IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (excep…
172 …__IOM uint32_t CLK_GPOUT0_DIV; /*!< Clock divisor, can be changed on-the-fly …
173 …__IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which SRC is currently selected by th…
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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/
Dcmsis_armclang_ltm.h67 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
91 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
149 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
258 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR()
293 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) in __CLZ()
340 #define __LDREXW (uint32_t)__builtin_arm_ldrex
351 #define __STREXB (uint32_t)__builtin_arm_strex
362 #define __STREXH (uint32_t)__builtin_arm_strex
373 #define __STREXW (uint32_t)__builtin_arm_strex
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Dcore_cm0plus.h215 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
216 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
217 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
218 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
219 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
221 uint32_t w; /*!< Type used for word access */
245 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
246 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
248 uint32_t w; /*!< Type used for word access */
263 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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Dcore_cm33.h342 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
343 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
344 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
345 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
346 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
347 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
348 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
349 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
351 uint32_t w; /*!< Type used for word access */
381 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
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Dcmsis_gcc.h91 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
207 __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) in __REV()
219 __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) in __REV16()
221 uint32_t result; in __REV16()
247 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) in __ROR()
274 __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) in __RBIT()
276 uint32_t result; in __RBIT()
281 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ in __RBIT()
302 __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) in __CLZ()
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Dcmsis_armcc.h88 #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
97 #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
100 #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
160 __STATIC_INLINE uint32_t __get_CONTROL(void) in __get_CONTROL()
162 register uint32_t __regControl __ASM("control"); in __get_CONTROL()
172 __STATIC_INLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
174 register uint32_t __regControl __ASM("control"); in __set_CONTROL()
184 __STATIC_INLINE uint32_t __get_IPSR(void) in __get_IPSR()
186 register uint32_t __regIPSR __ASM("ipsr"); in __get_IPSR()
196 __STATIC_INLINE uint32_t __get_APSR(void) in __get_APSR()
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Dcmsis_iccarm.h206 __IAR_FT uint32_t __iar_uint32_read(void const *ptr) in __iar_uint32_read()
208 return *(__packed uint32_t*)(ptr); in __iar_uint32_read()
217 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) in __iar_uint32_write()
219 *(__packed uint32_t*)(ptr) = val;; in __iar_uint32_write()
228 __packed struct __iar_u32 { uint32_t v; };
283 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
359 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
387 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) in __TZ_set_CONTROL_NS()
558 __STATIC_INLINE uint8_t __CLZ(uint32_t data) in __CLZ()
562 uint32_t count = 0U; in __CLZ()
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Dmpu_armv8.h123 uint32_t RBAR; /*!< Region Base Address Register value */
124 uint32_t RLAR; /*!< Region Limit Address Register value */
130 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) in ARM_MPU_Enable()
158 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) in ARM_MPU_Enable_NS()
191 const uint32_t pos = ((idx % 4U) * 8U); in ARM_MPU_SetMemAttrEx()
192 const uint32_t mask = 0xFFU << pos; in ARM_MPU_SetMemAttrEx()
225 __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) in ARM_MPU_ClrRegionEx()
234 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) in ARM_MPU_ClrRegion()
243 __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) in ARM_MPU_ClrRegion_NS()
255 __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) in ARM_MPU_SetRegionEx()
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Dcmsis_armclang.h87 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
94 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
282 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) in __SSAT()
308 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) in __USAT()
312 const uint32_t max = ((1U << sat) - 1U); in __USAT()
322 return ((uint32_t)val); in __USAT()
352 #define __STREXB (uint32_t)__builtin_arm_strex
374 #define __STREXH (uint32_t)__builtin_arm_strex
385 #define __LDREXW (uint32_t)__builtin_arm_ldrex
396 #define __STREXW (uint32_t)__builtin_arm_strex
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Dcmsis_clang.h92 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
99 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
287 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) in __SSAT()
313 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) in __USAT()
317 const uint32_t max = ((1U << sat) - 1U); in __USAT()
327 return ((uint32_t)val); in __USAT()
357 #define __STREXB (uint32_t)__builtin_arm_strex
379 #define __STREXH (uint32_t)__builtin_arm_strex
390 #define __LDREXW (uint32_t)__builtin_arm_ldrex
401 #define __STREXW (uint32_t)__builtin_arm_strex
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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/
Dcmsis_gcc_m.h47 uint32_t const* src; in __cmsis_start()
48 uint32_t* dest; in __cmsis_start()
49 uint32_t wlen; in __cmsis_start()
53 uint32_t* dest; in __cmsis_start()
54 uint32_t wlen; in __cmsis_start()
63 for(uint32_t i=0u; i<pTable->wlen; ++i) { in __cmsis_start()
69 for(uint32_t i=0u; i<pTable->wlen; ++i) { in __cmsis_start()
110 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
127 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) in __get_CONTROL()
129 uint32_t result; in __get_CONTROL()
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Dcmsis_armclang_m.h73 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
87 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
99 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
109 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) in __STRT()
128 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) in __get_CONTROL()
130 uint32_t result; in __get_CONTROL()
143 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) in __TZ_get_CONTROL_NS()
145 uint32_t result; in __TZ_get_CONTROL_NS()
158 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
171 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) in __TZ_set_CONTROL_NS()
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Dcmsis_clang_m.h79 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
94 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRBT()
106 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); in __STRHT()
116 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) in __STRT()
134 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void) in __get_CONTROL()
136 uint32_t result; in __get_CONTROL()
149 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) in __TZ_get_CONTROL_NS()
151 uint32_t result; in __TZ_get_CONTROL_NS()
164 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
177 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) in __TZ_set_CONTROL_NS()
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Dcmsis_tiarmclang_m.h82 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
89 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
144 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
318 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) in __SSAT()
344 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) in __USAT()
348 const uint32_t max = ((1U << sat) - 1U); in __USAT()
358 return ((uint32_t)val); in __USAT()
388 #define __STREXB (uint32_t)__builtin_arm_strex
410 #define __STREXH (uint32_t)__builtin_arm_strex
421 #define __LDREXW (uint32_t)__builtin_arm_ldrex
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Darmv7m_cachel1.h65 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ in SCB_EnableICache()
81 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ in SCB_DisableICache()
117 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); in SCB_InvalidateICache_by_Addr()
118 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; in SCB_InvalidateICache_by_Addr()
142 uint32_t ccsidr; in SCB_EnableDCache()
143 uint32_t sets; in SCB_EnableDCache()
144 uint32_t ways; in SCB_EnableDCache()
154 sets = (uint32_t)(CCSIDR_SETS(ccsidr)); in SCB_EnableDCache()
156 ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); in SCB_EnableDCache()
167 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ in SCB_EnableDCache()
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Dcmsis_iccarm_m.h213 __IAR_FT uint32_t __iar_uint32_read(void const *ptr) in __iar_uint32_read()
215 return *(__packed uint32_t*)(ptr); in __iar_uint32_read()
224 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) in __iar_uint32_write()
226 *(__packed uint32_t*)(ptr) = val;; in __iar_uint32_write()
235 __packed struct __iar_u32 { uint32_t v; };
290 __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { in __TZ_set_STACKSEAL_S()
378 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) in __set_CONTROL()
408 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) in __TZ_set_CONTROL_NS()
586 __STATIC_INLINE uint8_t __CLZ(uint32_t data) in __CLZ()
590 uint32_t count = 0U; in __CLZ()
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Darmv8m_pmu.h174 __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
179 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
180 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
182 __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
183 __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
185 __STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
186 __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
188 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
189 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
191 __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
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/hal_rpi_pico-latest/src/rp2_common/pico_bootrom/include/pico/
Dbootrom.h27 typedef uint32_t (*rom_popcount32_fn)(uint32_t);
28 typedef uint32_t (*rom_reverse32_fn)(uint32_t);
29 typedef uint32_t (*rom_clz32_fn)(uint32_t);
30 typedef uint32_t (*rom_ctz32_fn)(uint32_t);
31 typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t);
32 typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t);
33 typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t);
34 typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t);
36 typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t);
37 typedef int (*rom_reboot_fn)(uint32_t flags, uint32_t delay_ms, uint32_t p0, uint32_t p1);
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/hal_rpi_pico-latest/src/host/hardware_divider/include/hardware/
Ddivider.h31 static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { in hw_divider_divmod_u32()
32 if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this in hw_divider_divmod_u32()
46 if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); in hw_divider_divmod_s32()
47 return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b); in hw_divider_divmod_s32()
74 static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { in hw_divider_divmod_u32_start()
114 inline static uint32_t to_quotient_u32(divmod_result_t r) { in to_quotient_u32()
115 return (uint32_t) r; in to_quotient_u32()
125 return (int32_t)(uint32_t)r; in to_quotient_s32()
136 inline static uint32_t to_remainder_u32(divmod_result_t r) { in to_remainder_u32()
137 return (uint32_t)(r >> 32u); in to_remainder_u32()
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/hal_rpi_pico-latest/src/rp2_common/hardware_divider/include/hardware/
Ddivider.h75 if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-__sign_of(a)); in hw_divider_divmod_s32()
76 return (((uint64_t)(a%b))<<32u) | (uint32_t)(a/b); in hw_divider_divmod_s32()
90 divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b);
92 static inline divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b) { in hw_divider_divmod_u32()
93 if (!b) return (((uint64_t)a)<<32u) | (uint32_t)(-1); // todo check this in hw_divider_divmod_u32()
110 sio_hw->div_sdividend = (uint32_t)a; in hw_divider_divmod_s32_start()
111 sio_hw->div_sdivisor = (uint32_t)b; in hw_divider_divmod_s32_start()
126 static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) { in hw_divider_divmod_u32_start()
149 uint32_t tmp; // allow compiler to pick scratch register in hw_divider_wait_ready()
198 inline static uint32_t to_quotient_u32(divmod_result_t r) { in to_quotient_u32()
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/hal_rpi_pico-latest/src/rp2_common/hardware_gpio/include/hardware/
Dgpio_coproc.h28 __force_inline static void gpioc_lo_out_put(uint32_t x) { in gpioc_lo_out_put()
33 __force_inline static void gpioc_lo_out_xor(uint32_t x) { in gpioc_lo_out_xor()
38 __force_inline static void gpioc_lo_out_set(uint32_t x) { in gpioc_lo_out_set()
43 __force_inline static void gpioc_lo_out_clr(uint32_t x) { in gpioc_lo_out_clr()
48 __force_inline static void gpioc_hi_out_put(uint32_t x) { in gpioc_hi_out_put()
53 __force_inline static void gpioc_hi_out_xor(uint32_t x) { in gpioc_hi_out_xor()
58 __force_inline static void gpioc_hi_out_set(uint32_t x) { in gpioc_hi_out_set()
63 __force_inline static void gpioc_hi_out_clr(uint32_t x) { in gpioc_hi_out_clr()
99 __force_inline static void gpioc_lo_oe_put(uint32_t x) { in gpioc_lo_oe_put()
104 __force_inline static void gpioc_lo_oe_xor(uint32_t x) { in gpioc_lo_oe_xor()
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Dgpio.h205 typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t event_mask);
263 void gpio_set_function_masked(uint32_t gpio_mask, gpio_function_t fn);
466 void gpio_set_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
525 void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t event_mask, bool enabled, gpio_irq_call…
537 void gpio_set_dormant_irq_enabled(uint gpio, uint32_t event_mask, bool enabled);
546 static inline uint32_t gpio_get_irq_event_mask(uint gpio) { in gpio_get_irq_event_mask()
568 void gpio_acknowledge_irq(uint gpio, uint32_t event_mask);
603 void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler,…
708 void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler);
788 void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler);
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/hal_rpi_pico-latest/src/common/boot_picoboot_headers/include/boot/
Dpicoboot.h87 uint32_t dPC; // 0 means reset into regular boot path
88 uint32_t dSP;
89 uint32_t dDelayMS;
95 uint32_t dFlags;
96 uint32_t dDelayMS;
97 uint32_t dParam0;
98 uint32_t dParam1;
103 uint32_t dAddr;
108 uint32_t dAddr;
109 uint32_t dSize;
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/hal_rpi_pico-latest/src/rp2350/hardware_structs/include/hardware/structs/
Dm33.h37 uint32_t _pad0[864];
44 uint32_t _pad1[15];
51 uint32_t _pad2[15];
67 uint32_t _pad3[27];
75 uint32_t _pad4;
83 uint32_t _pad5;
90 uint32_t _pad6[46];
101 uint32_t _pad7[3];
188 uint32_t _pad8;
195 uint32_t _pad9;
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