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/hal_rpi_pico-latest/src/rp2040/boot_stage2/
Dboot2_w25q080.S109 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
113 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
114 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
115 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
116 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
122 str r1, [r3, #SSI_SSIENR_OFFSET]
126 str r1, [r3, #SSI_BAUDR_OFFSET]
136 str r1, [r3, r2]
148 str r1, [r3, #SSI_CTRLR0_OFFSET]
152 str r1, [r3, #SSI_SSIENR_OFFSET]
[all …]
Dboot2_at25sf128a.S109 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
113 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
114 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
115 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
116 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
122 str r1, [r3, #SSI_SSIENR_OFFSET]
126 str r1, [r3, #SSI_BAUDR_OFFSET]
136 str r1, [r3, r2]
148 str r1, [r3, #SSI_CTRLR0_OFFSET]
152 str r1, [r3, #SSI_SSIENR_OFFSET]
[all …]
Dboot2_is25lp080.S100 str r1, [r3, #SSI_SSIENR_OFFSET]
104 str r1, [r3, #SSI_BAUDR_OFFSET]
115 str r1, [r3, #SSI_CTRLR0_OFFSET]
119 str r1, [r3, #SSI_SSIENR_OFFSET]
130 str r1, [r3, #SSI_DR0_OFFSET]
138 str r1, [r3, #SSI_DR0_OFFSET]
140 str r2, [r3, #SSI_DR0_OFFSET]
163 str r1, [r3, #SSI_SSIENR_OFFSET]
185 str r1, [r3, #SSI_CTRLR0_OFFSET]
188 str r1, [r3, #SSI_CTRLR1_OFFSET]
[all …]
Dboot2_w25x10cl.S92 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
98 str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock
118 str r1, [r3, #SSI_CTRLR0_OFFSET]
121 str r1, [r3, #SSI_CTRLR1_OFFSET]
133 str r1, [r0]
136 str r1, [r3, #SSI_SSIENR_OFFSET]
139 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
141 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
163 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
182 str r1, [r0]
[all …]
Dboot2_generic_03h.S74 str r1, [r3, #SSI_SSIENR_OFFSET]
78 str r1, [r3, #SSI_BAUDR_OFFSET]
81 str r1, [r3, #SSI_CTRLR0_OFFSET]
85 str r1, [r0]
89 str r1, [r3, #SSI_CTRLR1_OFFSET]
93 str r1, [r3, #SSI_SSIENR_OFFSET]
/hal_rpi_pico-latest/src/rp2350/boot_stage2/
Dboot2_at25sf128a.S105 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
109 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
110 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
111 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
112 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
118 str r1, [r3, #SSI_SSIENR_OFFSET]
122 str r1, [r3, #SSI_BAUDR_OFFSET]
132 str r1, [r3, r2]
144 str r1, [r3, #SSI_CTRLR0_OFFSET]
148 str r1, [r3, #SSI_SSIENR_OFFSET]
[all …]
Dboot2_is25lp080.S96 str r1, [r3, #SSI_SSIENR_OFFSET]
100 str r1, [r3, #SSI_BAUDR_OFFSET]
111 str r1, [r3, #SSI_CTRLR0_OFFSET]
115 str r1, [r3, #SSI_SSIENR_OFFSET]
126 str r1, [r3, #SSI_DR0_OFFSET]
134 str r1, [r3, #SSI_DR0_OFFSET]
136 str r2, [r3, #SSI_DR0_OFFSET]
159 str r1, [r3, #SSI_SSIENR_OFFSET]
181 str r1, [r3, #SSI_CTRLR0_OFFSET]
184 str r1, [r3, #SSI_CTRLR1_OFFSET]
[all …]
Dboot2_w25x10cl.S88 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
94 str r1, [r3, #SSI_BAUDR_OFFSET] // Set SSI Clock
114 str r1, [r3, #SSI_CTRLR0_OFFSET]
117 str r1, [r3, #SSI_CTRLR1_OFFSET]
129 str r1, [r0]
132 str r1, [r3, #SSI_SSIENR_OFFSET]
135 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
137 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
159 str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
178 str r1, [r0]
[all …]
Dboot2_w25q080.S243 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
247 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
248 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
249 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
250 str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
263 str r1, [r3, #QMI_DIRECT_CSR_OFFSET]
280 str r0, [r3, #QMI_DIRECT_TX_OFFSET]
286 str r0, [r3, #QMI_DIRECT_TX_OFFSET]
288 str r0, [r3, #QMI_DIRECT_TX_OFFSET]
290 str r0, [r3, #QMI_DIRECT_TX_OFFSET]
[all …]
Dboot2_generic_03h.S107 str r0, [r3, #QMI_M0_TIMING_OFFSET]
109 str r0, [r3, #QMI_M0_RCMD_OFFSET]
111 str r0, [r3, #QMI_M0_RFMT_OFFSET]
/hal_rpi_pico-latest/src/rp2_common/hardware_divider/
Ddivider.S14 str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET]
15 str r1, [r3, #SIO_DIV_SDIVISOR_OFFSET]
22 str r0, [r3, #SIO_DIV_UDIVIDEND_OFFSET]
23 str r1, [r3, #SIO_DIV_UDIVISOR_OFFSET]
54 str r1, [r3, #SIO_DIV_UDIVIDEND_OFFSET]
55 str r2, [r3, #SIO_DIV_UDIVISOR_OFFSET]
57 str r1, [r3, #SIO_DIV_REMAINDER_OFFSET]
58 str r2, [r3, #SIO_DIV_QUOTIENT_OFFSET]
/hal_rpi_pico-latest/src/rp2_common/hardware_divider/include/hardware/
Ddivider_helper.S63 str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] label
64 str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] label
65 str r7, [r2, #SIO_DIV_REMAINDER_OFFSET] label
66 str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] label
/hal_rpi_pico-latest/src/rp2_common/pico_printf/
Dprintf_none.S21 ldr r0, =str
24 la a0, str
28 str: label
/hal_rpi_pico-latest/tools/
Dcheck_source_files_in_bazel_build.py76 " ".join(shlex.quote(str(arg)) for arg in args),
94 bazel_extensions_to_check: Container[str], argument
139 "\n".join(" " + str(x) for x in sorted(missing_from_bazel)),
145 "\n".join(" " + str(x) for x in sorted(referenced_in_bazel_missing)),
151 def git_ls_files_by_extension(file_suffixes: Iterable[str]) -> Iterable[Path]: argument
185 "Ignoring files:\n\n%s\n", "\n".join(" " + str(f) for f in ignored_files)
Dbazel_common.py53 def bazel_command() -> str:
80 " ".join(shlex.quote(str(arg)) for arg in args),
84 proc.stderr if isinstance(proc.stderr, str) else proc.stderr.decode()
Dcompare_build_systems.py165 name: str
166 description: str
167 attrs: Dict[str, str]
/hal_rpi_pico-latest/bazel/util/
Dlabel_flag_matches.bzl7 matches = str(ctx.attr.expected_value.label) == str(ctx.attr.flag.label)
9 config_common.FeatureFlagInfo(value = str(matches)),
/hal_rpi_pico-latest/src/rp2040/boot_stage2/asminclude/boot2_helpers/
Dread_flash_sreg.S19 str r0, [r3, #SSI_DR0_OFFSET]
21 str r0, [r3, #SSI_DR0_OFFSET]
/hal_rpi_pico-latest/src/rp2_common/pico_float/
Dfloat_none.S74 la a0, str
78 ldr r0, =str
81 str: label
/hal_rpi_pico-latest/src/rp2_common/pico_double/
Ddouble_none.S76 la a0, str
80 ldr r0, =str
84 str: label
/hal_rpi_pico-latest/src/rp2350/boot_stage2/asminclude/boot2_helpers/
Dread_flash_sreg.S36 str r0, [r3, #QMI_DIRECT_TX_OFFSET]
38 str r0, [r3, #QMI_DIRECT_TX_OFFSET]
/hal_rpi_pico-latest/src/rp2_common/pico_divider/
Ddivider_hardware.S84 str r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
85 str r5, [r2, #SIO_DIV_UDIVISOR_OFFSET]
86 str r7, [r2, #SIO_DIV_REMAINDER_OFFSET]
87 str r6, [r2, #SIO_DIV_QUOTIENT_OFFSET]
118 str r0, [r2, #SIO_DIV_SDIVIDEND_OFFSET]
119 str r1, [r2, #SIO_DIV_SDIVISOR_OFFSET]
180 str r0, [r2, #SIO_DIV_UDIVIDEND_OFFSET]
181 str r1, [r2, #SIO_DIV_UDIVISOR_OFFSET]
351 str r0,[r7,#SIO_DIV_UDIVIDEND_OFFSET]
352 str r2,[r7,#SIO_DIV_UDIVISOR_OFFSET]
[all …]
/hal_rpi_pico-latest/src/rp2_common/pico_standard_link/
Dpico_flash_region.bzl8 "FLASH(rx) : ORIGIN = 0x10000000, LENGTH = " + str(ctx.attr.flash_region_size),
14 direct = ["-L" + str(link_include_dir)],
/hal_rpi_pico-latest/src/rp2_common/pico_stdio_usb/
Dstdio_usb_descriptors.c176 const char *str = usbd_desc_str[index]; in tud_descriptor_string_cb() local
177 for (len = 0; len < USBD_DESC_STR_MAX - 1 && str[len]; ++len) { in tud_descriptor_string_cb()
178 desc_str[1 + len] = str[len]; in tud_descriptor_string_cb()
/hal_rpi_pico-latest/tools/pioasm/
Dpio_assembler.h67 throw syntax_error(l, msg.str());
75 throw syntax_error(l, msg.str());
110 throw syntax_error(l, msg.str()); in check_version()

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