Searched refs:ldr (Results 1 – 25 of 35) sorted by relevance
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13 ldr r3, =(SIO_BASE)21 ldr r3, =(SIO_BASE)35 ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET]36 ldr r0, [r3, #SIO_DIV_QUOTIENT_OFFSET]40 ldr r3, =SIO_BASE41 ldr r1, [r3, #SIO_DIV_UDIVIDEND_OFFSET]42 ldr r2, [r3, #SIO_DIV_UDIVISOR_OFFSET]46 ldr r1, [r3, #SIO_DIV_REMAINDER_OFFSET]47 ldr r2, [r3, #SIO_DIV_QUOTIENT_OFFSET]52 ldr r3, =SIO_BASE
38 ldr r0, =aeabi_bits_funcs40 ldr r3, =rom_funcs_lookup52 ldr r3, =aeabi_bits_funcs53 ldr r3, [r3, #CLZ32]58 ldr r3, =aeabi_bits_funcs59 ldr r3, [r3, #CTZ32]64 ldr r3, =aeabi_bits_funcs65 ldr r3, [r3, #POPCOUNT32]71 ldr r3, =aeabi_bits_funcs72 ldr r3, [r3, #CLZ32][all …]
45 ldr r0, =aeabi_mem_funcs47 ldr r3, =rom_funcs_lookup65 ldr r3, =aeabi_mem_funcs66 ldr r3, [r3, #MEMSET]75 ldr r3, =aeabi_mem_funcs76 ldr r3, [r3, #MEMSET4]81 ldr r3, =aeabi_mem_funcs82 ldr r3, [r3, #MEMCPY4]88 ldr r3, =aeabi_mem_funcs89 ldr r3, [r3, #MEMSET][all …]
96 ldr r3, =XIP_SSI_BASE // Use as base address where possible114 ldr r1, =(CTRL0_SPI_TXRX)122 ldr r0, =CMD_READ_STATUS124 ldr r2, =SREG_DATA134 ldr r1, [r3, #SSI_DR0_OFFSET]143 ldr r1, [r3, #SSI_DR0_OFFSET]144 ldr r1, [r3, #SSI_DR0_OFFSET]148 ldr r0, =CMD_READ_STATUS184 ldr r1, =(CTRLR0_ENTER_XIP)198 ldr r1, =(SPI_CTRLR0_ENTER_XIP)[all …]
107 ldr r3, =PADS_QSPI_BASE110 ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]118 ldr r3, =XIP_SSI_BASE147 ldr r1, =(CTRL0_SPI_TXRX)167 ldr r1, [r3, #SSI_DR0_OFFSET]175 ldr r1, [r3, #SSI_DR0_OFFSET]176 ldr r1, [r3, #SSI_DR0_OFFSET]177 ldr r1, [r3, #SSI_DR0_OFFSET]208 ldr r1, =(CTRLR0_ENTER_XIP)222 ldr r1, =(SPI_CTRLR0_ENTER_XIP)[all …]
107 ldr r3, =PADS_QSPI_BASE110 ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]118 ldr r3, =XIP_SSI_BASE147 ldr r1, =(CTRL0_SPI_TXRX)167 ldr r1, [r3, #SSI_DR0_OFFSET]177 ldr r1, [r3, #SSI_DR0_OFFSET]178 ldr r1, [r3, #SSI_DR0_OFFSET]179 ldr r1, [r3, #SSI_DR0_OFFSET]210 ldr r1, =(CTRLR0_ENTER_XIP)224 ldr r1, =(SPI_CTRLR0_ENTER_XIP)[all …]
87 ldr r3, =XIP_SSI_BASE // Use as base address where possible117 ldr r1, =(CTRLR0_ENTER_XIP)131 ldr r1, =(SPI_CTRLR0_ENTER_XIP)132 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register148 ldr r0, [r3, #SSI_SR_OFFSET] // Read status register180 ldr r1, =(SPI_CTRLR0_XIP)181 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
70 ldr r3, =XIP_SSI_BASE // Use as base address where possible80 ldr r1, =(CTRLR0_XIP)83 ldr r1, =(SPI_CTRLR0_XIP)84 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
32 ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot38 ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use
92 ldr r3, =XIP_SSI_BASE // Use as base address where possible110 ldr r1, =(CTRL0_SPI_TXRX)118 ldr r0, =CMD_READ_STATUS120 ldr r2, =SREG_DATA130 ldr r1, [r3, #SSI_DR0_OFFSET]139 ldr r1, [r3, #SSI_DR0_OFFSET]140 ldr r1, [r3, #SSI_DR0_OFFSET]144 ldr r0, =CMD_READ_STATUS180 ldr r1, =(CTRLR0_ENTER_XIP)194 ldr r1, =(SPI_CTRLR0_ENTER_XIP)[all …]
103 ldr r3, =PADS_QSPI_BASE106 ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]114 ldr r3, =XIP_SSI_BASE143 ldr r1, =(CTRL0_SPI_TXRX)163 ldr r1, [r3, #SSI_DR0_OFFSET]171 ldr r1, [r3, #SSI_DR0_OFFSET]172 ldr r1, [r3, #SSI_DR0_OFFSET]173 ldr r1, [r3, #SSI_DR0_OFFSET]204 ldr r1, =(CTRLR0_ENTER_XIP)218 ldr r1, =(SPI_CTRLR0_ENTER_XIP)[all …]
83 ldr r3, =XIP_SSI_BASE // Use as base address where possible113 ldr r1, =(CTRLR0_ENTER_XIP)127 ldr r1, =(SPI_CTRLR0_ENTER_XIP)128 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register144 ldr r0, [r3, #SSI_SR_OFFSET] // Read status register176 ldr r1, =(SPI_CTRLR0_XIP)177 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
241 ldr r3, =PADS_QSPI_BASE262 ldr r1, =INIT_DIRECT_CSR268 ldr r0, [r3, #QMI_DIRECT_CSR_OFFSET]282 ldr r0, [r3, #QMI_DIRECT_RX_OFFSET]292 ldr r0, [r3, #QMI_DIRECT_RX_OFFSET]293 ldr r0, [r3, #QMI_DIRECT_RX_OFFSET]294 ldr r0, [r3, #QMI_DIRECT_RX_OFFSET]311 ldr r0, =INIT_M0_TIMING313 ldr r0, =INIT_M0_RCMD315 ldr r0, =INIT_M0_RFMT
105 ldr r3, =XIP_QMI_BASE106 ldr r0, =INIT_M0_TIMING108 ldr r0, =INIT_M0_RCMD110 ldr r0, =INIT_M0_RFMT
33 ldr r1, =('U' | ('B' << 8)) // Symbol for USB Boot39 ldr r0, =(1u << ACTIVITY_LED) // Mask of which GPIO (or GPIOs) to use
37 ldr r4, [r2, #SIO_DIV_UDIVIDEND_OFFSET] label38 ldr r5, [r2, #SIO_DIV_UDIVISOR_OFFSET] label39 ldr r7, [r2, #SIO_DIV_REMAINDER_OFFSET] label40 ldr r6, [r2, #SIO_DIV_QUOTIENT_OFFSET] label
56 ldr r6, =SIO_BASE58 ldr r4, [r6, #SIO_DIV_UDIVIDEND_OFFSET]59 ldr r5, [r6, #SIO_DIV_UDIVISOR_OFFSET]61 ldr r7, [r6, #SIO_DIV_REMAINDER_OFFSET]62 ldr r6, [r6, #SIO_DIV_QUOTIENT_OFFSET]81 ldr r2, =SIO_BASE103 ldr r2, =SIO_BASE104 ldr r3, [r2, #SIO_DIV_CSR_OFFSET]114 ldr r2, =SIO_BASE124 ldr r1, [r2, #SIO_DIV_REMAINDER_OFFSET][all …]
92 ldr r3, =sd_table93 ldr r3, [r3, #\SF_TABLE_OFFSET]100 ldr r3, =sd_table101 ldr r3, [r3, #\SF_TABLE_OFFSET]184 ldr r2, =(SIO_BASE)185 ldr r2, [r2, #SIO_DIV_CSR_OFFSET]203 ldr r2, =(SIO_BASE)207 ldr r2, =(SIO_BASE)222 ldr r2, [sp, #4]223 ldr r3, [sp, #12][all …]
343 ldr r0, = PPB_BASE + M33_CPACR_OFFSET356 ldr r0, =__vectors362 ldr r0, =BOOTROM_VTABLE_OFFSET366 ldr r1, =(PPB_BASE + ARM_CPU_PREFIXED(VTOR_OFFSET))385 ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET)386 ldr r0, [r0]395 ldr r0, =BOOTROM_VTABLE_OFFSET405 ldr r1, =__boot2_entry_point433 ldr r1, =__bss_start__434 ldr r2, =__bss_end__[all …]
52 ldr r0, [r0]54 ldr r2, =sf_table106 ldr r1, =0x29ef // packx115 ldr r4, =0x29c1 // unpackx148 ldr r3, =0x2cfc @ &pi_q29, circular coefficients149 ldr r0,[r3] @ x negative, return +/- pi158 ldr r3, =0x2cfc @ &pi_q29, circular coefficients163 ldr r2,[r3] @ pi Q29166 ldr r5, =0x2b97 @ cordic_vec171 ldr r3, =0x2cfc @ &pi_q29, circular coefficients[all …]
88 ldr r3, =sf_table89 ldr r3, [r3, #\SF_TABLE_OFFSET]94 ldr r3, =sf_table95 ldr r3, [r3, #\SF_TABLE_OFFSET]151 ldr r2, =(SIO_BASE)152 ldr r3, [r2, #SIO_DIV_CSR_OFFSET]170 ldr r2, =(SIO_BASE)390 ldr r3, =sf_clz_func391 ldr r3, [r3]507 ldr r2, =__aeabi_i2f[all …]
21 ldr r0, =(XIP_BASE + 0x100)22 ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
25 ldr r0, [r3, #SSI_DR0_OFFSET]26 ldr r0, [r3, #SSI_DR0_OFFSET]
42 ldr r0, [r3, #QMI_DIRECT_RX_OFFSET]43 ldr r0, [r3, #QMI_DIRECT_RX_OFFSET]
70 ldr r0, [r1, #4] // Get `handler` field of irq_handler_chain_slot85 ldr r1, =irq_add_tail_to_free_list
