| /hal_rpi_pico-latest/src/rp2_common/hardware_rtc/ |
| D | rtc.c | 110 hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); in rtc_enable_alarm()
159 if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS); in rtc_set_alarm()
160 if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS); in rtc_set_alarm()
161 if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS); in rtc_set_alarm()
162 if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS); in rtc_set_alarm()
163 if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS); in rtc_set_alarm()
164 if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS); in rtc_set_alarm()
165 if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS); in rtc_set_alarm()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_watchdog/ |
| D | watchdog.c | 48 hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS)); in _watchdog_enable()
55 hw_set_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
61 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS); in _watchdog_enable()
72 hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_vreg/ |
| D | vreg.c | 21 hw_set_bits(&powman_hw->vreg_ctrl, POWMAN_PASSWORD_BITS | POWMAN_VREG_CTRL_UNLOCK_BITS); in vreg_set_voltage()
46 …hw_set_bits(&powman_hw->vreg_ctrl, POWMAN_PASSWORD_BITS | POWMAN_VREG_CTRL_DISABLE_VOLTAGE_LIMIT_B… in vreg_disable_voltage_limit()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_dma/include/hardware/ |
| D | dma.h | 562 hw_set_bits(&dma_hw->inte0, 1u << channel); in dma_channel_set_irq0_enabled()
575 hw_set_bits(&dma_hw->inte0, channel_mask); in dma_set_irq0_channel_mask_enabled()
591 hw_set_bits(&dma_hw->inte1, 1u << channel); in dma_channel_set_irq1_enabled()
604 hw_set_bits(&dma_hw->inte1, channel_mask); in dma_set_irq1_channel_mask_enabled()
621 hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel); in dma_irqn_set_channel_enabled()
636 hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask); in dma_irqn_set_channel_mask_enabled()
755 hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS); in dma_sniffer_enable()
779 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); in dma_sniffer_set_byte_swap_enabled()
794 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS); in dma_sniffer_set_output_invert_enabled()
809 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS); in dma_sniffer_set_output_reverse_enabled()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_pwm/include/hardware/ |
| D | pwm.h | 416 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS); in pwm_advance_count()
433 hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS); in pwm_retard_count()
600 hw_set_bits(&pwm_hw->inte, 1u << slice_num); in pwm_set_irq_enabled()
631 hw_set_bits(&pwm_hw->inte1, 1u << slice_num); in pwm_set_irq1_enabled()
654 hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num); in pwm_irqn_set_slice_enabled()
674 hw_set_bits(&pwm_hw->inte, slice_mask); in pwm_set_irq_mask_enabled()
682 hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); in pwm_set_irq_mask_enabled()
713 hw_set_bits(&pwm_hw->inte1, slice_mask); in pwm_set_irq1_mask_enabled()
734 hw_set_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); in pwm_irqn_set_slice_mask_enabled()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_adc/include/hardware/ |
| D | adc.h | 163 hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); in adc_set_temp_sensor_enabled()
176 hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS); in pico_adc_read()
191 hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); in adc_run()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_sha256/include/hardware/ |
| D | sha256.h | 93 hw_set_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); in sha256_set_bswap()
105 hw_set_bits(&sha256_hw->csr, SHA256_CSR_START_BITS); in sha256_start()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_spi/include/hardware/ |
| D | spi.h | 264 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); in spi_set_format()
282 hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); in spi_set_slave()
287 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); in spi_set_slave()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_pio/include/hardware/ |
| D | pio.h | 1074 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_SM_RESTART_LSB + sm)); in pio_sm_restart()
1089 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS); in pio_restart_sm_mask()
1116 hw_set_bits(&pio->ctrl, 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm)); in pio_sm_clkdiv_restart()
1151 hw_set_bits(&pio->ctrl, (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS); in pio_clkdiv_restart_sm_mask()
1189 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | in pio_clkdiv_restart_sm_multi_mask()
1210 hw_set_bits(&pio->ctrl, in pio_enable_sm_mask_in_sync()
1234 hw_set_bits(&pio->ctrl, ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) | in pio_enable_sm_multi_mask_in_sync()
1277 hw_set_bits(&pio->inte0, 1u << source); in pio_set_irq0_source_enabled()
1293 hw_set_bits(&pio->inte1, 1u << source); in pio_set_irq1_source_enabled()
1309 hw_set_bits(&pio->inte0, source_mask); in pio_set_irq0_source_mask_enabled()
[all …]
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| /hal_rpi_pico-latest/src/rp2_common/pico_time_adapter/include/pico/ |
| D | time_adapter.h | 20 hw_set_bits(&timer_hw_from_timer(timer)->intf, 1u << alarm_num); in ta_force_irq()
73 hw_set_bits(&timer_hw_from_timer(timer)->inte, 1u << alarm_num); in ta_enable_irq_handler()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_gpio/ |
| D | gpio.c | 30 hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); in gpio_get_pad()
109 hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); in gpio_set_input_hysteresis_enabled()
181 hw_set_bits(en_reg, events); in _gpio_set_irq_enabled()
281 hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); in gpio_set_input_enabled()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_spi/ |
| D | spi.c | 28 hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); in spi_init()
31 hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); in spi_init()
70 hw_set_bits(&spi_get_hw(spi)->cr1, enable_mask); in spi_set_baudrate()
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| /hal_rpi_pico-latest/src/rp2_common/pico_stdio_uart/ |
| D | stdio_uart.c | 136 if (tx_pin >= 0) hw_set_bits(&pads_bank0_hw->io[tx_pin], PADS_BANK0_GPIO0_ISO_BITS); in stdio_uart_deinit_full()
137 if (rx_pin >= 0) hw_set_bits(&pads_bank0_hw->io[rx_pin], PADS_BANK0_GPIO0_ISO_BITS); in stdio_uart_deinit_full()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_xosc/ |
| D | xosc.c | 37 hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB); in xosc_init()
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| /hal_rpi_pico-latest/src/rp2_common/pico_bootsel_via_double_reset/ |
| D | pico_bootsel_via_double_reset.c | 100 hw_set_bits(&powman_hw->chip_reset, POWMAN_CHIP_RESET_DOUBLE_TAP_BITS); in set_double_tap_flag()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_resets/include/hardware/ |
| D | resets.h | 72 hw_set_bits(reset, mask); in reset_block_reg_mask()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_powman/include/hardware/ |
| D | powman.h | 108 hw_set_bits(reg, POWMAN_PASSWORD_BITS | bits); in powman_set_bits()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_base/include/hardware/ |
| D | address_mapped.h | 135 __force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) { in hw_set_bits() function
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| /hal_rpi_pico-latest/src/rp2_common/pico_runtime_init/ |
| D | runtime_init.c | 101 hw_set_bits(&usb_hw->sie_ctrl, USB_SIE_CTRL_TRANSCEIVER_PD_BITS); in runtime_init_usb_power_down()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_timer/ |
| D | timer.c | 202 hw_set_bits(&timer->inte, 1u << alarm_num); in timer_hardware_alarm_set_callback()
289 hw_set_bits(&timer->intf, 1u << alarm_num); in timer_hardware_alarm_force_irq()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_flash/ |
| D | flash.c | 200 hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS); in __no_inline_not_in_flash_func()
243 hw_set_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); in __no_inline_not_in_flash_func()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_clocks/ |
| D | clocks.c | 90 hw_set_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure_internal()
178 hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); in clocks_handle_resus()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_uart/ |
| D | uart.c | 68 hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS); in uart_init()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_gpio/include/hardware/ |
| D | gpio.h | 1395 if (ns) hw_set_bits(&accessctrl_hw->gpio_nsmask[gpio/32], 1u << (gpio & 0x1fu)); in gpio_assign_to_ns()
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| /hal_rpi_pico-latest/src/rp2_common/pico_cyw43_driver/ |
| D | cyw43_bus_pio_spi.c | 142 …hw_set_bits(&bus_data->pio->input_sync_bypass, 1u << (CYW43_PIN_WL_DATA_IN - pio_get_gpio_base(bus… in cyw43_spi_init()
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