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Searched refs:hw_clear_bits (Results 1 – 25 of 26) sorted by relevance

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/hal_rpi_pico-latest/src/rp2_common/hardware_watchdog/
Dwatchdog.c45 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in _watchdog_enable()
57 hw_clear_bits(&watchdog_hw->ctrl, dbg_bits); in _watchdog_enable()
87 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in watchdog_disable()
94 hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS); in watchdog_reboot()
/hal_rpi_pico-latest/src/rp2_common/hardware_dma/include/hardware/
Ddma.h564 hw_clear_bits(&dma_hw->inte0, 1u << channel); in dma_channel_set_irq0_enabled()
577 hw_clear_bits(&dma_hw->inte0, channel_mask); in dma_set_irq0_channel_mask_enabled()
593 hw_clear_bits(&dma_hw->inte1, 1u << channel); in dma_channel_set_irq1_enabled()
606 hw_clear_bits(&dma_hw->inte1, channel_mask); in dma_set_irq1_channel_mask_enabled()
623 hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel); in dma_irqn_set_channel_enabled()
638 hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask); in dma_irqn_set_channel_mask_enabled()
781 hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS); in dma_sniffer_set_byte_swap_enabled()
796 hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS); in dma_sniffer_set_output_invert_enabled()
811 hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS); in dma_sniffer_set_output_reverse_enabled()
/hal_rpi_pico-latest/src/rp2_common/hardware_ticks/
Dticks.c30 hw_clear_bits(&watchdog_hw->tick, WATCHDOG_TICK_ENABLE_BITS); in tick_stop()
32 hw_clear_bits(&ticks_hw->ticks[tick].ctrl, TICKS_WATCHDOG_CTRL_ENABLE_BITS); in tick_stop()
/hal_rpi_pico-latest/src/rp2_common/hardware_pll/
Dpll.c60 hw_clear_bits(&pll->pwr, power); in pll_init()
69 hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS); in pll_init()
/hal_rpi_pico-latest/src/rp2_common/hardware_sha256/include/hardware/
Dsha256.h95 hw_clear_bits(&sha256_hw->csr, SHA256_CSR_BSWAP_BITS); in sha256_set_bswap()
184 hw_clear_bits(&sha256_hw->csr, SHA256_CSR_ERR_WDATA_NOT_RDY_BITS); in sha256_err_not_ready_clear()
/hal_rpi_pico-latest/src/rp2_common/pico_runtime_init/
Druntime_init_clocks.c58 hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); in runtime_init_clocks()
61 hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in runtime_init_clocks()
/hal_rpi_pico-latest/src/rp2_common/hardware_pwm/include/hardware/
Dpwm.h602 hw_clear_bits(&pwm_hw->inte, 1u << slice_num); in pwm_set_irq_enabled()
633 hw_clear_bits(&pwm_hw->inte1, 1u << slice_num); in pwm_set_irq1_enabled()
656 hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, 1u << slice_num); in pwm_irqn_set_slice_enabled()
676 hw_clear_bits(&pwm_hw->inte, slice_mask); in pwm_set_irq_mask_enabled()
684 hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); in pwm_set_irq_mask_enabled()
715 hw_clear_bits(&pwm_hw->inte1, slice_mask); in pwm_set_irq1_mask_enabled()
736 hw_clear_bits(&pwm_hw->irq_ctrl[irq_index].inte, slice_mask); in pwm_irqn_set_slice_mask_enabled()
/hal_rpi_pico-latest/src/rp2_common/hardware_resets/include/hardware/
Dresets.h76 hw_clear_bits(reset, mask); in unreset_block_reg_mask()
80 hw_clear_bits(reset, mask); in unreset_block_reg_mask_wait_blocking()
/hal_rpi_pico-latest/src/rp2_common/hardware_spi/include/hardware/
Dspi.h253 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); in spi_set_format()
279 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); in spi_set_slave()
284 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS); in spi_set_slave()
/hal_rpi_pico-latest/src/rp2_common/hardware_adc/include/hardware/
Dadc.h165 hw_clear_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS); in adc_set_temp_sensor_enabled()
193 hw_clear_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS); in adc_run()
/hal_rpi_pico-latest/src/rp2_common/pico_time_adapter/include/pico/
Dtime_adapter.h24 hw_clear_bits(&timer_hw_from_timer(timer)->intf, 1u << alarm_num); in ta_clear_force_irq()
78 hw_clear_bits(&timer_hw_from_timer(timer)->inte, 1u << alarm_num); in ta_disable_irq_handler()
/hal_rpi_pico-latest/src/rp2_common/hardware_gpio/
Dgpio.c51 hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_ISO_BITS); in gpio_set_function()
111 hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS); in gpio_set_input_hysteresis_enabled()
183 hw_clear_bits(en_reg, events); in _gpio_set_irq_enabled()
283 hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS); in gpio_set_input_enabled()
/hal_rpi_pico-latest/src/rp2_common/hardware_spi/
Dspi.c37 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); in spi_deinit()
38 hw_clear_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS); in spi_deinit()
49 hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS); in spi_set_baudrate()
/hal_rpi_pico-latest/src/rp2_common/hardware_clocks/
Dclocks.c35 hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS); in clock_stop()
53 hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); in clock_configure_internal()
63 hw_clear_bits(&clock_hw->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); in clock_configure_internal()
179 hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS); in clocks_handle_resus()
/hal_rpi_pico-latest/src/rp2_common/pico_bootsel_via_double_reset/
Dpico_bootsel_via_double_reset.c104 hw_clear_bits(&powman_hw->chip_reset, POWMAN_CHIP_RESET_DOUBLE_TAP_BITS); in clear_double_tap_flag()
/hal_rpi_pico-latest/src/rp2_common/pico_fix/rp2040_usb_device_enumeration/
Drp2040_usb_device_enumeration.c142 …hw_clear_bits(&usb_hw->phy_direct_override, USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BI… in hw_enumeration_fix_finish()
/hal_rpi_pico-latest/src/rp2_common/hardware_powman/include/hardware/
Dpowman.h122 hw_clear_bits(reg, POWMAN_PASSWORD_BITS | bits); in powman_clear_bits()
/hal_rpi_pico-latest/src/rp2_common/hardware_base/include/hardware/
Daddress_mapped.h145 __force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) { in hw_clear_bits() function
/hal_rpi_pico-latest/src/rp2_common/hardware_pio/
Dpio.c226 hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); in pio_sm_set_pins_internal()
266 hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); in pio_sm_set_pins_with_mask_internal()
303 hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); in pio_sm_set_pindirs_with_mask_internal()
341 hw_clear_bits(&pio->sm[sm].execctrl, 1u << PIO_SM0_EXECCTRL_OUT_STICKY_LSB); in pio_sm_set_consecutive_pindirs()
/hal_rpi_pico-latest/src/rp2_common/hardware_flash/
Dflash.c198 hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_ASSERT_CS0N_BITS); in __no_inline_not_in_flash_func()
257 hw_clear_bits(&qmi_hw->direct_csr, QMI_DIRECT_CSR_EN_BITS); in __no_inline_not_in_flash_func()
/hal_rpi_pico-latest/src/rp2_common/hardware_pio/include/hardware/
Dpio.h1279 hw_clear_bits(&pio->inte0, 1u << source); in pio_set_irq0_source_enabled()
1295 hw_clear_bits(&pio->inte1, 1u << source); in pio_set_irq1_source_enabled()
1311 hw_clear_bits(&pio->inte0, source_mask); in pio_set_irq0_source_mask_enabled()
1328 hw_clear_bits(&pio->inte1, source_mask); in pio_set_irq1_source_mask_enabled()
1346 hw_clear_bits(&pio->irq_ctrl[irq_index].inte, 1u << source); in pio_set_irqn_source_enabled()
1364 hw_clear_bits(&pio->irq_ctrl[irq_index].inte, source_mask); in pio_set_irqn_source_mask_enabled()
/hal_rpi_pico-latest/src/rp2_common/hardware_rtc/
Drtc.c186 hw_clear_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS); in rtc_disable_alarm()
/hal_rpi_pico-latest/src/rp2_common/pico_aon_timer/
Daon_timer.c219 hw_clear_bits(&rtc_hw->ctrl, RTC_CTRL_RTC_ENABLE_BITS); in aon_timer_stop()
/hal_rpi_pico-latest/src/rp2_common/hardware_uart/
Duart.c124 hw_clear_bits(&uart_get_hw(uart)->cr, in uart_disable_before_lcr_write()
/hal_rpi_pico-latest/src/rp2_common/hardware_timer/
Dtimer.c166 hw_clear_bits(&timer->intf, 1u << alarm_num); in hardware_alarm_irq_handler()

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