Searched refs:hazard3_irqarray_clear (Results 1 – 3 of 3) sorted by relevance
| /hal_rpi_pico-latest/src/rp2_common/hardware_hazard3/include/hardware/ |
| D | hazard3.h | 51 #define hazard3_irqarray_clear(csr, index, data) (riscv_clear_csr(csr, (index) | ((uint32_t)(data) … macro
53 #define hazard3_irqarray_clear(csr, index, data) static_assert(false, "Not supported: Xh3irq extens…
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| /hal_rpi_pico-latest/src/rp2_common/hardware_irq/ |
| D | irq.c | 82 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
83 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
87 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
88 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
595 hazard3_irqarray_clear(RVCSR_MEIPRA_OFFSET, num / 4, 0xfu << (4 * (num % 4))); in irq_set_priority()
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| /hal_rpi_pico-latest/src/rp2_common/hardware_irq/include/hardware/ |
| D | irq.h | 383 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16)); in irq_clear()
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