Searched refs:__IOM (Results 1 – 4 of 4) sorted by relevance
133 #ifndef __IOM /*!< Fallback for older CMSIS versions …134 #define __IOM __IO macro159 …__IOM uint32_t RESET; /*!< RESET …160 …__IOM uint32_t WDSEL; /*!< WDSEL …161 …__IOM uint32_t RESET_DONE; /*!< RESET_DONE …176 …__IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) …177 …__IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) …178 …__IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this …179 …__IOM uint32_t DONE; /*!< Is the subsystem ready? …194 …__IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (excep…[all …]
105 #ifndef __IOM /*!< Fallback for older CMSIS versions …106 #define __IOM __IO macro131 …__IOM uint32_t RESET; /*!< Reset control. If a bit is set it means the per…133 …__IOM uint32_t WDSEL; /*!< Watchdog select. If a bit is set then the watch…135 …__IOM uint32_t RESET_DONE; /*!< Reset done. If a bit is set then a reset done s…152 …__IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) …153 …__IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) …154 …__IOM uint32_t WDSEL; /*!< Set to 1 if this peripheral should be reset whe…156 …__IOM uint32_t DONE; /*!< Indicates the peripheral's registers are ready …171 …__IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (excep…[all …]
305 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro487 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */489 …__IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */491 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */493 …__IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …495 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */497 …__IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Regist…499 …__IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…524 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…525 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */[all …]
181 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro331 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */333 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */335 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */337 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …340 __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */359 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…361 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */365 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…366 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */[all …]
