Searched refs:__IM (Results 1 – 4 of 4) sorted by relevance
127 #ifndef __IM /*!< Fallback for older CMSIS versions …128 #define __IM __I macro401 __IM uint32_t RESERVED[112];528 __IM uint32_t RESERVED[32];620 __IM uint32_t RESERVED[2];760 __IM uint32_t RESERVED[864];762 __IM uint32_t RESERVED1[15];765 __IM uint32_t RESERVED2[15];767 __IM uint32_t RESERVED3[27];769 __IM uint32_t RESERVED4;[all …]
303 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro523 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */537 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */538 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */539 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */540 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */541 …__IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…542 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */543 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */544 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */[all …]
179 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro358 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */478 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */527 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
99 #ifndef __IM /*!< Fallback for older CMSIS versions …100 #define __IM __I macro472 __IM uint32_t RESERVED[2];488 __IM uint32_t RESERVED[14340];505 __IM uint32_t RESERVED1[56];513 __IM uint32_t RESERVED2[31];516 __IM uint32_t RESERVED3[31];519 __IM uint32_t RESERVED4[31];522 __IM uint32_t RESERVED5[95];549 __IM uint32_t RESERVED6[568];[all …]
