Home
last modified time | relevance | path

Searched refs:XIP_SSI_BASE (Results 1 – 10 of 10) sorted by relevance

/hal_rpi_pico-latest/src/rp2040/boot_stage2/
Dboot2_w25x10cl.S87 ldr r3, =XIP_SSI_BASE // Use as base address where possible
132 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
181 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_generic_03h.S70 ldr r3, =XIP_SSI_BASE // Use as base address where possible
84 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_is25lp080.S96 ldr r3, =XIP_SSI_BASE // Use as base address where possible
199 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
242 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_at25sf128a.S118 ldr r3, =XIP_SSI_BASE
223 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
260 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_w25q080.S118 ldr r3, =XIP_SSI_BASE
225 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
262 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
/hal_rpi_pico-latest/src/rp2350/boot_stage2/
Dboot2_w25x10cl.S83 ldr r3, =XIP_SSI_BASE // Use as base address where possible
128 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
177 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_is25lp080.S92 ldr r3, =XIP_SSI_BASE // Use as base address where possible
195 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
238 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_at25sf128a.S114 ldr r3, =XIP_SSI_BASE
219 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
256 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dssi.h211 #define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE)
/hal_rpi_pico-latest/src/rp2040/hardware_regs/include/hardware/regs/
Daddressmap.h32 #define XIP_SSI_BASE _u(0x18000000) macro