1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : XIP
10 // Version        : 1
11 // Bus type       : ahb
12 // Description    : QSPI flash execute-in-place block
13 // =============================================================================
14 #ifndef _HARDWARE_REGS_XIP_H
15 #define _HARDWARE_REGS_XIP_H
16 // =============================================================================
17 // Register    : XIP_CTRL
18 // Description : Cache control
19 #define XIP_CTRL_OFFSET _u(0x00000000)
20 #define XIP_CTRL_BITS   _u(0x0000000b)
21 #define XIP_CTRL_RESET  _u(0x00000003)
22 // -----------------------------------------------------------------------------
23 // Field       : XIP_CTRL_POWER_DOWN
24 // Description : When 1, the cache memories are powered down. They retain state,
25 //               but can not be accessed. This reduces static power dissipation.
26 //               Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
27 //               cannot
28 //               be enabled when powered down.
29 //               Cache-as-SRAM accesses will produce a bus error response when
30 //               the cache is powered down.
31 #define XIP_CTRL_POWER_DOWN_RESET  _u(0x0)
32 #define XIP_CTRL_POWER_DOWN_BITS   _u(0x00000008)
33 #define XIP_CTRL_POWER_DOWN_MSB    _u(3)
34 #define XIP_CTRL_POWER_DOWN_LSB    _u(3)
35 #define XIP_CTRL_POWER_DOWN_ACCESS "RW"
36 // -----------------------------------------------------------------------------
37 // Field       : XIP_CTRL_ERR_BADWRITE
38 // Description : When 1, writes to any alias other than 0x0 (caching,
39 //               allocating)
40 //               will produce a bus fault. When 0, these writes are silently
41 //               ignored.
42 //               In either case, writes to the 0x0 alias will deallocate on tag
43 //               match,
44 //               as usual.
45 #define XIP_CTRL_ERR_BADWRITE_RESET  _u(0x1)
46 #define XIP_CTRL_ERR_BADWRITE_BITS   _u(0x00000002)
47 #define XIP_CTRL_ERR_BADWRITE_MSB    _u(1)
48 #define XIP_CTRL_ERR_BADWRITE_LSB    _u(1)
49 #define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
50 // -----------------------------------------------------------------------------
51 // Field       : XIP_CTRL_EN
52 // Description : When 1, enable the cache. When the cache is disabled, all XIP
53 //               accesses
54 //               will go straight to the flash, without querying the cache. When
55 //               enabled,
56 //               cacheable XIP accesses will query the cache, and the flash will
57 //               not be accessed if the tag matches and the valid bit is set.
58 //
59 //               If the cache is enabled, cache-as-SRAM accesses have no effect
60 //               on the
61 //               cache data RAM, and will produce a bus error response.
62 #define XIP_CTRL_EN_RESET  _u(0x1)
63 #define XIP_CTRL_EN_BITS   _u(0x00000001)
64 #define XIP_CTRL_EN_MSB    _u(0)
65 #define XIP_CTRL_EN_LSB    _u(0)
66 #define XIP_CTRL_EN_ACCESS "RW"
67 // =============================================================================
68 // Register    : XIP_FLUSH
69 // Description : Cache Flush control
70 //               Write 1 to flush the cache. This clears the tag memory, but
71 //               the data memory retains its contents. (This means cache-as-SRAM
72 //               contents is not affected by flush or reset.)
73 //               Reading will hold the bus (stall the processor) until the flush
74 //               completes. Alternatively STAT can be polled until completion.
75 #define XIP_FLUSH_OFFSET _u(0x00000004)
76 #define XIP_FLUSH_BITS   _u(0x00000001)
77 #define XIP_FLUSH_RESET  _u(0x00000000)
78 #define XIP_FLUSH_MSB    _u(0)
79 #define XIP_FLUSH_LSB    _u(0)
80 #define XIP_FLUSH_ACCESS "SC"
81 // =============================================================================
82 // Register    : XIP_STAT
83 // Description : Cache Status
84 #define XIP_STAT_OFFSET _u(0x00000008)
85 #define XIP_STAT_BITS   _u(0x00000007)
86 #define XIP_STAT_RESET  _u(0x00000002)
87 // -----------------------------------------------------------------------------
88 // Field       : XIP_STAT_FIFO_FULL
89 // Description : When 1, indicates the XIP streaming FIFO is completely full.
90 //               The streaming FIFO is 2 entries deep, so the full and empty
91 //               flag allow its level to be ascertained.
92 #define XIP_STAT_FIFO_FULL_RESET  _u(0x0)
93 #define XIP_STAT_FIFO_FULL_BITS   _u(0x00000004)
94 #define XIP_STAT_FIFO_FULL_MSB    _u(2)
95 #define XIP_STAT_FIFO_FULL_LSB    _u(2)
96 #define XIP_STAT_FIFO_FULL_ACCESS "RO"
97 // -----------------------------------------------------------------------------
98 // Field       : XIP_STAT_FIFO_EMPTY
99 // Description : When 1, indicates the XIP streaming FIFO is completely empty.
100 #define XIP_STAT_FIFO_EMPTY_RESET  _u(0x1)
101 #define XIP_STAT_FIFO_EMPTY_BITS   _u(0x00000002)
102 #define XIP_STAT_FIFO_EMPTY_MSB    _u(1)
103 #define XIP_STAT_FIFO_EMPTY_LSB    _u(1)
104 #define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
105 // -----------------------------------------------------------------------------
106 // Field       : XIP_STAT_FLUSH_READY
107 // Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
108 //               The cache is flushed whenever the XIP block is reset, and also
109 //               when requested via the FLUSH register.
110 #define XIP_STAT_FLUSH_READY_RESET  _u(0x0)
111 #define XIP_STAT_FLUSH_READY_BITS   _u(0x00000001)
112 #define XIP_STAT_FLUSH_READY_MSB    _u(0)
113 #define XIP_STAT_FLUSH_READY_LSB    _u(0)
114 #define XIP_STAT_FLUSH_READY_ACCESS "RO"
115 // =============================================================================
116 // Register    : XIP_CTR_HIT
117 // Description : Cache Hit counter
118 //               A 32 bit saturating counter that increments upon each cache
119 //               hit,
120 //               i.e. when an XIP access is serviced directly from cached data.
121 //               Write any value to clear.
122 #define XIP_CTR_HIT_OFFSET _u(0x0000000c)
123 #define XIP_CTR_HIT_BITS   _u(0xffffffff)
124 #define XIP_CTR_HIT_RESET  _u(0x00000000)
125 #define XIP_CTR_HIT_MSB    _u(31)
126 #define XIP_CTR_HIT_LSB    _u(0)
127 #define XIP_CTR_HIT_ACCESS "WC"
128 // =============================================================================
129 // Register    : XIP_CTR_ACC
130 // Description : Cache Access counter
131 //               A 32 bit saturating counter that increments upon each XIP
132 //               access,
133 //               whether the cache is hit or not. This includes noncacheable
134 //               accesses.
135 //               Write any value to clear.
136 #define XIP_CTR_ACC_OFFSET _u(0x00000010)
137 #define XIP_CTR_ACC_BITS   _u(0xffffffff)
138 #define XIP_CTR_ACC_RESET  _u(0x00000000)
139 #define XIP_CTR_ACC_MSB    _u(31)
140 #define XIP_CTR_ACC_LSB    _u(0)
141 #define XIP_CTR_ACC_ACCESS "WC"
142 // =============================================================================
143 // Register    : XIP_STREAM_ADDR
144 // Description : FIFO stream address
145 //               The address of the next word to be streamed from flash to the
146 //               streaming FIFO.
147 //               Increments automatically after each flash access.
148 //               Write the initial access address here before starting a
149 //               streaming read.
150 #define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
151 #define XIP_STREAM_ADDR_BITS   _u(0xfffffffc)
152 #define XIP_STREAM_ADDR_RESET  _u(0x00000000)
153 #define XIP_STREAM_ADDR_MSB    _u(31)
154 #define XIP_STREAM_ADDR_LSB    _u(2)
155 #define XIP_STREAM_ADDR_ACCESS "RW"
156 // =============================================================================
157 // Register    : XIP_STREAM_CTR
158 // Description : FIFO stream control
159 //               Write a nonzero value to start a streaming read. This will then
160 //               progress in the background, using flash idle cycles to transfer
161 //               a linear data block from flash to the streaming FIFO.
162 //               Decrements automatically (1 at a time) as the stream
163 //               progresses, and halts on reaching 0.
164 //               Write 0 to halt an in-progress stream, and discard any in-
165 //               flight
166 //               read, so that a new stream can immediately be started (after
167 //               draining the FIFO and reinitialising STREAM_ADDR)
168 #define XIP_STREAM_CTR_OFFSET _u(0x00000018)
169 #define XIP_STREAM_CTR_BITS   _u(0x003fffff)
170 #define XIP_STREAM_CTR_RESET  _u(0x00000000)
171 #define XIP_STREAM_CTR_MSB    _u(21)
172 #define XIP_STREAM_CTR_LSB    _u(0)
173 #define XIP_STREAM_CTR_ACCESS "RW"
174 // =============================================================================
175 // Register    : XIP_STREAM_FIFO
176 // Description : FIFO stream data
177 //               Streamed data is buffered here, for retrieval by the system
178 //               DMA.
179 //               This FIFO can also be accessed via the XIP_AUX slave, to avoid
180 //               exposing
181 //               the DMA to bus stalls caused by other XIP traffic.
182 #define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
183 #define XIP_STREAM_FIFO_BITS   _u(0xffffffff)
184 #define XIP_STREAM_FIFO_RESET  _u(0x00000000)
185 #define XIP_STREAM_FIFO_MSB    _u(31)
186 #define XIP_STREAM_FIFO_LSB    _u(0)
187 #define XIP_STREAM_FIFO_ACCESS "RF"
188 // =============================================================================
189 #endif // _HARDWARE_REGS_XIP_H
190 
191