1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : XIP_AUX 10 // Version : 1 11 // Bus type : ahb 12 // Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_XIP_AUX_H 15 #define _HARDWARE_REGS_XIP_AUX_H 16 // ============================================================================= 17 // Register : XIP_AUX_STREAM 18 // Description : Read the XIP stream FIFO (fast bus access to 19 // XIP_CTRL_STREAM_FIFO) 20 #define XIP_AUX_STREAM_OFFSET _u(0x00000000) 21 #define XIP_AUX_STREAM_BITS _u(0xffffffff) 22 #define XIP_AUX_STREAM_RESET _u(0x00000000) 23 #define XIP_AUX_STREAM_MSB _u(31) 24 #define XIP_AUX_STREAM_LSB _u(0) 25 #define XIP_AUX_STREAM_ACCESS "RF" 26 // ============================================================================= 27 // Register : XIP_AUX_QMI_DIRECT_TX 28 // Description : Write to the QMI direct-mode TX FIFO (fast bus access to 29 // QMI_DIRECT_TX) 30 #define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004) 31 #define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff) 32 #define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000) 33 // ----------------------------------------------------------------------------- 34 // Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH 35 // Description : Inhibit the RX FIFO push that would correspond to this TX FIFO 36 // entry. 37 // 38 // Useful to avoid garbage appearing in the RX FIFO when pushing 39 // the command at the beginning of a SPI transfer. 40 #define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0) 41 #define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000) 42 #define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20) 43 #define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20) 44 #define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF" 45 // ----------------------------------------------------------------------------- 46 // Field : XIP_AUX_QMI_DIRECT_TX_OE 47 // Description : Output enable (active-high). For single width (SPI), this field 48 // is ignored, and SD0 is always set to output, with SD1 always 49 // set to input. 50 // 51 // For dual and quad width (DSPI/QSPI), this sets whether the 52 // relevant SDx pads are set to output whilst transferring this 53 // FIFO record. In this case the command/address should have OE 54 // set, and the data transfer should have OE set or clear 55 // depending on the direction of the transfer. 56 #define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0) 57 #define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000) 58 #define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19) 59 #define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19) 60 #define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF" 61 // ----------------------------------------------------------------------------- 62 // Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH 63 // Description : Data width. If 0, hardware will transmit the 8 LSBs of the 64 // DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs 65 // of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 66 // 16-bit transfers can be mixed freely. 67 #define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0) 68 #define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000) 69 #define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18) 70 #define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18) 71 #define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF" 72 // ----------------------------------------------------------------------------- 73 // Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH 74 // Description : Configure whether this FIFO record is transferred with 75 // single/dual/quad interface width (0/1/2). Different widths can 76 // be mixed freely. 77 // 0x0 -> Single width 78 // 0x1 -> Dual width 79 // 0x2 -> Quad width 80 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0) 81 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000) 82 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17) 83 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16) 84 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF" 85 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0) 86 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1) 87 #define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2) 88 // ----------------------------------------------------------------------------- 89 // Field : XIP_AUX_QMI_DIRECT_TX_DATA 90 // Description : Data pushed here will be clocked out falling edges of SCK (or 91 // before the very first rising edge of SCK, if this is the first 92 // pulse). For each byte clocked out, the interface will 93 // simultaneously sample one byte, on rising edges of SCK, and 94 // push this to the DIRECT_RX FIFO. 95 // 96 // For 16-bit data, the least-significant byte is transmitted 97 // first. 98 #define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000) 99 #define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff) 100 #define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15) 101 #define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0) 102 #define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF" 103 // ============================================================================= 104 // Register : XIP_AUX_QMI_DIRECT_RX 105 // Description : Read from the QMI direct-mode RX FIFO (fast bus access to 106 // QMI_DIRECT_RX) 107 // With each byte clocked out on the serial interface, one byte 108 // will simultaneously be clocked in, and will appear in this 109 // FIFO. The serial interface will stall when this FIFO is full, 110 // to avoid dropping data. 111 // 112 // When 16-bit data is pushed into the TX FIFO, the corresponding 113 // RX FIFO push will also contain 16 bits of data. The least- 114 // significant byte is the first one received. 115 #define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008) 116 #define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff) 117 #define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000) 118 #define XIP_AUX_QMI_DIRECT_RX_MSB _u(15) 119 #define XIP_AUX_QMI_DIRECT_RX_LSB _u(0) 120 #define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF" 121 // ============================================================================= 122 #endif // _HARDWARE_REGS_XIP_AUX_H 123 124
