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/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/
Dcore_cm33.h78 #define __FPU_USED 0U
81 #define __FPU_USED 0U
89 #define __DSP_USED 0U
92 #define __DSP_USED 0U
101 #define __FPU_USED 0U
104 #define __FPU_USED 0U
112 #define __DSP_USED 0U
115 #define __DSP_USED 0U
124 #define __FPU_USED 0U
127 #define __FPU_USED 0U
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Dcore_cm0plus.h67 #define __CORTEX_M (0U) /*!< Cortex-M Core */
72 #define __FPU_USED 0U
142 #define __MPU_PRESENT 0U
147 #define __VTOR_PRESENT 0U
157 #define __Vendor_SysTickConfig 0U
252 #define IPSR_ISR_Pos 0U /*!< IPSR…
291 #define xPSR_ISR_Pos 0U /*!< xPSR…
313 #define CONTROL_nPRIV_Pos 0U /*!< CONT…
386 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB …
414 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB …
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Dmpu_armv7.h63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
144 …EVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, …
162 #define ARM_MPU_CACHEP_NOCACHE 0U
221 MPU->RASR = 0U; in ARM_MPU_ClrRegion()
254 for (i = 0U; i < len; ++i) in ARM_MPU_OrderedMemcpy()
Dmpu_armv8.h35 #define ARM_MPU_ATTR_DEVICE ( 0U )
50 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
65 #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0…
68 #define ARM_MPU_SH_NON (0U)
228 mpu->RLAR = 0U; in ARM_MPU_ClrRegionEx()
292 for (i = 0U; i < len; ++i) in ARM_MPU_OrderedMemcpy()
320 rnrOffset = 0U; in ARM_MPU_LoadEx()
Dcmsis_iccarm.h339 #define __get_MSPLIM() (0U)
349 #define __get_PSPLIM() (0U)
409 #define __TZ_get_PSPLIM_NS() (0U)
560 if (data == 0U) { return 32U; } in __CLZ()
562 uint32_t count = 0U; in __CLZ()
565 while ((data & mask) == 0U) in __CLZ()
662 res = 0U; in __get_MSPLIM()
686 res = 0U; in __get_PSPLIM()
794 res = 0U; in __TZ_get_PSPLIM_NS()
860 return 0U; in __USAT()
Dcmsis_gcc.h250 if (op2 == 0U) in __ROR()
284 for (value >>= 1U; value != 0U; value >>= 1U) in __RBIT()
313 if (value == 0U) in __CLZ()
386 return (0U); in __USAT()
848 return (0U); in __get_FPSCR()
Dcmsis_armclang_ltm.h261 if (op2 == 0U) in __ROR()
304 if (value == 0U) in __CLZ()
555 return 0U; in __USAT()
1199 return 0U; in __get_PSPLIM()
1221 return 0U; in __TZ_get_PSPLIM_NS()
1287 return 0U; in __get_MSPLIM()
1309 return 0U; in __TZ_get_MSPLIM_NS()
1371 #define __get_FPSCR() ((uint32_t)0U)
Dcmsis_armcc.h382 return(0U); in __get_FPSCR()
540 for (value >>= 1U; value != 0U; value >>= 1U) in __RBIT()
790 return 0U; in __USAT()
Dcmsis_armclang.h319 return (0U); in __USAT()
675 return (0U); in __get_FPSCR()
Dcmsis_clang.h324 return (0U); in __USAT()
676 return (0U); in __get_FPSCR()
/hal_rpi_pico-latest/src/rp2_common/cmsis/stub/CMSIS/Core/Include/m-profile/
Darmv7m_mpu.h61 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
131 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
142 …EVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, …
160 #define ARM_MPU_CACHEP_NOCACHE 0U
219 MPU->RASR = 0U; in ARM_MPU_ClrRegion()
252 for (i = 0U; i < len; ++i) in ARM_MPU_OrderedMemcpy()
Darmv7m_cachel1.h148 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
163 } while (ways-- != 0U); in SCB_EnableDCache()
164 } while(sets-- != 0U); in SCB_EnableDCache()
192 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
234 } while (locals.ways-- != 0U); in SCB_DisableDCache()
235 } while(locals.sets-- != 0U); in SCB_DisableDCache()
254 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
269 } while (ways-- != 0U); in SCB_InvalidateDCache()
270 } while(sets-- != 0U); in SCB_InvalidateDCache()
289 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
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Darmv8m_mpu.h33 #define ARM_MPU_ATTR_DEVICE ( 0U )
48 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
93 #define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0…
102 #define ARM_MPU_SH_NON (0U)
115 #define ARM_MPU_AP_RW (0U)
124 #define ARM_MPU_AP_PO (0U)
134 #define ARM_MPU_EX (0U)
297 mpu->RLAR = 0U; in ARM_MPU_ClrRegionEx()
361 for (i = 0U; i < len; ++i) in ARM_MPU_OrderedMemcpy()
389 rnrOffset = 0U; in ARM_MPU_LoadEx()
Dcmsis_gcc_m.h548 return (0U); in __get_PSPLIM()
570 return (0U); in __TZ_get_PSPLIM_NS()
638 return (0U); in __get_MSPLIM()
661 return (0U); in __TZ_get_MSPLIM_NS()
Dcmsis_iccarm_m.h357 #define __get_MSPLIM() (0U)
368 #define __get_PSPLIM() (0U)
431 #define __TZ_get_PSPLIM_NS() (0U)
588 if (data == 0U) { return 32U; } in __CLZ()
590 uint32_t count = 0U; in __CLZ()
593 while ((data & mask) == 0U) in __CLZ()
697 res = 0U; in __get_MSPLIM()
723 res = 0U; in __get_PSPLIM()
833 res = 0U; in __TZ_get_PSPLIM_NS()
900 return 0U; in __USAT()
Dcmsis_armclang_m.h549 return (0U); in __get_PSPLIM()
571 return (0U); in __TZ_get_PSPLIM_NS()
639 return (0U); in __get_MSPLIM()
662 return (0U); in __TZ_get_MSPLIM_NS()
Dcmsis_clang_m.h555 return (0U); in __get_PSPLIM()
577 return (0U); in __TZ_get_PSPLIM_NS()
645 return (0U); in __get_MSPLIM()
668 return (0U); in __TZ_get_MSPLIM_NS()
Dcmsis_tiarmclang_m.h355 return (0U); in __USAT()
1161 return (0U); in __get_PSPLIM()
1183 return (0U); in __TZ_get_PSPLIM_NS()
1251 return (0U); in __get_MSPLIM()
1274 return (0U); in __TZ_get_MSPLIM_NS()
1339 return (0U); in __get_FPSCR()
/hal_rpi_pico-latest/src/rp2_common/pico_printf/
Dprintf.c90 #define FLAGS_ZEROPAD (1U << 0U)
171 unsigned int i = 0U; in _atoi()
262 size_t len = 0U; in _ntoa_long()
289 size_t len = 0U; in _ntoa_long_long()
325 size_t len = 0U; in _ftoa()
346 return 0U; in _ftoa()
380 } else if ((frac == 0U) || (frac & 1U)) { in _ftoa()
385 if (prec == 0U) { in _ftoa()
403 while ((len < PICO_PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) { in _ftoa()
468 uint64_t U; in _etoa() member
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/hal_rpi_pico-latest/tools/pioasm/gen/
Dparser.hpp238 template <typename T, typename... U>
240 emplace (U&&... u)
242 return *new (yyas_<T> ()) T (std::forward <U>(u)...);