1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : TICKS
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_TICKS_H
14 #define _HARDWARE_REGS_TICKS_H
15 // =============================================================================
16 // Register    : TICKS_PROC0_CTRL
17 // Description : Controls the tick generator
18 #define TICKS_PROC0_CTRL_OFFSET _u(0x00000000)
19 #define TICKS_PROC0_CTRL_BITS   _u(0x00000003)
20 #define TICKS_PROC0_CTRL_RESET  _u(0x00000000)
21 // -----------------------------------------------------------------------------
22 // Field       : TICKS_PROC0_CTRL_RUNNING
23 // Description : Is the tick generator running?
24 #define TICKS_PROC0_CTRL_RUNNING_RESET  "-"
25 #define TICKS_PROC0_CTRL_RUNNING_BITS   _u(0x00000002)
26 #define TICKS_PROC0_CTRL_RUNNING_MSB    _u(1)
27 #define TICKS_PROC0_CTRL_RUNNING_LSB    _u(1)
28 #define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO"
29 // -----------------------------------------------------------------------------
30 // Field       : TICKS_PROC0_CTRL_ENABLE
31 // Description : start / stop tick generation
32 #define TICKS_PROC0_CTRL_ENABLE_RESET  _u(0x0)
33 #define TICKS_PROC0_CTRL_ENABLE_BITS   _u(0x00000001)
34 #define TICKS_PROC0_CTRL_ENABLE_MSB    _u(0)
35 #define TICKS_PROC0_CTRL_ENABLE_LSB    _u(0)
36 #define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW"
37 // =============================================================================
38 // Register    : TICKS_PROC0_CYCLES
39 // Description : None
40 //               Total number of clk_tick cycles before the next tick.
41 #define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004)
42 #define TICKS_PROC0_CYCLES_BITS   _u(0x000001ff)
43 #define TICKS_PROC0_CYCLES_RESET  _u(0x00000000)
44 #define TICKS_PROC0_CYCLES_MSB    _u(8)
45 #define TICKS_PROC0_CYCLES_LSB    _u(0)
46 #define TICKS_PROC0_CYCLES_ACCESS "RW"
47 // =============================================================================
48 // Register    : TICKS_PROC0_COUNT
49 // Description : None
50 //               Count down timer: the remaining number clk_tick cycles before
51 //               the next tick is generated.
52 #define TICKS_PROC0_COUNT_OFFSET _u(0x00000008)
53 #define TICKS_PROC0_COUNT_BITS   _u(0x000001ff)
54 #define TICKS_PROC0_COUNT_RESET  "-"
55 #define TICKS_PROC0_COUNT_MSB    _u(8)
56 #define TICKS_PROC0_COUNT_LSB    _u(0)
57 #define TICKS_PROC0_COUNT_ACCESS "RO"
58 // =============================================================================
59 // Register    : TICKS_PROC1_CTRL
60 // Description : Controls the tick generator
61 #define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c)
62 #define TICKS_PROC1_CTRL_BITS   _u(0x00000003)
63 #define TICKS_PROC1_CTRL_RESET  _u(0x00000000)
64 // -----------------------------------------------------------------------------
65 // Field       : TICKS_PROC1_CTRL_RUNNING
66 // Description : Is the tick generator running?
67 #define TICKS_PROC1_CTRL_RUNNING_RESET  "-"
68 #define TICKS_PROC1_CTRL_RUNNING_BITS   _u(0x00000002)
69 #define TICKS_PROC1_CTRL_RUNNING_MSB    _u(1)
70 #define TICKS_PROC1_CTRL_RUNNING_LSB    _u(1)
71 #define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO"
72 // -----------------------------------------------------------------------------
73 // Field       : TICKS_PROC1_CTRL_ENABLE
74 // Description : start / stop tick generation
75 #define TICKS_PROC1_CTRL_ENABLE_RESET  _u(0x0)
76 #define TICKS_PROC1_CTRL_ENABLE_BITS   _u(0x00000001)
77 #define TICKS_PROC1_CTRL_ENABLE_MSB    _u(0)
78 #define TICKS_PROC1_CTRL_ENABLE_LSB    _u(0)
79 #define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW"
80 // =============================================================================
81 // Register    : TICKS_PROC1_CYCLES
82 // Description : None
83 //               Total number of clk_tick cycles before the next tick.
84 #define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010)
85 #define TICKS_PROC1_CYCLES_BITS   _u(0x000001ff)
86 #define TICKS_PROC1_CYCLES_RESET  _u(0x00000000)
87 #define TICKS_PROC1_CYCLES_MSB    _u(8)
88 #define TICKS_PROC1_CYCLES_LSB    _u(0)
89 #define TICKS_PROC1_CYCLES_ACCESS "RW"
90 // =============================================================================
91 // Register    : TICKS_PROC1_COUNT
92 // Description : None
93 //               Count down timer: the remaining number clk_tick cycles before
94 //               the next tick is generated.
95 #define TICKS_PROC1_COUNT_OFFSET _u(0x00000014)
96 #define TICKS_PROC1_COUNT_BITS   _u(0x000001ff)
97 #define TICKS_PROC1_COUNT_RESET  "-"
98 #define TICKS_PROC1_COUNT_MSB    _u(8)
99 #define TICKS_PROC1_COUNT_LSB    _u(0)
100 #define TICKS_PROC1_COUNT_ACCESS "RO"
101 // =============================================================================
102 // Register    : TICKS_TIMER0_CTRL
103 // Description : Controls the tick generator
104 #define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018)
105 #define TICKS_TIMER0_CTRL_BITS   _u(0x00000003)
106 #define TICKS_TIMER0_CTRL_RESET  _u(0x00000000)
107 // -----------------------------------------------------------------------------
108 // Field       : TICKS_TIMER0_CTRL_RUNNING
109 // Description : Is the tick generator running?
110 #define TICKS_TIMER0_CTRL_RUNNING_RESET  "-"
111 #define TICKS_TIMER0_CTRL_RUNNING_BITS   _u(0x00000002)
112 #define TICKS_TIMER0_CTRL_RUNNING_MSB    _u(1)
113 #define TICKS_TIMER0_CTRL_RUNNING_LSB    _u(1)
114 #define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO"
115 // -----------------------------------------------------------------------------
116 // Field       : TICKS_TIMER0_CTRL_ENABLE
117 // Description : start / stop tick generation
118 #define TICKS_TIMER0_CTRL_ENABLE_RESET  _u(0x0)
119 #define TICKS_TIMER0_CTRL_ENABLE_BITS   _u(0x00000001)
120 #define TICKS_TIMER0_CTRL_ENABLE_MSB    _u(0)
121 #define TICKS_TIMER0_CTRL_ENABLE_LSB    _u(0)
122 #define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW"
123 // =============================================================================
124 // Register    : TICKS_TIMER0_CYCLES
125 // Description : None
126 //               Total number of clk_tick cycles before the next tick.
127 #define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c)
128 #define TICKS_TIMER0_CYCLES_BITS   _u(0x000001ff)
129 #define TICKS_TIMER0_CYCLES_RESET  _u(0x00000000)
130 #define TICKS_TIMER0_CYCLES_MSB    _u(8)
131 #define TICKS_TIMER0_CYCLES_LSB    _u(0)
132 #define TICKS_TIMER0_CYCLES_ACCESS "RW"
133 // =============================================================================
134 // Register    : TICKS_TIMER0_COUNT
135 // Description : None
136 //               Count down timer: the remaining number clk_tick cycles before
137 //               the next tick is generated.
138 #define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020)
139 #define TICKS_TIMER0_COUNT_BITS   _u(0x000001ff)
140 #define TICKS_TIMER0_COUNT_RESET  "-"
141 #define TICKS_TIMER0_COUNT_MSB    _u(8)
142 #define TICKS_TIMER0_COUNT_LSB    _u(0)
143 #define TICKS_TIMER0_COUNT_ACCESS "RO"
144 // =============================================================================
145 // Register    : TICKS_TIMER1_CTRL
146 // Description : Controls the tick generator
147 #define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024)
148 #define TICKS_TIMER1_CTRL_BITS   _u(0x00000003)
149 #define TICKS_TIMER1_CTRL_RESET  _u(0x00000000)
150 // -----------------------------------------------------------------------------
151 // Field       : TICKS_TIMER1_CTRL_RUNNING
152 // Description : Is the tick generator running?
153 #define TICKS_TIMER1_CTRL_RUNNING_RESET  "-"
154 #define TICKS_TIMER1_CTRL_RUNNING_BITS   _u(0x00000002)
155 #define TICKS_TIMER1_CTRL_RUNNING_MSB    _u(1)
156 #define TICKS_TIMER1_CTRL_RUNNING_LSB    _u(1)
157 #define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO"
158 // -----------------------------------------------------------------------------
159 // Field       : TICKS_TIMER1_CTRL_ENABLE
160 // Description : start / stop tick generation
161 #define TICKS_TIMER1_CTRL_ENABLE_RESET  _u(0x0)
162 #define TICKS_TIMER1_CTRL_ENABLE_BITS   _u(0x00000001)
163 #define TICKS_TIMER1_CTRL_ENABLE_MSB    _u(0)
164 #define TICKS_TIMER1_CTRL_ENABLE_LSB    _u(0)
165 #define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW"
166 // =============================================================================
167 // Register    : TICKS_TIMER1_CYCLES
168 // Description : None
169 //               Total number of clk_tick cycles before the next tick.
170 #define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028)
171 #define TICKS_TIMER1_CYCLES_BITS   _u(0x000001ff)
172 #define TICKS_TIMER1_CYCLES_RESET  _u(0x00000000)
173 #define TICKS_TIMER1_CYCLES_MSB    _u(8)
174 #define TICKS_TIMER1_CYCLES_LSB    _u(0)
175 #define TICKS_TIMER1_CYCLES_ACCESS "RW"
176 // =============================================================================
177 // Register    : TICKS_TIMER1_COUNT
178 // Description : None
179 //               Count down timer: the remaining number clk_tick cycles before
180 //               the next tick is generated.
181 #define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c)
182 #define TICKS_TIMER1_COUNT_BITS   _u(0x000001ff)
183 #define TICKS_TIMER1_COUNT_RESET  "-"
184 #define TICKS_TIMER1_COUNT_MSB    _u(8)
185 #define TICKS_TIMER1_COUNT_LSB    _u(0)
186 #define TICKS_TIMER1_COUNT_ACCESS "RO"
187 // =============================================================================
188 // Register    : TICKS_WATCHDOG_CTRL
189 // Description : Controls the tick generator
190 #define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030)
191 #define TICKS_WATCHDOG_CTRL_BITS   _u(0x00000003)
192 #define TICKS_WATCHDOG_CTRL_RESET  _u(0x00000000)
193 // -----------------------------------------------------------------------------
194 // Field       : TICKS_WATCHDOG_CTRL_RUNNING
195 // Description : Is the tick generator running?
196 #define TICKS_WATCHDOG_CTRL_RUNNING_RESET  "-"
197 #define TICKS_WATCHDOG_CTRL_RUNNING_BITS   _u(0x00000002)
198 #define TICKS_WATCHDOG_CTRL_RUNNING_MSB    _u(1)
199 #define TICKS_WATCHDOG_CTRL_RUNNING_LSB    _u(1)
200 #define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO"
201 // -----------------------------------------------------------------------------
202 // Field       : TICKS_WATCHDOG_CTRL_ENABLE
203 // Description : start / stop tick generation
204 #define TICKS_WATCHDOG_CTRL_ENABLE_RESET  _u(0x0)
205 #define TICKS_WATCHDOG_CTRL_ENABLE_BITS   _u(0x00000001)
206 #define TICKS_WATCHDOG_CTRL_ENABLE_MSB    _u(0)
207 #define TICKS_WATCHDOG_CTRL_ENABLE_LSB    _u(0)
208 #define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW"
209 // =============================================================================
210 // Register    : TICKS_WATCHDOG_CYCLES
211 // Description : None
212 //               Total number of clk_tick cycles before the next tick.
213 #define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034)
214 #define TICKS_WATCHDOG_CYCLES_BITS   _u(0x000001ff)
215 #define TICKS_WATCHDOG_CYCLES_RESET  _u(0x00000000)
216 #define TICKS_WATCHDOG_CYCLES_MSB    _u(8)
217 #define TICKS_WATCHDOG_CYCLES_LSB    _u(0)
218 #define TICKS_WATCHDOG_CYCLES_ACCESS "RW"
219 // =============================================================================
220 // Register    : TICKS_WATCHDOG_COUNT
221 // Description : None
222 //               Count down timer: the remaining number clk_tick cycles before
223 //               the next tick is generated.
224 #define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038)
225 #define TICKS_WATCHDOG_COUNT_BITS   _u(0x000001ff)
226 #define TICKS_WATCHDOG_COUNT_RESET  "-"
227 #define TICKS_WATCHDOG_COUNT_MSB    _u(8)
228 #define TICKS_WATCHDOG_COUNT_LSB    _u(0)
229 #define TICKS_WATCHDOG_COUNT_ACCESS "RO"
230 // =============================================================================
231 // Register    : TICKS_RISCV_CTRL
232 // Description : Controls the tick generator
233 #define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c)
234 #define TICKS_RISCV_CTRL_BITS   _u(0x00000003)
235 #define TICKS_RISCV_CTRL_RESET  _u(0x00000000)
236 // -----------------------------------------------------------------------------
237 // Field       : TICKS_RISCV_CTRL_RUNNING
238 // Description : Is the tick generator running?
239 #define TICKS_RISCV_CTRL_RUNNING_RESET  "-"
240 #define TICKS_RISCV_CTRL_RUNNING_BITS   _u(0x00000002)
241 #define TICKS_RISCV_CTRL_RUNNING_MSB    _u(1)
242 #define TICKS_RISCV_CTRL_RUNNING_LSB    _u(1)
243 #define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO"
244 // -----------------------------------------------------------------------------
245 // Field       : TICKS_RISCV_CTRL_ENABLE
246 // Description : start / stop tick generation
247 #define TICKS_RISCV_CTRL_ENABLE_RESET  _u(0x0)
248 #define TICKS_RISCV_CTRL_ENABLE_BITS   _u(0x00000001)
249 #define TICKS_RISCV_CTRL_ENABLE_MSB    _u(0)
250 #define TICKS_RISCV_CTRL_ENABLE_LSB    _u(0)
251 #define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW"
252 // =============================================================================
253 // Register    : TICKS_RISCV_CYCLES
254 // Description : None
255 //               Total number of clk_tick cycles before the next tick.
256 #define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040)
257 #define TICKS_RISCV_CYCLES_BITS   _u(0x000001ff)
258 #define TICKS_RISCV_CYCLES_RESET  _u(0x00000000)
259 #define TICKS_RISCV_CYCLES_MSB    _u(8)
260 #define TICKS_RISCV_CYCLES_LSB    _u(0)
261 #define TICKS_RISCV_CYCLES_ACCESS "RW"
262 // =============================================================================
263 // Register    : TICKS_RISCV_COUNT
264 // Description : None
265 //               Count down timer: the remaining number clk_tick cycles before
266 //               the next tick is generated.
267 #define TICKS_RISCV_COUNT_OFFSET _u(0x00000044)
268 #define TICKS_RISCV_COUNT_BITS   _u(0x000001ff)
269 #define TICKS_RISCV_COUNT_RESET  "-"
270 #define TICKS_RISCV_COUNT_MSB    _u(8)
271 #define TICKS_RISCV_COUNT_LSB    _u(0)
272 #define TICKS_RISCV_COUNT_ACCESS "RO"
273 // =============================================================================
274 #endif // _HARDWARE_REGS_TICKS_H
275 
276