Home
last modified time | relevance | path

Searched refs:SSI_SPI_CTRLR0_OFFSET (Results 1 – 10 of 10) sorted by relevance

/hal_rpi_pico-latest/src/rp2040/boot_stage2/
Dboot2_w25x10cl.S132 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
181 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_is25lp080.S199 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
242 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_generic_03h.S84 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_at25sf128a.S223 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
260 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_w25q080.S225 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
262 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
/hal_rpi_pico-latest/src/rp2350/boot_stage2/
Dboot2_w25x10cl.S128 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
177 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_is25lp080.S195 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
238 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
Dboot2_at25sf128a.S219 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
256 ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dssi.h193 _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
/hal_rpi_pico-latest/src/rp2040/hardware_regs/include/hardware/regs/
Dssi.h709 #define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4) macro