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Searched refs:SSI_DR0_OFFSET (Results 1 – 10 of 10) sorted by relevance

/hal_rpi_pico-latest/src/rp2040/boot_stage2/asminclude/boot2_helpers/
Dread_flash_sreg.S19 str r0, [r3, #SSI_DR0_OFFSET]
21 str r0, [r3, #SSI_DR0_OFFSET]
25 ldr r0, [r3, #SSI_DR0_OFFSET]
26 ldr r0, [r3, #SSI_DR0_OFFSET]
/hal_rpi_pico-latest/src/rp2040/boot_stage2/
Dboot2_w25q080.S163 str r1, [r3, #SSI_DR0_OFFSET]
167 ldr r1, [r3, #SSI_DR0_OFFSET]
171 str r1, [r3, #SSI_DR0_OFFSET]
173 str r0, [r3, #SSI_DR0_OFFSET]
174 str r2, [r3, #SSI_DR0_OFFSET]
177 ldr r1, [r3, #SSI_DR0_OFFSET]
178 ldr r1, [r3, #SSI_DR0_OFFSET]
179 ldr r1, [r3, #SSI_DR0_OFFSET]
232 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
234 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_is25lp080.S130 str r1, [r3, #SSI_DR0_OFFSET]
134 ldr r1, [r3, #SSI_DR0_OFFSET]
138 str r1, [r3, #SSI_DR0_OFFSET]
140 str r2, [r3, #SSI_DR0_OFFSET]
143 ldr r1, [r3, #SSI_DR0_OFFSET]
144 ldr r1, [r3, #SSI_DR0_OFFSET]
206 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
208 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_at25sf128a.S163 str r1, [r3, #SSI_DR0_OFFSET]
167 ldr r1, [r3, #SSI_DR0_OFFSET]
171 str r1, [r3, #SSI_DR0_OFFSET]
172 str r2, [r3, #SSI_DR0_OFFSET]
175 ldr r1, [r3, #SSI_DR0_OFFSET]
176 ldr r1, [r3, #SSI_DR0_OFFSET]
177 ldr r1, [r3, #SSI_DR0_OFFSET]
230 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
232 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_w25x10cl.S139 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
141 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
/hal_rpi_pico-latest/src/rp2350/boot_stage2/
Dboot2_is25lp080.S126 str r1, [r3, #SSI_DR0_OFFSET]
130 ldr r1, [r3, #SSI_DR0_OFFSET]
134 str r1, [r3, #SSI_DR0_OFFSET]
136 str r2, [r3, #SSI_DR0_OFFSET]
139 ldr r1, [r3, #SSI_DR0_OFFSET]
140 ldr r1, [r3, #SSI_DR0_OFFSET]
202 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
204 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_at25sf128a.S159 str r1, [r3, #SSI_DR0_OFFSET]
163 ldr r1, [r3, #SSI_DR0_OFFSET]
167 str r1, [r3, #SSI_DR0_OFFSET]
168 str r2, [r3, #SSI_DR0_OFFSET]
171 ldr r1, [r3, #SSI_DR0_OFFSET]
172 ldr r1, [r3, #SSI_DR0_OFFSET]
173 ldr r1, [r3, #SSI_DR0_OFFSET]
226 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
228 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
Dboot2_w25x10cl.S135 str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
137 str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
/hal_rpi_pico-latest/src/rp2040/hardware_structs/include/hardware/structs/
Dssi.h181 _REG_(SSI_DR0_OFFSET) // SSI_DR0
/hal_rpi_pico-latest/src/rp2040/hardware_regs/include/hardware/regs/
Dssi.h681 #define SSI_DR0_OFFSET _u(0x00000060) macro