1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : SIO 10 // Version : 1 11 // Bus type : apb 12 // Description : Single-cycle IO block 13 // Provides core-local and inter-core hardware for the two 14 // processors, with single-cycle access. 15 // ============================================================================= 16 #ifndef _HARDWARE_REGS_SIO_H 17 #define _HARDWARE_REGS_SIO_H 18 // ============================================================================= 19 // Register : SIO_CPUID 20 // Description : Processor core identifier 21 // Value is 0 when read from processor core 0, and 1 when read 22 // from processor core 1. 23 #define SIO_CPUID_OFFSET _u(0x00000000) 24 #define SIO_CPUID_BITS _u(0xffffffff) 25 #define SIO_CPUID_RESET "-" 26 #define SIO_CPUID_MSB _u(31) 27 #define SIO_CPUID_LSB _u(0) 28 #define SIO_CPUID_ACCESS "RO" 29 // ============================================================================= 30 // Register : SIO_GPIO_IN 31 // Description : Input value for GPIO0...31. 32 // 33 // In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 34 // appear as zero. 35 #define SIO_GPIO_IN_OFFSET _u(0x00000004) 36 #define SIO_GPIO_IN_BITS _u(0xffffffff) 37 #define SIO_GPIO_IN_RESET _u(0x00000000) 38 #define SIO_GPIO_IN_MSB _u(31) 39 #define SIO_GPIO_IN_LSB _u(0) 40 #define SIO_GPIO_IN_ACCESS "RO" 41 // ============================================================================= 42 // Register : SIO_GPIO_HI_IN 43 // Description : Input value on GPIO32...47, QSPI IOs and USB pins 44 // 45 // In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 46 // appear as zero. 47 #define SIO_GPIO_HI_IN_OFFSET _u(0x00000008) 48 #define SIO_GPIO_HI_IN_BITS _u(0xff00ffff) 49 #define SIO_GPIO_HI_IN_RESET _u(0x00000000) 50 // ----------------------------------------------------------------------------- 51 // Field : SIO_GPIO_HI_IN_QSPI_SD 52 // Description : Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins 53 #define SIO_GPIO_HI_IN_QSPI_SD_RESET _u(0x0) 54 #define SIO_GPIO_HI_IN_QSPI_SD_BITS _u(0xf0000000) 55 #define SIO_GPIO_HI_IN_QSPI_SD_MSB _u(31) 56 #define SIO_GPIO_HI_IN_QSPI_SD_LSB _u(28) 57 #define SIO_GPIO_HI_IN_QSPI_SD_ACCESS "RO" 58 // ----------------------------------------------------------------------------- 59 // Field : SIO_GPIO_HI_IN_QSPI_CSN 60 // Description : Input value on QSPI CSn pin 61 #define SIO_GPIO_HI_IN_QSPI_CSN_RESET _u(0x0) 62 #define SIO_GPIO_HI_IN_QSPI_CSN_BITS _u(0x08000000) 63 #define SIO_GPIO_HI_IN_QSPI_CSN_MSB _u(27) 64 #define SIO_GPIO_HI_IN_QSPI_CSN_LSB _u(27) 65 #define SIO_GPIO_HI_IN_QSPI_CSN_ACCESS "RO" 66 // ----------------------------------------------------------------------------- 67 // Field : SIO_GPIO_HI_IN_QSPI_SCK 68 // Description : Input value on QSPI SCK pin 69 #define SIO_GPIO_HI_IN_QSPI_SCK_RESET _u(0x0) 70 #define SIO_GPIO_HI_IN_QSPI_SCK_BITS _u(0x04000000) 71 #define SIO_GPIO_HI_IN_QSPI_SCK_MSB _u(26) 72 #define SIO_GPIO_HI_IN_QSPI_SCK_LSB _u(26) 73 #define SIO_GPIO_HI_IN_QSPI_SCK_ACCESS "RO" 74 // ----------------------------------------------------------------------------- 75 // Field : SIO_GPIO_HI_IN_USB_DM 76 // Description : Input value on USB D- pin 77 #define SIO_GPIO_HI_IN_USB_DM_RESET _u(0x0) 78 #define SIO_GPIO_HI_IN_USB_DM_BITS _u(0x02000000) 79 #define SIO_GPIO_HI_IN_USB_DM_MSB _u(25) 80 #define SIO_GPIO_HI_IN_USB_DM_LSB _u(25) 81 #define SIO_GPIO_HI_IN_USB_DM_ACCESS "RO" 82 // ----------------------------------------------------------------------------- 83 // Field : SIO_GPIO_HI_IN_USB_DP 84 // Description : Input value on USB D+ pin 85 #define SIO_GPIO_HI_IN_USB_DP_RESET _u(0x0) 86 #define SIO_GPIO_HI_IN_USB_DP_BITS _u(0x01000000) 87 #define SIO_GPIO_HI_IN_USB_DP_MSB _u(24) 88 #define SIO_GPIO_HI_IN_USB_DP_LSB _u(24) 89 #define SIO_GPIO_HI_IN_USB_DP_ACCESS "RO" 90 // ----------------------------------------------------------------------------- 91 // Field : SIO_GPIO_HI_IN_GPIO 92 // Description : Input value on GPIO32...47 93 #define SIO_GPIO_HI_IN_GPIO_RESET _u(0x0000) 94 #define SIO_GPIO_HI_IN_GPIO_BITS _u(0x0000ffff) 95 #define SIO_GPIO_HI_IN_GPIO_MSB _u(15) 96 #define SIO_GPIO_HI_IN_GPIO_LSB _u(0) 97 #define SIO_GPIO_HI_IN_GPIO_ACCESS "RO" 98 // ============================================================================= 99 // Register : SIO_GPIO_OUT 100 // Description : GPIO0...31 output value 101 // Set output level (1/0 -> high/low) for GPIO0...31. Reading back 102 // gives the last value written, NOT the input value from the 103 // pins. 104 // 105 // If core 0 and core 1 both write to GPIO_OUT simultaneously (or 106 // to a SET/CLR/XOR alias), the result is as though the write from 107 // core 0 took place first, and the write from core 1 was then 108 // applied to that intermediate result. 109 // 110 // In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 111 // ignore writes, and their output status reads back as zero. This 112 // is also true for SET/CLR/XOR aliases of this register. 113 #define SIO_GPIO_OUT_OFFSET _u(0x00000010) 114 #define SIO_GPIO_OUT_BITS _u(0xffffffff) 115 #define SIO_GPIO_OUT_RESET _u(0x00000000) 116 #define SIO_GPIO_OUT_MSB _u(31) 117 #define SIO_GPIO_OUT_LSB _u(0) 118 #define SIO_GPIO_OUT_ACCESS "RW" 119 // ============================================================================= 120 // Register : SIO_GPIO_HI_OUT 121 // Description : Output value for GPIO32...47, QSPI IOs and USB pins. 122 // 123 // Write to set output level (1/0 -> high/low). Reading back gives 124 // the last value written, NOT the input value from the pins. If 125 // core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or 126 // to a SET/CLR/XOR alias), the result is as though the write from 127 // core 0 took place first, and the write from core 1 was then 128 // applied to that intermediate result. 129 // 130 // In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 131 // ignore writes, and their output status reads back as zero. This 132 // is also true for SET/CLR/XOR aliases of this register. 133 #define SIO_GPIO_HI_OUT_OFFSET _u(0x00000014) 134 #define SIO_GPIO_HI_OUT_BITS _u(0xff00ffff) 135 #define SIO_GPIO_HI_OUT_RESET _u(0x00000000) 136 // ----------------------------------------------------------------------------- 137 // Field : SIO_GPIO_HI_OUT_QSPI_SD 138 // Description : Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins 139 #define SIO_GPIO_HI_OUT_QSPI_SD_RESET _u(0x0) 140 #define SIO_GPIO_HI_OUT_QSPI_SD_BITS _u(0xf0000000) 141 #define SIO_GPIO_HI_OUT_QSPI_SD_MSB _u(31) 142 #define SIO_GPIO_HI_OUT_QSPI_SD_LSB _u(28) 143 #define SIO_GPIO_HI_OUT_QSPI_SD_ACCESS "RW" 144 // ----------------------------------------------------------------------------- 145 // Field : SIO_GPIO_HI_OUT_QSPI_CSN 146 // Description : Output value for QSPI CSn pin 147 #define SIO_GPIO_HI_OUT_QSPI_CSN_RESET _u(0x0) 148 #define SIO_GPIO_HI_OUT_QSPI_CSN_BITS _u(0x08000000) 149 #define SIO_GPIO_HI_OUT_QSPI_CSN_MSB _u(27) 150 #define SIO_GPIO_HI_OUT_QSPI_CSN_LSB _u(27) 151 #define SIO_GPIO_HI_OUT_QSPI_CSN_ACCESS "RW" 152 // ----------------------------------------------------------------------------- 153 // Field : SIO_GPIO_HI_OUT_QSPI_SCK 154 // Description : Output value for QSPI SCK pin 155 #define SIO_GPIO_HI_OUT_QSPI_SCK_RESET _u(0x0) 156 #define SIO_GPIO_HI_OUT_QSPI_SCK_BITS _u(0x04000000) 157 #define SIO_GPIO_HI_OUT_QSPI_SCK_MSB _u(26) 158 #define SIO_GPIO_HI_OUT_QSPI_SCK_LSB _u(26) 159 #define SIO_GPIO_HI_OUT_QSPI_SCK_ACCESS "RW" 160 // ----------------------------------------------------------------------------- 161 // Field : SIO_GPIO_HI_OUT_USB_DM 162 // Description : Output value for USB D- pin 163 #define SIO_GPIO_HI_OUT_USB_DM_RESET _u(0x0) 164 #define SIO_GPIO_HI_OUT_USB_DM_BITS _u(0x02000000) 165 #define SIO_GPIO_HI_OUT_USB_DM_MSB _u(25) 166 #define SIO_GPIO_HI_OUT_USB_DM_LSB _u(25) 167 #define SIO_GPIO_HI_OUT_USB_DM_ACCESS "RW" 168 // ----------------------------------------------------------------------------- 169 // Field : SIO_GPIO_HI_OUT_USB_DP 170 // Description : Output value for USB D+ pin 171 #define SIO_GPIO_HI_OUT_USB_DP_RESET _u(0x0) 172 #define SIO_GPIO_HI_OUT_USB_DP_BITS _u(0x01000000) 173 #define SIO_GPIO_HI_OUT_USB_DP_MSB _u(24) 174 #define SIO_GPIO_HI_OUT_USB_DP_LSB _u(24) 175 #define SIO_GPIO_HI_OUT_USB_DP_ACCESS "RW" 176 // ----------------------------------------------------------------------------- 177 // Field : SIO_GPIO_HI_OUT_GPIO 178 // Description : Output value for GPIO32...47 179 #define SIO_GPIO_HI_OUT_GPIO_RESET _u(0x0000) 180 #define SIO_GPIO_HI_OUT_GPIO_BITS _u(0x0000ffff) 181 #define SIO_GPIO_HI_OUT_GPIO_MSB _u(15) 182 #define SIO_GPIO_HI_OUT_GPIO_LSB _u(0) 183 #define SIO_GPIO_HI_OUT_GPIO_ACCESS "RW" 184 // ============================================================================= 185 // Register : SIO_GPIO_OUT_SET 186 // Description : GPIO0...31 output value set 187 // Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` 188 #define SIO_GPIO_OUT_SET_OFFSET _u(0x00000018) 189 #define SIO_GPIO_OUT_SET_BITS _u(0xffffffff) 190 #define SIO_GPIO_OUT_SET_RESET _u(0x00000000) 191 #define SIO_GPIO_OUT_SET_MSB _u(31) 192 #define SIO_GPIO_OUT_SET_LSB _u(0) 193 #define SIO_GPIO_OUT_SET_ACCESS "WO" 194 // ============================================================================= 195 // Register : SIO_GPIO_HI_OUT_SET 196 // Description : Output value set for GPIO32..47, QSPI IOs and USB pins. 197 // Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= 198 // wdata` 199 #define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x0000001c) 200 #define SIO_GPIO_HI_OUT_SET_BITS _u(0xff00ffff) 201 #define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000) 202 // ----------------------------------------------------------------------------- 203 // Field : SIO_GPIO_HI_OUT_SET_QSPI_SD 204 #define SIO_GPIO_HI_OUT_SET_QSPI_SD_RESET _u(0x0) 205 #define SIO_GPIO_HI_OUT_SET_QSPI_SD_BITS _u(0xf0000000) 206 #define SIO_GPIO_HI_OUT_SET_QSPI_SD_MSB _u(31) 207 #define SIO_GPIO_HI_OUT_SET_QSPI_SD_LSB _u(28) 208 #define SIO_GPIO_HI_OUT_SET_QSPI_SD_ACCESS "WO" 209 // ----------------------------------------------------------------------------- 210 // Field : SIO_GPIO_HI_OUT_SET_QSPI_CSN 211 #define SIO_GPIO_HI_OUT_SET_QSPI_CSN_RESET _u(0x0) 212 #define SIO_GPIO_HI_OUT_SET_QSPI_CSN_BITS _u(0x08000000) 213 #define SIO_GPIO_HI_OUT_SET_QSPI_CSN_MSB _u(27) 214 #define SIO_GPIO_HI_OUT_SET_QSPI_CSN_LSB _u(27) 215 #define SIO_GPIO_HI_OUT_SET_QSPI_CSN_ACCESS "WO" 216 // ----------------------------------------------------------------------------- 217 // Field : SIO_GPIO_HI_OUT_SET_QSPI_SCK 218 #define SIO_GPIO_HI_OUT_SET_QSPI_SCK_RESET _u(0x0) 219 #define SIO_GPIO_HI_OUT_SET_QSPI_SCK_BITS _u(0x04000000) 220 #define SIO_GPIO_HI_OUT_SET_QSPI_SCK_MSB _u(26) 221 #define SIO_GPIO_HI_OUT_SET_QSPI_SCK_LSB _u(26) 222 #define SIO_GPIO_HI_OUT_SET_QSPI_SCK_ACCESS "WO" 223 // ----------------------------------------------------------------------------- 224 // Field : SIO_GPIO_HI_OUT_SET_USB_DM 225 #define SIO_GPIO_HI_OUT_SET_USB_DM_RESET _u(0x0) 226 #define SIO_GPIO_HI_OUT_SET_USB_DM_BITS _u(0x02000000) 227 #define SIO_GPIO_HI_OUT_SET_USB_DM_MSB _u(25) 228 #define SIO_GPIO_HI_OUT_SET_USB_DM_LSB _u(25) 229 #define SIO_GPIO_HI_OUT_SET_USB_DM_ACCESS "WO" 230 // ----------------------------------------------------------------------------- 231 // Field : SIO_GPIO_HI_OUT_SET_USB_DP 232 #define SIO_GPIO_HI_OUT_SET_USB_DP_RESET _u(0x0) 233 #define SIO_GPIO_HI_OUT_SET_USB_DP_BITS _u(0x01000000) 234 #define SIO_GPIO_HI_OUT_SET_USB_DP_MSB _u(24) 235 #define SIO_GPIO_HI_OUT_SET_USB_DP_LSB _u(24) 236 #define SIO_GPIO_HI_OUT_SET_USB_DP_ACCESS "WO" 237 // ----------------------------------------------------------------------------- 238 // Field : SIO_GPIO_HI_OUT_SET_GPIO 239 #define SIO_GPIO_HI_OUT_SET_GPIO_RESET _u(0x0000) 240 #define SIO_GPIO_HI_OUT_SET_GPIO_BITS _u(0x0000ffff) 241 #define SIO_GPIO_HI_OUT_SET_GPIO_MSB _u(15) 242 #define SIO_GPIO_HI_OUT_SET_GPIO_LSB _u(0) 243 #define SIO_GPIO_HI_OUT_SET_GPIO_ACCESS "WO" 244 // ============================================================================= 245 // Register : SIO_GPIO_OUT_CLR 246 // Description : GPIO0...31 output value clear 247 // Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= 248 // ~wdata` 249 #define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000020) 250 #define SIO_GPIO_OUT_CLR_BITS _u(0xffffffff) 251 #define SIO_GPIO_OUT_CLR_RESET _u(0x00000000) 252 #define SIO_GPIO_OUT_CLR_MSB _u(31) 253 #define SIO_GPIO_OUT_CLR_LSB _u(0) 254 #define SIO_GPIO_OUT_CLR_ACCESS "WO" 255 // ============================================================================= 256 // Register : SIO_GPIO_HI_OUT_CLR 257 // Description : Output value clear for GPIO32..47, QSPI IOs and USB pins. 258 // Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT 259 // &= ~wdata` 260 #define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000024) 261 #define SIO_GPIO_HI_OUT_CLR_BITS _u(0xff00ffff) 262 #define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000) 263 // ----------------------------------------------------------------------------- 264 // Field : SIO_GPIO_HI_OUT_CLR_QSPI_SD 265 #define SIO_GPIO_HI_OUT_CLR_QSPI_SD_RESET _u(0x0) 266 #define SIO_GPIO_HI_OUT_CLR_QSPI_SD_BITS _u(0xf0000000) 267 #define SIO_GPIO_HI_OUT_CLR_QSPI_SD_MSB _u(31) 268 #define SIO_GPIO_HI_OUT_CLR_QSPI_SD_LSB _u(28) 269 #define SIO_GPIO_HI_OUT_CLR_QSPI_SD_ACCESS "WO" 270 // ----------------------------------------------------------------------------- 271 // Field : SIO_GPIO_HI_OUT_CLR_QSPI_CSN 272 #define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_RESET _u(0x0) 273 #define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_BITS _u(0x08000000) 274 #define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_MSB _u(27) 275 #define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_LSB _u(27) 276 #define SIO_GPIO_HI_OUT_CLR_QSPI_CSN_ACCESS "WO" 277 // ----------------------------------------------------------------------------- 278 // Field : SIO_GPIO_HI_OUT_CLR_QSPI_SCK 279 #define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_RESET _u(0x0) 280 #define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_BITS _u(0x04000000) 281 #define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_MSB _u(26) 282 #define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_LSB _u(26) 283 #define SIO_GPIO_HI_OUT_CLR_QSPI_SCK_ACCESS "WO" 284 // ----------------------------------------------------------------------------- 285 // Field : SIO_GPIO_HI_OUT_CLR_USB_DM 286 #define SIO_GPIO_HI_OUT_CLR_USB_DM_RESET _u(0x0) 287 #define SIO_GPIO_HI_OUT_CLR_USB_DM_BITS _u(0x02000000) 288 #define SIO_GPIO_HI_OUT_CLR_USB_DM_MSB _u(25) 289 #define SIO_GPIO_HI_OUT_CLR_USB_DM_LSB _u(25) 290 #define SIO_GPIO_HI_OUT_CLR_USB_DM_ACCESS "WO" 291 // ----------------------------------------------------------------------------- 292 // Field : SIO_GPIO_HI_OUT_CLR_USB_DP 293 #define SIO_GPIO_HI_OUT_CLR_USB_DP_RESET _u(0x0) 294 #define SIO_GPIO_HI_OUT_CLR_USB_DP_BITS _u(0x01000000) 295 #define SIO_GPIO_HI_OUT_CLR_USB_DP_MSB _u(24) 296 #define SIO_GPIO_HI_OUT_CLR_USB_DP_LSB _u(24) 297 #define SIO_GPIO_HI_OUT_CLR_USB_DP_ACCESS "WO" 298 // ----------------------------------------------------------------------------- 299 // Field : SIO_GPIO_HI_OUT_CLR_GPIO 300 #define SIO_GPIO_HI_OUT_CLR_GPIO_RESET _u(0x0000) 301 #define SIO_GPIO_HI_OUT_CLR_GPIO_BITS _u(0x0000ffff) 302 #define SIO_GPIO_HI_OUT_CLR_GPIO_MSB _u(15) 303 #define SIO_GPIO_HI_OUT_CLR_GPIO_LSB _u(0) 304 #define SIO_GPIO_HI_OUT_CLR_GPIO_ACCESS "WO" 305 // ============================================================================= 306 // Register : SIO_GPIO_OUT_XOR 307 // Description : GPIO0...31 output value XOR 308 // Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= 309 // wdata` 310 #define SIO_GPIO_OUT_XOR_OFFSET _u(0x00000028) 311 #define SIO_GPIO_OUT_XOR_BITS _u(0xffffffff) 312 #define SIO_GPIO_OUT_XOR_RESET _u(0x00000000) 313 #define SIO_GPIO_OUT_XOR_MSB _u(31) 314 #define SIO_GPIO_OUT_XOR_LSB _u(0) 315 #define SIO_GPIO_OUT_XOR_ACCESS "WO" 316 // ============================================================================= 317 // Register : SIO_GPIO_HI_OUT_XOR 318 // Description : Output value XOR for GPIO32..47, QSPI IOs and USB pins. 319 // Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT 320 // ^= wdata` 321 #define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000002c) 322 #define SIO_GPIO_HI_OUT_XOR_BITS _u(0xff00ffff) 323 #define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000) 324 // ----------------------------------------------------------------------------- 325 // Field : SIO_GPIO_HI_OUT_XOR_QSPI_SD 326 #define SIO_GPIO_HI_OUT_XOR_QSPI_SD_RESET _u(0x0) 327 #define SIO_GPIO_HI_OUT_XOR_QSPI_SD_BITS _u(0xf0000000) 328 #define SIO_GPIO_HI_OUT_XOR_QSPI_SD_MSB _u(31) 329 #define SIO_GPIO_HI_OUT_XOR_QSPI_SD_LSB _u(28) 330 #define SIO_GPIO_HI_OUT_XOR_QSPI_SD_ACCESS "WO" 331 // ----------------------------------------------------------------------------- 332 // Field : SIO_GPIO_HI_OUT_XOR_QSPI_CSN 333 #define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_RESET _u(0x0) 334 #define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_BITS _u(0x08000000) 335 #define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_MSB _u(27) 336 #define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_LSB _u(27) 337 #define SIO_GPIO_HI_OUT_XOR_QSPI_CSN_ACCESS "WO" 338 // ----------------------------------------------------------------------------- 339 // Field : SIO_GPIO_HI_OUT_XOR_QSPI_SCK 340 #define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_RESET _u(0x0) 341 #define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_BITS _u(0x04000000) 342 #define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_MSB _u(26) 343 #define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_LSB _u(26) 344 #define SIO_GPIO_HI_OUT_XOR_QSPI_SCK_ACCESS "WO" 345 // ----------------------------------------------------------------------------- 346 // Field : SIO_GPIO_HI_OUT_XOR_USB_DM 347 #define SIO_GPIO_HI_OUT_XOR_USB_DM_RESET _u(0x0) 348 #define SIO_GPIO_HI_OUT_XOR_USB_DM_BITS _u(0x02000000) 349 #define SIO_GPIO_HI_OUT_XOR_USB_DM_MSB _u(25) 350 #define SIO_GPIO_HI_OUT_XOR_USB_DM_LSB _u(25) 351 #define SIO_GPIO_HI_OUT_XOR_USB_DM_ACCESS "WO" 352 // ----------------------------------------------------------------------------- 353 // Field : SIO_GPIO_HI_OUT_XOR_USB_DP 354 #define SIO_GPIO_HI_OUT_XOR_USB_DP_RESET _u(0x0) 355 #define SIO_GPIO_HI_OUT_XOR_USB_DP_BITS _u(0x01000000) 356 #define SIO_GPIO_HI_OUT_XOR_USB_DP_MSB _u(24) 357 #define SIO_GPIO_HI_OUT_XOR_USB_DP_LSB _u(24) 358 #define SIO_GPIO_HI_OUT_XOR_USB_DP_ACCESS "WO" 359 // ----------------------------------------------------------------------------- 360 // Field : SIO_GPIO_HI_OUT_XOR_GPIO 361 #define SIO_GPIO_HI_OUT_XOR_GPIO_RESET _u(0x0000) 362 #define SIO_GPIO_HI_OUT_XOR_GPIO_BITS _u(0x0000ffff) 363 #define SIO_GPIO_HI_OUT_XOR_GPIO_MSB _u(15) 364 #define SIO_GPIO_HI_OUT_XOR_GPIO_LSB _u(0) 365 #define SIO_GPIO_HI_OUT_XOR_GPIO_ACCESS "WO" 366 // ============================================================================= 367 // Register : SIO_GPIO_OE 368 // Description : GPIO0...31 output enable 369 // Set output enable (1/0 -> output/input) for GPIO0...31. Reading 370 // back gives the last value written. 371 // 372 // If core 0 and core 1 both write to GPIO_OE simultaneously (or 373 // to a SET/CLR/XOR alias), the result is as though the write from 374 // core 0 took place first, and the write from core 1 was then 375 // applied to that intermediate result. 376 // 377 // In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 378 // ignore writes, and their output status reads back as zero. This 379 // is also true for SET/CLR/XOR aliases of this register. 380 #define SIO_GPIO_OE_OFFSET _u(0x00000030) 381 #define SIO_GPIO_OE_BITS _u(0xffffffff) 382 #define SIO_GPIO_OE_RESET _u(0x00000000) 383 #define SIO_GPIO_OE_MSB _u(31) 384 #define SIO_GPIO_OE_LSB _u(0) 385 #define SIO_GPIO_OE_ACCESS "RW" 386 // ============================================================================= 387 // Register : SIO_GPIO_HI_OE 388 // Description : Output enable value for GPIO32...47, QSPI IOs and USB pins. 389 // 390 // Write output enable (1/0 -> output/input). Reading back gives 391 // the last value written. If core 0 and core 1 both write to 392 // GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the 393 // result is as though the write from core 0 took place first, and 394 // the write from core 1 was then applied to that intermediate 395 // result. 396 // 397 // In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 398 // ignore writes, and their output status reads back as zero. This 399 // is also true for SET/CLR/XOR aliases of this register. 400 #define SIO_GPIO_HI_OE_OFFSET _u(0x00000034) 401 #define SIO_GPIO_HI_OE_BITS _u(0xff00ffff) 402 #define SIO_GPIO_HI_OE_RESET _u(0x00000000) 403 // ----------------------------------------------------------------------------- 404 // Field : SIO_GPIO_HI_OE_QSPI_SD 405 // Description : Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and 406 // SD3 pins 407 #define SIO_GPIO_HI_OE_QSPI_SD_RESET _u(0x0) 408 #define SIO_GPIO_HI_OE_QSPI_SD_BITS _u(0xf0000000) 409 #define SIO_GPIO_HI_OE_QSPI_SD_MSB _u(31) 410 #define SIO_GPIO_HI_OE_QSPI_SD_LSB _u(28) 411 #define SIO_GPIO_HI_OE_QSPI_SD_ACCESS "RW" 412 // ----------------------------------------------------------------------------- 413 // Field : SIO_GPIO_HI_OE_QSPI_CSN 414 // Description : Output enable value for QSPI CSn pin 415 #define SIO_GPIO_HI_OE_QSPI_CSN_RESET _u(0x0) 416 #define SIO_GPIO_HI_OE_QSPI_CSN_BITS _u(0x08000000) 417 #define SIO_GPIO_HI_OE_QSPI_CSN_MSB _u(27) 418 #define SIO_GPIO_HI_OE_QSPI_CSN_LSB _u(27) 419 #define SIO_GPIO_HI_OE_QSPI_CSN_ACCESS "RW" 420 // ----------------------------------------------------------------------------- 421 // Field : SIO_GPIO_HI_OE_QSPI_SCK 422 // Description : Output enable value for QSPI SCK pin 423 #define SIO_GPIO_HI_OE_QSPI_SCK_RESET _u(0x0) 424 #define SIO_GPIO_HI_OE_QSPI_SCK_BITS _u(0x04000000) 425 #define SIO_GPIO_HI_OE_QSPI_SCK_MSB _u(26) 426 #define SIO_GPIO_HI_OE_QSPI_SCK_LSB _u(26) 427 #define SIO_GPIO_HI_OE_QSPI_SCK_ACCESS "RW" 428 // ----------------------------------------------------------------------------- 429 // Field : SIO_GPIO_HI_OE_USB_DM 430 // Description : Output enable value for USB D- pin 431 #define SIO_GPIO_HI_OE_USB_DM_RESET _u(0x0) 432 #define SIO_GPIO_HI_OE_USB_DM_BITS _u(0x02000000) 433 #define SIO_GPIO_HI_OE_USB_DM_MSB _u(25) 434 #define SIO_GPIO_HI_OE_USB_DM_LSB _u(25) 435 #define SIO_GPIO_HI_OE_USB_DM_ACCESS "RW" 436 // ----------------------------------------------------------------------------- 437 // Field : SIO_GPIO_HI_OE_USB_DP 438 // Description : Output enable value for USB D+ pin 439 #define SIO_GPIO_HI_OE_USB_DP_RESET _u(0x0) 440 #define SIO_GPIO_HI_OE_USB_DP_BITS _u(0x01000000) 441 #define SIO_GPIO_HI_OE_USB_DP_MSB _u(24) 442 #define SIO_GPIO_HI_OE_USB_DP_LSB _u(24) 443 #define SIO_GPIO_HI_OE_USB_DP_ACCESS "RW" 444 // ----------------------------------------------------------------------------- 445 // Field : SIO_GPIO_HI_OE_GPIO 446 // Description : Output enable value for GPIO32...47 447 #define SIO_GPIO_HI_OE_GPIO_RESET _u(0x0000) 448 #define SIO_GPIO_HI_OE_GPIO_BITS _u(0x0000ffff) 449 #define SIO_GPIO_HI_OE_GPIO_MSB _u(15) 450 #define SIO_GPIO_HI_OE_GPIO_LSB _u(0) 451 #define SIO_GPIO_HI_OE_GPIO_ACCESS "RW" 452 // ============================================================================= 453 // Register : SIO_GPIO_OE_SET 454 // Description : GPIO0...31 output enable set 455 // Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` 456 #define SIO_GPIO_OE_SET_OFFSET _u(0x00000038) 457 #define SIO_GPIO_OE_SET_BITS _u(0xffffffff) 458 #define SIO_GPIO_OE_SET_RESET _u(0x00000000) 459 #define SIO_GPIO_OE_SET_MSB _u(31) 460 #define SIO_GPIO_OE_SET_LSB _u(0) 461 #define SIO_GPIO_OE_SET_ACCESS "WO" 462 // ============================================================================= 463 // Register : SIO_GPIO_HI_OE_SET 464 // Description : Output enable set for GPIO32...47, QSPI IOs and USB pins. 465 // Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= 466 // wdata` 467 #define SIO_GPIO_HI_OE_SET_OFFSET _u(0x0000003c) 468 #define SIO_GPIO_HI_OE_SET_BITS _u(0xff00ffff) 469 #define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000) 470 // ----------------------------------------------------------------------------- 471 // Field : SIO_GPIO_HI_OE_SET_QSPI_SD 472 #define SIO_GPIO_HI_OE_SET_QSPI_SD_RESET _u(0x0) 473 #define SIO_GPIO_HI_OE_SET_QSPI_SD_BITS _u(0xf0000000) 474 #define SIO_GPIO_HI_OE_SET_QSPI_SD_MSB _u(31) 475 #define SIO_GPIO_HI_OE_SET_QSPI_SD_LSB _u(28) 476 #define SIO_GPIO_HI_OE_SET_QSPI_SD_ACCESS "WO" 477 // ----------------------------------------------------------------------------- 478 // Field : SIO_GPIO_HI_OE_SET_QSPI_CSN 479 #define SIO_GPIO_HI_OE_SET_QSPI_CSN_RESET _u(0x0) 480 #define SIO_GPIO_HI_OE_SET_QSPI_CSN_BITS _u(0x08000000) 481 #define SIO_GPIO_HI_OE_SET_QSPI_CSN_MSB _u(27) 482 #define SIO_GPIO_HI_OE_SET_QSPI_CSN_LSB _u(27) 483 #define SIO_GPIO_HI_OE_SET_QSPI_CSN_ACCESS "WO" 484 // ----------------------------------------------------------------------------- 485 // Field : SIO_GPIO_HI_OE_SET_QSPI_SCK 486 #define SIO_GPIO_HI_OE_SET_QSPI_SCK_RESET _u(0x0) 487 #define SIO_GPIO_HI_OE_SET_QSPI_SCK_BITS _u(0x04000000) 488 #define SIO_GPIO_HI_OE_SET_QSPI_SCK_MSB _u(26) 489 #define SIO_GPIO_HI_OE_SET_QSPI_SCK_LSB _u(26) 490 #define SIO_GPIO_HI_OE_SET_QSPI_SCK_ACCESS "WO" 491 // ----------------------------------------------------------------------------- 492 // Field : SIO_GPIO_HI_OE_SET_USB_DM 493 #define SIO_GPIO_HI_OE_SET_USB_DM_RESET _u(0x0) 494 #define SIO_GPIO_HI_OE_SET_USB_DM_BITS _u(0x02000000) 495 #define SIO_GPIO_HI_OE_SET_USB_DM_MSB _u(25) 496 #define SIO_GPIO_HI_OE_SET_USB_DM_LSB _u(25) 497 #define SIO_GPIO_HI_OE_SET_USB_DM_ACCESS "WO" 498 // ----------------------------------------------------------------------------- 499 // Field : SIO_GPIO_HI_OE_SET_USB_DP 500 #define SIO_GPIO_HI_OE_SET_USB_DP_RESET _u(0x0) 501 #define SIO_GPIO_HI_OE_SET_USB_DP_BITS _u(0x01000000) 502 #define SIO_GPIO_HI_OE_SET_USB_DP_MSB _u(24) 503 #define SIO_GPIO_HI_OE_SET_USB_DP_LSB _u(24) 504 #define SIO_GPIO_HI_OE_SET_USB_DP_ACCESS "WO" 505 // ----------------------------------------------------------------------------- 506 // Field : SIO_GPIO_HI_OE_SET_GPIO 507 #define SIO_GPIO_HI_OE_SET_GPIO_RESET _u(0x0000) 508 #define SIO_GPIO_HI_OE_SET_GPIO_BITS _u(0x0000ffff) 509 #define SIO_GPIO_HI_OE_SET_GPIO_MSB _u(15) 510 #define SIO_GPIO_HI_OE_SET_GPIO_LSB _u(0) 511 #define SIO_GPIO_HI_OE_SET_GPIO_ACCESS "WO" 512 // ============================================================================= 513 // Register : SIO_GPIO_OE_CLR 514 // Description : GPIO0...31 output enable clear 515 // Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= 516 // ~wdata` 517 #define SIO_GPIO_OE_CLR_OFFSET _u(0x00000040) 518 #define SIO_GPIO_OE_CLR_BITS _u(0xffffffff) 519 #define SIO_GPIO_OE_CLR_RESET _u(0x00000000) 520 #define SIO_GPIO_OE_CLR_MSB _u(31) 521 #define SIO_GPIO_OE_CLR_LSB _u(0) 522 #define SIO_GPIO_OE_CLR_ACCESS "WO" 523 // ============================================================================= 524 // Register : SIO_GPIO_HI_OE_CLR 525 // Description : Output enable clear for GPIO32...47, QSPI IOs and USB pins. 526 // Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= 527 // ~wdata` 528 #define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000044) 529 #define SIO_GPIO_HI_OE_CLR_BITS _u(0xff00ffff) 530 #define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000) 531 // ----------------------------------------------------------------------------- 532 // Field : SIO_GPIO_HI_OE_CLR_QSPI_SD 533 #define SIO_GPIO_HI_OE_CLR_QSPI_SD_RESET _u(0x0) 534 #define SIO_GPIO_HI_OE_CLR_QSPI_SD_BITS _u(0xf0000000) 535 #define SIO_GPIO_HI_OE_CLR_QSPI_SD_MSB _u(31) 536 #define SIO_GPIO_HI_OE_CLR_QSPI_SD_LSB _u(28) 537 #define SIO_GPIO_HI_OE_CLR_QSPI_SD_ACCESS "WO" 538 // ----------------------------------------------------------------------------- 539 // Field : SIO_GPIO_HI_OE_CLR_QSPI_CSN 540 #define SIO_GPIO_HI_OE_CLR_QSPI_CSN_RESET _u(0x0) 541 #define SIO_GPIO_HI_OE_CLR_QSPI_CSN_BITS _u(0x08000000) 542 #define SIO_GPIO_HI_OE_CLR_QSPI_CSN_MSB _u(27) 543 #define SIO_GPIO_HI_OE_CLR_QSPI_CSN_LSB _u(27) 544 #define SIO_GPIO_HI_OE_CLR_QSPI_CSN_ACCESS "WO" 545 // ----------------------------------------------------------------------------- 546 // Field : SIO_GPIO_HI_OE_CLR_QSPI_SCK 547 #define SIO_GPIO_HI_OE_CLR_QSPI_SCK_RESET _u(0x0) 548 #define SIO_GPIO_HI_OE_CLR_QSPI_SCK_BITS _u(0x04000000) 549 #define SIO_GPIO_HI_OE_CLR_QSPI_SCK_MSB _u(26) 550 #define SIO_GPIO_HI_OE_CLR_QSPI_SCK_LSB _u(26) 551 #define SIO_GPIO_HI_OE_CLR_QSPI_SCK_ACCESS "WO" 552 // ----------------------------------------------------------------------------- 553 // Field : SIO_GPIO_HI_OE_CLR_USB_DM 554 #define SIO_GPIO_HI_OE_CLR_USB_DM_RESET _u(0x0) 555 #define SIO_GPIO_HI_OE_CLR_USB_DM_BITS _u(0x02000000) 556 #define SIO_GPIO_HI_OE_CLR_USB_DM_MSB _u(25) 557 #define SIO_GPIO_HI_OE_CLR_USB_DM_LSB _u(25) 558 #define SIO_GPIO_HI_OE_CLR_USB_DM_ACCESS "WO" 559 // ----------------------------------------------------------------------------- 560 // Field : SIO_GPIO_HI_OE_CLR_USB_DP 561 #define SIO_GPIO_HI_OE_CLR_USB_DP_RESET _u(0x0) 562 #define SIO_GPIO_HI_OE_CLR_USB_DP_BITS _u(0x01000000) 563 #define SIO_GPIO_HI_OE_CLR_USB_DP_MSB _u(24) 564 #define SIO_GPIO_HI_OE_CLR_USB_DP_LSB _u(24) 565 #define SIO_GPIO_HI_OE_CLR_USB_DP_ACCESS "WO" 566 // ----------------------------------------------------------------------------- 567 // Field : SIO_GPIO_HI_OE_CLR_GPIO 568 #define SIO_GPIO_HI_OE_CLR_GPIO_RESET _u(0x0000) 569 #define SIO_GPIO_HI_OE_CLR_GPIO_BITS _u(0x0000ffff) 570 #define SIO_GPIO_HI_OE_CLR_GPIO_MSB _u(15) 571 #define SIO_GPIO_HI_OE_CLR_GPIO_LSB _u(0) 572 #define SIO_GPIO_HI_OE_CLR_GPIO_ACCESS "WO" 573 // ============================================================================= 574 // Register : SIO_GPIO_OE_XOR 575 // Description : GPIO0...31 output enable XOR 576 // Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= 577 // wdata` 578 #define SIO_GPIO_OE_XOR_OFFSET _u(0x00000048) 579 #define SIO_GPIO_OE_XOR_BITS _u(0xffffffff) 580 #define SIO_GPIO_OE_XOR_RESET _u(0x00000000) 581 #define SIO_GPIO_OE_XOR_MSB _u(31) 582 #define SIO_GPIO_OE_XOR_LSB _u(0) 583 #define SIO_GPIO_OE_XOR_ACCESS "WO" 584 // ============================================================================= 585 // Register : SIO_GPIO_HI_OE_XOR 586 // Description : Output enable XOR for GPIO32...47, QSPI IOs and USB pins. 587 // Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE 588 // ^= wdata` 589 #define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c) 590 #define SIO_GPIO_HI_OE_XOR_BITS _u(0xff00ffff) 591 #define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000) 592 // ----------------------------------------------------------------------------- 593 // Field : SIO_GPIO_HI_OE_XOR_QSPI_SD 594 #define SIO_GPIO_HI_OE_XOR_QSPI_SD_RESET _u(0x0) 595 #define SIO_GPIO_HI_OE_XOR_QSPI_SD_BITS _u(0xf0000000) 596 #define SIO_GPIO_HI_OE_XOR_QSPI_SD_MSB _u(31) 597 #define SIO_GPIO_HI_OE_XOR_QSPI_SD_LSB _u(28) 598 #define SIO_GPIO_HI_OE_XOR_QSPI_SD_ACCESS "WO" 599 // ----------------------------------------------------------------------------- 600 // Field : SIO_GPIO_HI_OE_XOR_QSPI_CSN 601 #define SIO_GPIO_HI_OE_XOR_QSPI_CSN_RESET _u(0x0) 602 #define SIO_GPIO_HI_OE_XOR_QSPI_CSN_BITS _u(0x08000000) 603 #define SIO_GPIO_HI_OE_XOR_QSPI_CSN_MSB _u(27) 604 #define SIO_GPIO_HI_OE_XOR_QSPI_CSN_LSB _u(27) 605 #define SIO_GPIO_HI_OE_XOR_QSPI_CSN_ACCESS "WO" 606 // ----------------------------------------------------------------------------- 607 // Field : SIO_GPIO_HI_OE_XOR_QSPI_SCK 608 #define SIO_GPIO_HI_OE_XOR_QSPI_SCK_RESET _u(0x0) 609 #define SIO_GPIO_HI_OE_XOR_QSPI_SCK_BITS _u(0x04000000) 610 #define SIO_GPIO_HI_OE_XOR_QSPI_SCK_MSB _u(26) 611 #define SIO_GPIO_HI_OE_XOR_QSPI_SCK_LSB _u(26) 612 #define SIO_GPIO_HI_OE_XOR_QSPI_SCK_ACCESS "WO" 613 // ----------------------------------------------------------------------------- 614 // Field : SIO_GPIO_HI_OE_XOR_USB_DM 615 #define SIO_GPIO_HI_OE_XOR_USB_DM_RESET _u(0x0) 616 #define SIO_GPIO_HI_OE_XOR_USB_DM_BITS _u(0x02000000) 617 #define SIO_GPIO_HI_OE_XOR_USB_DM_MSB _u(25) 618 #define SIO_GPIO_HI_OE_XOR_USB_DM_LSB _u(25) 619 #define SIO_GPIO_HI_OE_XOR_USB_DM_ACCESS "WO" 620 // ----------------------------------------------------------------------------- 621 // Field : SIO_GPIO_HI_OE_XOR_USB_DP 622 #define SIO_GPIO_HI_OE_XOR_USB_DP_RESET _u(0x0) 623 #define SIO_GPIO_HI_OE_XOR_USB_DP_BITS _u(0x01000000) 624 #define SIO_GPIO_HI_OE_XOR_USB_DP_MSB _u(24) 625 #define SIO_GPIO_HI_OE_XOR_USB_DP_LSB _u(24) 626 #define SIO_GPIO_HI_OE_XOR_USB_DP_ACCESS "WO" 627 // ----------------------------------------------------------------------------- 628 // Field : SIO_GPIO_HI_OE_XOR_GPIO 629 #define SIO_GPIO_HI_OE_XOR_GPIO_RESET _u(0x0000) 630 #define SIO_GPIO_HI_OE_XOR_GPIO_BITS _u(0x0000ffff) 631 #define SIO_GPIO_HI_OE_XOR_GPIO_MSB _u(15) 632 #define SIO_GPIO_HI_OE_XOR_GPIO_LSB _u(0) 633 #define SIO_GPIO_HI_OE_XOR_GPIO_ACCESS "WO" 634 // ============================================================================= 635 // Register : SIO_FIFO_ST 636 // Description : Status register for inter-core FIFOs (mailboxes). 637 // There is one FIFO in the core 0 -> core 1 direction, and one 638 // core 1 -> core 0. Both are 32 bits wide and 8 words deep. 639 // Core 0 can see the read side of the 1->0 FIFO (RX), and the 640 // write side of 0->1 FIFO (TX). 641 // Core 1 can see the read side of the 0->1 FIFO (RX), and the 642 // write side of 1->0 FIFO (TX). 643 // The SIO IRQ for each core is the logical OR of the VLD, WOF and 644 // ROE fields of its FIFO_ST register. 645 #define SIO_FIFO_ST_OFFSET _u(0x00000050) 646 #define SIO_FIFO_ST_BITS _u(0x0000000f) 647 #define SIO_FIFO_ST_RESET _u(0x00000002) 648 // ----------------------------------------------------------------------------- 649 // Field : SIO_FIFO_ST_ROE 650 // Description : Sticky flag indicating the RX FIFO was read when empty. This 651 // read was ignored by the FIFO. 652 #define SIO_FIFO_ST_ROE_RESET _u(0x0) 653 #define SIO_FIFO_ST_ROE_BITS _u(0x00000008) 654 #define SIO_FIFO_ST_ROE_MSB _u(3) 655 #define SIO_FIFO_ST_ROE_LSB _u(3) 656 #define SIO_FIFO_ST_ROE_ACCESS "WC" 657 // ----------------------------------------------------------------------------- 658 // Field : SIO_FIFO_ST_WOF 659 // Description : Sticky flag indicating the TX FIFO was written when full. This 660 // write was ignored by the FIFO. 661 #define SIO_FIFO_ST_WOF_RESET _u(0x0) 662 #define SIO_FIFO_ST_WOF_BITS _u(0x00000004) 663 #define SIO_FIFO_ST_WOF_MSB _u(2) 664 #define SIO_FIFO_ST_WOF_LSB _u(2) 665 #define SIO_FIFO_ST_WOF_ACCESS "WC" 666 // ----------------------------------------------------------------------------- 667 // Field : SIO_FIFO_ST_RDY 668 // Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR 669 // is ready for more data) 670 #define SIO_FIFO_ST_RDY_RESET _u(0x1) 671 #define SIO_FIFO_ST_RDY_BITS _u(0x00000002) 672 #define SIO_FIFO_ST_RDY_MSB _u(1) 673 #define SIO_FIFO_ST_RDY_LSB _u(1) 674 #define SIO_FIFO_ST_RDY_ACCESS "RO" 675 // ----------------------------------------------------------------------------- 676 // Field : SIO_FIFO_ST_VLD 677 // Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD 678 // is valid) 679 #define SIO_FIFO_ST_VLD_RESET _u(0x0) 680 #define SIO_FIFO_ST_VLD_BITS _u(0x00000001) 681 #define SIO_FIFO_ST_VLD_MSB _u(0) 682 #define SIO_FIFO_ST_VLD_LSB _u(0) 683 #define SIO_FIFO_ST_VLD_ACCESS "RO" 684 // ============================================================================= 685 // Register : SIO_FIFO_WR 686 // Description : Write access to this core's TX FIFO 687 #define SIO_FIFO_WR_OFFSET _u(0x00000054) 688 #define SIO_FIFO_WR_BITS _u(0xffffffff) 689 #define SIO_FIFO_WR_RESET _u(0x00000000) 690 #define SIO_FIFO_WR_MSB _u(31) 691 #define SIO_FIFO_WR_LSB _u(0) 692 #define SIO_FIFO_WR_ACCESS "WF" 693 // ============================================================================= 694 // Register : SIO_FIFO_RD 695 // Description : Read access to this core's RX FIFO 696 #define SIO_FIFO_RD_OFFSET _u(0x00000058) 697 #define SIO_FIFO_RD_BITS _u(0xffffffff) 698 #define SIO_FIFO_RD_RESET "-" 699 #define SIO_FIFO_RD_MSB _u(31) 700 #define SIO_FIFO_RD_LSB _u(0) 701 #define SIO_FIFO_RD_ACCESS "RF" 702 // ============================================================================= 703 // Register : SIO_SPINLOCK_ST 704 // Description : Spinlock state 705 // A bitmap containing the state of all 32 spinlocks (1=locked). 706 // Mainly intended for debugging. 707 #define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c) 708 #define SIO_SPINLOCK_ST_BITS _u(0xffffffff) 709 #define SIO_SPINLOCK_ST_RESET _u(0x00000000) 710 #define SIO_SPINLOCK_ST_MSB _u(31) 711 #define SIO_SPINLOCK_ST_LSB _u(0) 712 #define SIO_SPINLOCK_ST_ACCESS "RO" 713 // ============================================================================= 714 // Register : SIO_INTERP0_ACCUM0 715 // Description : Read/write access to accumulator 0 716 #define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080) 717 #define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff) 718 #define SIO_INTERP0_ACCUM0_RESET _u(0x00000000) 719 #define SIO_INTERP0_ACCUM0_MSB _u(31) 720 #define SIO_INTERP0_ACCUM0_LSB _u(0) 721 #define SIO_INTERP0_ACCUM0_ACCESS "RW" 722 // ============================================================================= 723 // Register : SIO_INTERP0_ACCUM1 724 // Description : Read/write access to accumulator 1 725 #define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084) 726 #define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff) 727 #define SIO_INTERP0_ACCUM1_RESET _u(0x00000000) 728 #define SIO_INTERP0_ACCUM1_MSB _u(31) 729 #define SIO_INTERP0_ACCUM1_LSB _u(0) 730 #define SIO_INTERP0_ACCUM1_ACCESS "RW" 731 // ============================================================================= 732 // Register : SIO_INTERP0_BASE0 733 // Description : Read/write access to BASE0 register. 734 #define SIO_INTERP0_BASE0_OFFSET _u(0x00000088) 735 #define SIO_INTERP0_BASE0_BITS _u(0xffffffff) 736 #define SIO_INTERP0_BASE0_RESET _u(0x00000000) 737 #define SIO_INTERP0_BASE0_MSB _u(31) 738 #define SIO_INTERP0_BASE0_LSB _u(0) 739 #define SIO_INTERP0_BASE0_ACCESS "RW" 740 // ============================================================================= 741 // Register : SIO_INTERP0_BASE1 742 // Description : Read/write access to BASE1 register. 743 #define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c) 744 #define SIO_INTERP0_BASE1_BITS _u(0xffffffff) 745 #define SIO_INTERP0_BASE1_RESET _u(0x00000000) 746 #define SIO_INTERP0_BASE1_MSB _u(31) 747 #define SIO_INTERP0_BASE1_LSB _u(0) 748 #define SIO_INTERP0_BASE1_ACCESS "RW" 749 // ============================================================================= 750 // Register : SIO_INTERP0_BASE2 751 // Description : Read/write access to BASE2 register. 752 #define SIO_INTERP0_BASE2_OFFSET _u(0x00000090) 753 #define SIO_INTERP0_BASE2_BITS _u(0xffffffff) 754 #define SIO_INTERP0_BASE2_RESET _u(0x00000000) 755 #define SIO_INTERP0_BASE2_MSB _u(31) 756 #define SIO_INTERP0_BASE2_LSB _u(0) 757 #define SIO_INTERP0_BASE2_ACCESS "RW" 758 // ============================================================================= 759 // Register : SIO_INTERP0_POP_LANE0 760 // Description : Read LANE0 result, and simultaneously write lane results to 761 // both accumulators (POP). 762 #define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094) 763 #define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff) 764 #define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000) 765 #define SIO_INTERP0_POP_LANE0_MSB _u(31) 766 #define SIO_INTERP0_POP_LANE0_LSB _u(0) 767 #define SIO_INTERP0_POP_LANE0_ACCESS "RO" 768 // ============================================================================= 769 // Register : SIO_INTERP0_POP_LANE1 770 // Description : Read LANE1 result, and simultaneously write lane results to 771 // both accumulators (POP). 772 #define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098) 773 #define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff) 774 #define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000) 775 #define SIO_INTERP0_POP_LANE1_MSB _u(31) 776 #define SIO_INTERP0_POP_LANE1_LSB _u(0) 777 #define SIO_INTERP0_POP_LANE1_ACCESS "RO" 778 // ============================================================================= 779 // Register : SIO_INTERP0_POP_FULL 780 // Description : Read FULL result, and simultaneously write lane results to both 781 // accumulators (POP). 782 #define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c) 783 #define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff) 784 #define SIO_INTERP0_POP_FULL_RESET _u(0x00000000) 785 #define SIO_INTERP0_POP_FULL_MSB _u(31) 786 #define SIO_INTERP0_POP_FULL_LSB _u(0) 787 #define SIO_INTERP0_POP_FULL_ACCESS "RO" 788 // ============================================================================= 789 // Register : SIO_INTERP0_PEEK_LANE0 790 // Description : Read LANE0 result, without altering any internal state (PEEK). 791 #define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0) 792 #define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff) 793 #define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000) 794 #define SIO_INTERP0_PEEK_LANE0_MSB _u(31) 795 #define SIO_INTERP0_PEEK_LANE0_LSB _u(0) 796 #define SIO_INTERP0_PEEK_LANE0_ACCESS "RO" 797 // ============================================================================= 798 // Register : SIO_INTERP0_PEEK_LANE1 799 // Description : Read LANE1 result, without altering any internal state (PEEK). 800 #define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4) 801 #define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff) 802 #define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000) 803 #define SIO_INTERP0_PEEK_LANE1_MSB _u(31) 804 #define SIO_INTERP0_PEEK_LANE1_LSB _u(0) 805 #define SIO_INTERP0_PEEK_LANE1_ACCESS "RO" 806 // ============================================================================= 807 // Register : SIO_INTERP0_PEEK_FULL 808 // Description : Read FULL result, without altering any internal state (PEEK). 809 #define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8) 810 #define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff) 811 #define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000) 812 #define SIO_INTERP0_PEEK_FULL_MSB _u(31) 813 #define SIO_INTERP0_PEEK_FULL_LSB _u(0) 814 #define SIO_INTERP0_PEEK_FULL_ACCESS "RO" 815 // ============================================================================= 816 // Register : SIO_INTERP0_CTRL_LANE0 817 // Description : Control register for lane 0 818 #define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac) 819 #define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff) 820 #define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000) 821 // ----------------------------------------------------------------------------- 822 // Field : SIO_INTERP0_CTRL_LANE0_OVERF 823 // Description : Set if either OVERF0 or OVERF1 is set. 824 #define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0) 825 #define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000) 826 #define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25) 827 #define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25) 828 #define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO" 829 // ----------------------------------------------------------------------------- 830 // Field : SIO_INTERP0_CTRL_LANE0_OVERF1 831 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. 832 #define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0) 833 #define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000) 834 #define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24) 835 #define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24) 836 #define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO" 837 // ----------------------------------------------------------------------------- 838 // Field : SIO_INTERP0_CTRL_LANE0_OVERF0 839 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. 840 #define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0) 841 #define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000) 842 #define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23) 843 #define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23) 844 #define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO" 845 // ----------------------------------------------------------------------------- 846 // Field : SIO_INTERP0_CTRL_LANE0_BLEND 847 // Description : Only present on INTERP0 on each core. If BLEND mode is enabled: 848 // - LANE1 result is a linear interpolation between BASE0 and 849 // BASE1, controlled 850 // by the 8 LSBs of lane 1 shift and mask value (a fractional 851 // number between 852 // 0 and 255/256ths) 853 // - LANE0 result does not have BASE0 added (yields only the 8 854 // LSBs of lane 1 shift+mask value) 855 // - FULL result does not have lane 1 shift+mask value added 856 // (BASE2 + lane 0 shift+mask) 857 // LANE1 SIGNED flag controls whether the interpolation is signed 858 // or unsigned. 859 #define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0) 860 #define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000) 861 #define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21) 862 #define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21) 863 #define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW" 864 // ----------------------------------------------------------------------------- 865 // Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB 866 // Description : ORed into bits 29:28 of the lane result presented to the 867 // processor on the bus. 868 // No effect on the internal 32-bit datapath. Handy for using a 869 // lane to generate sequence 870 // of pointers into flash or SRAM. 871 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) 872 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) 873 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20) 874 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19) 875 #define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW" 876 // ----------------------------------------------------------------------------- 877 // Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW 878 // Description : If 1, mask + shift is bypassed for LANE0 result. This does not 879 // affect FULL result. 880 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0) 881 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) 882 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18) 883 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18) 884 #define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW" 885 // ----------------------------------------------------------------------------- 886 // Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT 887 // Description : If 1, feed the opposite lane's result into this lane's 888 // accumulator on POP. 889 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) 890 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) 891 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17) 892 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17) 893 #define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" 894 // ----------------------------------------------------------------------------- 895 // Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT 896 // Description : If 1, feed the opposite lane's accumulator into this lane's 897 // shift + mask hardware. 898 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 899 // before the shift+mask bypass) 900 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) 901 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) 902 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16) 903 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16) 904 #define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" 905 // ----------------------------------------------------------------------------- 906 // Field : SIO_INTERP0_CTRL_LANE0_SIGNED 907 // Description : If SIGNED is set, the shifted and masked accumulator value is 908 // sign-extended to 32 bits 909 // before adding to BASE0, and LANE0 PEEK/POP appear extended to 910 // 32 bits when read by processor. 911 #define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0) 912 #define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000) 913 #define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15) 914 #define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15) 915 #define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW" 916 // ----------------------------------------------------------------------------- 917 // Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB 918 // Description : The most-significant bit allowed to pass by the mask 919 // (inclusive) 920 // Setting MSB < LSB may cause chip to turn inside-out 921 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00) 922 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) 923 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14) 924 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10) 925 #define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW" 926 // ----------------------------------------------------------------------------- 927 // Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB 928 // Description : The least-significant bit allowed to pass by the mask 929 // (inclusive) 930 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00) 931 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) 932 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9) 933 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5) 934 #define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW" 935 // ----------------------------------------------------------------------------- 936 // Field : SIO_INTERP0_CTRL_LANE0_SHIFT 937 // Description : Right-rotate applied to accumulator before masking. By 938 // appropriately configuring the masks, left and right shifts can 939 // be synthesised. 940 #define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00) 941 #define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) 942 #define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4) 943 #define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0) 944 #define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW" 945 // ============================================================================= 946 // Register : SIO_INTERP0_CTRL_LANE1 947 // Description : Control register for lane 1 948 #define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0) 949 #define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff) 950 #define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000) 951 // ----------------------------------------------------------------------------- 952 // Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB 953 // Description : ORed into bits 29:28 of the lane result presented to the 954 // processor on the bus. 955 // No effect on the internal 32-bit datapath. Handy for using a 956 // lane to generate sequence 957 // of pointers into flash or SRAM. 958 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) 959 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) 960 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20) 961 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19) 962 #define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW" 963 // ----------------------------------------------------------------------------- 964 // Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW 965 // Description : If 1, mask + shift is bypassed for LANE1 result. This does not 966 // affect FULL result. 967 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0) 968 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) 969 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18) 970 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18) 971 #define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW" 972 // ----------------------------------------------------------------------------- 973 // Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT 974 // Description : If 1, feed the opposite lane's result into this lane's 975 // accumulator on POP. 976 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) 977 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) 978 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17) 979 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17) 980 #define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" 981 // ----------------------------------------------------------------------------- 982 // Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT 983 // Description : If 1, feed the opposite lane's accumulator into this lane's 984 // shift + mask hardware. 985 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 986 // before the shift+mask bypass) 987 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) 988 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) 989 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16) 990 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16) 991 #define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" 992 // ----------------------------------------------------------------------------- 993 // Field : SIO_INTERP0_CTRL_LANE1_SIGNED 994 // Description : If SIGNED is set, the shifted and masked accumulator value is 995 // sign-extended to 32 bits 996 // before adding to BASE1, and LANE1 PEEK/POP appear extended to 997 // 32 bits when read by processor. 998 #define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0) 999 #define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000) 1000 #define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15) 1001 #define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15) 1002 #define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW" 1003 // ----------------------------------------------------------------------------- 1004 // Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB 1005 // Description : The most-significant bit allowed to pass by the mask 1006 // (inclusive) 1007 // Setting MSB < LSB may cause chip to turn inside-out 1008 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00) 1009 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) 1010 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14) 1011 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10) 1012 #define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW" 1013 // ----------------------------------------------------------------------------- 1014 // Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB 1015 // Description : The least-significant bit allowed to pass by the mask 1016 // (inclusive) 1017 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00) 1018 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) 1019 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9) 1020 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5) 1021 #define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW" 1022 // ----------------------------------------------------------------------------- 1023 // Field : SIO_INTERP0_CTRL_LANE1_SHIFT 1024 // Description : Right-rotate applied to accumulator before masking. By 1025 // appropriately configuring the masks, left and right shifts can 1026 // be synthesised. 1027 #define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00) 1028 #define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) 1029 #define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4) 1030 #define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0) 1031 #define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW" 1032 // ============================================================================= 1033 // Register : SIO_INTERP0_ACCUM0_ADD 1034 // Description : Values written here are atomically added to ACCUM0 1035 // Reading yields lane 0's raw shift and mask value (BASE0 not 1036 // added). 1037 #define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4) 1038 #define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff) 1039 #define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000) 1040 #define SIO_INTERP0_ACCUM0_ADD_MSB _u(23) 1041 #define SIO_INTERP0_ACCUM0_ADD_LSB _u(0) 1042 #define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW" 1043 // ============================================================================= 1044 // Register : SIO_INTERP0_ACCUM1_ADD 1045 // Description : Values written here are atomically added to ACCUM1 1046 // Reading yields lane 1's raw shift and mask value (BASE1 not 1047 // added). 1048 #define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8) 1049 #define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff) 1050 #define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000) 1051 #define SIO_INTERP0_ACCUM1_ADD_MSB _u(23) 1052 #define SIO_INTERP0_ACCUM1_ADD_LSB _u(0) 1053 #define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW" 1054 // ============================================================================= 1055 // Register : SIO_INTERP0_BASE_1AND0 1056 // Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 1057 // simultaneously. 1058 // Each half is sign-extended to 32 bits if that lane's SIGNED 1059 // flag is set. 1060 #define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc) 1061 #define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff) 1062 #define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000) 1063 #define SIO_INTERP0_BASE_1AND0_MSB _u(31) 1064 #define SIO_INTERP0_BASE_1AND0_LSB _u(0) 1065 #define SIO_INTERP0_BASE_1AND0_ACCESS "WO" 1066 // ============================================================================= 1067 // Register : SIO_INTERP1_ACCUM0 1068 // Description : Read/write access to accumulator 0 1069 #define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0) 1070 #define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff) 1071 #define SIO_INTERP1_ACCUM0_RESET _u(0x00000000) 1072 #define SIO_INTERP1_ACCUM0_MSB _u(31) 1073 #define SIO_INTERP1_ACCUM0_LSB _u(0) 1074 #define SIO_INTERP1_ACCUM0_ACCESS "RW" 1075 // ============================================================================= 1076 // Register : SIO_INTERP1_ACCUM1 1077 // Description : Read/write access to accumulator 1 1078 #define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4) 1079 #define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff) 1080 #define SIO_INTERP1_ACCUM1_RESET _u(0x00000000) 1081 #define SIO_INTERP1_ACCUM1_MSB _u(31) 1082 #define SIO_INTERP1_ACCUM1_LSB _u(0) 1083 #define SIO_INTERP1_ACCUM1_ACCESS "RW" 1084 // ============================================================================= 1085 // Register : SIO_INTERP1_BASE0 1086 // Description : Read/write access to BASE0 register. 1087 #define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8) 1088 #define SIO_INTERP1_BASE0_BITS _u(0xffffffff) 1089 #define SIO_INTERP1_BASE0_RESET _u(0x00000000) 1090 #define SIO_INTERP1_BASE0_MSB _u(31) 1091 #define SIO_INTERP1_BASE0_LSB _u(0) 1092 #define SIO_INTERP1_BASE0_ACCESS "RW" 1093 // ============================================================================= 1094 // Register : SIO_INTERP1_BASE1 1095 // Description : Read/write access to BASE1 register. 1096 #define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc) 1097 #define SIO_INTERP1_BASE1_BITS _u(0xffffffff) 1098 #define SIO_INTERP1_BASE1_RESET _u(0x00000000) 1099 #define SIO_INTERP1_BASE1_MSB _u(31) 1100 #define SIO_INTERP1_BASE1_LSB _u(0) 1101 #define SIO_INTERP1_BASE1_ACCESS "RW" 1102 // ============================================================================= 1103 // Register : SIO_INTERP1_BASE2 1104 // Description : Read/write access to BASE2 register. 1105 #define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0) 1106 #define SIO_INTERP1_BASE2_BITS _u(0xffffffff) 1107 #define SIO_INTERP1_BASE2_RESET _u(0x00000000) 1108 #define SIO_INTERP1_BASE2_MSB _u(31) 1109 #define SIO_INTERP1_BASE2_LSB _u(0) 1110 #define SIO_INTERP1_BASE2_ACCESS "RW" 1111 // ============================================================================= 1112 // Register : SIO_INTERP1_POP_LANE0 1113 // Description : Read LANE0 result, and simultaneously write lane results to 1114 // both accumulators (POP). 1115 #define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4) 1116 #define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff) 1117 #define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000) 1118 #define SIO_INTERP1_POP_LANE0_MSB _u(31) 1119 #define SIO_INTERP1_POP_LANE0_LSB _u(0) 1120 #define SIO_INTERP1_POP_LANE0_ACCESS "RO" 1121 // ============================================================================= 1122 // Register : SIO_INTERP1_POP_LANE1 1123 // Description : Read LANE1 result, and simultaneously write lane results to 1124 // both accumulators (POP). 1125 #define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8) 1126 #define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff) 1127 #define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000) 1128 #define SIO_INTERP1_POP_LANE1_MSB _u(31) 1129 #define SIO_INTERP1_POP_LANE1_LSB _u(0) 1130 #define SIO_INTERP1_POP_LANE1_ACCESS "RO" 1131 // ============================================================================= 1132 // Register : SIO_INTERP1_POP_FULL 1133 // Description : Read FULL result, and simultaneously write lane results to both 1134 // accumulators (POP). 1135 #define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc) 1136 #define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff) 1137 #define SIO_INTERP1_POP_FULL_RESET _u(0x00000000) 1138 #define SIO_INTERP1_POP_FULL_MSB _u(31) 1139 #define SIO_INTERP1_POP_FULL_LSB _u(0) 1140 #define SIO_INTERP1_POP_FULL_ACCESS "RO" 1141 // ============================================================================= 1142 // Register : SIO_INTERP1_PEEK_LANE0 1143 // Description : Read LANE0 result, without altering any internal state (PEEK). 1144 #define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0) 1145 #define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff) 1146 #define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000) 1147 #define SIO_INTERP1_PEEK_LANE0_MSB _u(31) 1148 #define SIO_INTERP1_PEEK_LANE0_LSB _u(0) 1149 #define SIO_INTERP1_PEEK_LANE0_ACCESS "RO" 1150 // ============================================================================= 1151 // Register : SIO_INTERP1_PEEK_LANE1 1152 // Description : Read LANE1 result, without altering any internal state (PEEK). 1153 #define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4) 1154 #define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff) 1155 #define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000) 1156 #define SIO_INTERP1_PEEK_LANE1_MSB _u(31) 1157 #define SIO_INTERP1_PEEK_LANE1_LSB _u(0) 1158 #define SIO_INTERP1_PEEK_LANE1_ACCESS "RO" 1159 // ============================================================================= 1160 // Register : SIO_INTERP1_PEEK_FULL 1161 // Description : Read FULL result, without altering any internal state (PEEK). 1162 #define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8) 1163 #define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff) 1164 #define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000) 1165 #define SIO_INTERP1_PEEK_FULL_MSB _u(31) 1166 #define SIO_INTERP1_PEEK_FULL_LSB _u(0) 1167 #define SIO_INTERP1_PEEK_FULL_ACCESS "RO" 1168 // ============================================================================= 1169 // Register : SIO_INTERP1_CTRL_LANE0 1170 // Description : Control register for lane 0 1171 #define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec) 1172 #define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff) 1173 #define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000) 1174 // ----------------------------------------------------------------------------- 1175 // Field : SIO_INTERP1_CTRL_LANE0_OVERF 1176 // Description : Set if either OVERF0 or OVERF1 is set. 1177 #define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0) 1178 #define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000) 1179 #define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25) 1180 #define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25) 1181 #define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO" 1182 // ----------------------------------------------------------------------------- 1183 // Field : SIO_INTERP1_CTRL_LANE0_OVERF1 1184 // Description : Indicates if any masked-off MSBs in ACCUM1 are set. 1185 #define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0) 1186 #define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000) 1187 #define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24) 1188 #define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24) 1189 #define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO" 1190 // ----------------------------------------------------------------------------- 1191 // Field : SIO_INTERP1_CTRL_LANE0_OVERF0 1192 // Description : Indicates if any masked-off MSBs in ACCUM0 are set. 1193 #define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0) 1194 #define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000) 1195 #define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23) 1196 #define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23) 1197 #define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO" 1198 // ----------------------------------------------------------------------------- 1199 // Field : SIO_INTERP1_CTRL_LANE0_CLAMP 1200 // Description : Only present on INTERP1 on each core. If CLAMP mode is enabled: 1201 // - LANE0 result is shifted and masked ACCUM0, clamped by a lower 1202 // bound of 1203 // BASE0 and an upper bound of BASE1. 1204 // - Signedness of these comparisons is determined by 1205 // LANE0_CTRL_SIGNED 1206 #define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0) 1207 #define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000) 1208 #define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22) 1209 #define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22) 1210 #define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW" 1211 // ----------------------------------------------------------------------------- 1212 // Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB 1213 // Description : ORed into bits 29:28 of the lane result presented to the 1214 // processor on the bus. 1215 // No effect on the internal 32-bit datapath. Handy for using a 1216 // lane to generate sequence 1217 // of pointers into flash or SRAM. 1218 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0) 1219 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000) 1220 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20) 1221 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19) 1222 #define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW" 1223 // ----------------------------------------------------------------------------- 1224 // Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW 1225 // Description : If 1, mask + shift is bypassed for LANE0 result. This does not 1226 // affect FULL result. 1227 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0) 1228 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000) 1229 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18) 1230 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18) 1231 #define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW" 1232 // ----------------------------------------------------------------------------- 1233 // Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT 1234 // Description : If 1, feed the opposite lane's result into this lane's 1235 // accumulator on POP. 1236 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0) 1237 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000) 1238 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17) 1239 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17) 1240 #define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW" 1241 // ----------------------------------------------------------------------------- 1242 // Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT 1243 // Description : If 1, feed the opposite lane's accumulator into this lane's 1244 // shift + mask hardware. 1245 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 1246 // before the shift+mask bypass) 1247 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0) 1248 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000) 1249 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16) 1250 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16) 1251 #define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW" 1252 // ----------------------------------------------------------------------------- 1253 // Field : SIO_INTERP1_CTRL_LANE0_SIGNED 1254 // Description : If SIGNED is set, the shifted and masked accumulator value is 1255 // sign-extended to 32 bits 1256 // before adding to BASE0, and LANE0 PEEK/POP appear extended to 1257 // 32 bits when read by processor. 1258 #define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0) 1259 #define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000) 1260 #define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15) 1261 #define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15) 1262 #define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW" 1263 // ----------------------------------------------------------------------------- 1264 // Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB 1265 // Description : The most-significant bit allowed to pass by the mask 1266 // (inclusive) 1267 // Setting MSB < LSB may cause chip to turn inside-out 1268 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00) 1269 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00) 1270 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14) 1271 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10) 1272 #define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW" 1273 // ----------------------------------------------------------------------------- 1274 // Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB 1275 // Description : The least-significant bit allowed to pass by the mask 1276 // (inclusive) 1277 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00) 1278 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0) 1279 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9) 1280 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5) 1281 #define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW" 1282 // ----------------------------------------------------------------------------- 1283 // Field : SIO_INTERP1_CTRL_LANE0_SHIFT 1284 // Description : Right-rotate applied to accumulator before masking. By 1285 // appropriately configuring the masks, left and right shifts can 1286 // be synthesised. 1287 #define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00) 1288 #define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f) 1289 #define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4) 1290 #define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0) 1291 #define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW" 1292 // ============================================================================= 1293 // Register : SIO_INTERP1_CTRL_LANE1 1294 // Description : Control register for lane 1 1295 #define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0) 1296 #define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff) 1297 #define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000) 1298 // ----------------------------------------------------------------------------- 1299 // Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB 1300 // Description : ORed into bits 29:28 of the lane result presented to the 1301 // processor on the bus. 1302 // No effect on the internal 32-bit datapath. Handy for using a 1303 // lane to generate sequence 1304 // of pointers into flash or SRAM. 1305 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0) 1306 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000) 1307 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20) 1308 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19) 1309 #define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW" 1310 // ----------------------------------------------------------------------------- 1311 // Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW 1312 // Description : If 1, mask + shift is bypassed for LANE1 result. This does not 1313 // affect FULL result. 1314 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0) 1315 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000) 1316 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18) 1317 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18) 1318 #define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW" 1319 // ----------------------------------------------------------------------------- 1320 // Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT 1321 // Description : If 1, feed the opposite lane's result into this lane's 1322 // accumulator on POP. 1323 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0) 1324 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000) 1325 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17) 1326 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17) 1327 #define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW" 1328 // ----------------------------------------------------------------------------- 1329 // Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT 1330 // Description : If 1, feed the opposite lane's accumulator into this lane's 1331 // shift + mask hardware. 1332 // Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is 1333 // before the shift+mask bypass) 1334 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0) 1335 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000) 1336 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16) 1337 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16) 1338 #define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW" 1339 // ----------------------------------------------------------------------------- 1340 // Field : SIO_INTERP1_CTRL_LANE1_SIGNED 1341 // Description : If SIGNED is set, the shifted and masked accumulator value is 1342 // sign-extended to 32 bits 1343 // before adding to BASE1, and LANE1 PEEK/POP appear extended to 1344 // 32 bits when read by processor. 1345 #define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0) 1346 #define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000) 1347 #define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15) 1348 #define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15) 1349 #define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW" 1350 // ----------------------------------------------------------------------------- 1351 // Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB 1352 // Description : The most-significant bit allowed to pass by the mask 1353 // (inclusive) 1354 // Setting MSB < LSB may cause chip to turn inside-out 1355 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00) 1356 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00) 1357 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14) 1358 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10) 1359 #define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW" 1360 // ----------------------------------------------------------------------------- 1361 // Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB 1362 // Description : The least-significant bit allowed to pass by the mask 1363 // (inclusive) 1364 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00) 1365 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0) 1366 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9) 1367 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5) 1368 #define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW" 1369 // ----------------------------------------------------------------------------- 1370 // Field : SIO_INTERP1_CTRL_LANE1_SHIFT 1371 // Description : Right-rotate applied to accumulator before masking. By 1372 // appropriately configuring the masks, left and right shifts can 1373 // be synthesised. 1374 #define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00) 1375 #define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f) 1376 #define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4) 1377 #define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0) 1378 #define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW" 1379 // ============================================================================= 1380 // Register : SIO_INTERP1_ACCUM0_ADD 1381 // Description : Values written here are atomically added to ACCUM0 1382 // Reading yields lane 0's raw shift and mask value (BASE0 not 1383 // added). 1384 #define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4) 1385 #define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff) 1386 #define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000) 1387 #define SIO_INTERP1_ACCUM0_ADD_MSB _u(23) 1388 #define SIO_INTERP1_ACCUM0_ADD_LSB _u(0) 1389 #define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW" 1390 // ============================================================================= 1391 // Register : SIO_INTERP1_ACCUM1_ADD 1392 // Description : Values written here are atomically added to ACCUM1 1393 // Reading yields lane 1's raw shift and mask value (BASE1 not 1394 // added). 1395 #define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8) 1396 #define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff) 1397 #define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000) 1398 #define SIO_INTERP1_ACCUM1_ADD_MSB _u(23) 1399 #define SIO_INTERP1_ACCUM1_ADD_LSB _u(0) 1400 #define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW" 1401 // ============================================================================= 1402 // Register : SIO_INTERP1_BASE_1AND0 1403 // Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1 1404 // simultaneously. 1405 // Each half is sign-extended to 32 bits if that lane's SIGNED 1406 // flag is set. 1407 #define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc) 1408 #define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff) 1409 #define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000) 1410 #define SIO_INTERP1_BASE_1AND0_MSB _u(31) 1411 #define SIO_INTERP1_BASE_1AND0_LSB _u(0) 1412 #define SIO_INTERP1_BASE_1AND0_ACCESS "WO" 1413 // ============================================================================= 1414 // Register : SIO_SPINLOCK0 1415 // Description : Reading from a spinlock address will: 1416 // - Return 0 if lock is already locked 1417 // - Otherwise return nonzero, and simultaneously claim the lock 1418 // 1419 // Writing (any value) releases the lock. 1420 // If core 0 and core 1 attempt to claim the same lock 1421 // simultaneously, core 0 wins. 1422 // The value returned on success is 0x1 << lock number. 1423 #define SIO_SPINLOCK0_OFFSET _u(0x00000100) 1424 #define SIO_SPINLOCK0_BITS _u(0xffffffff) 1425 #define SIO_SPINLOCK0_RESET _u(0x00000000) 1426 #define SIO_SPINLOCK0_MSB _u(31) 1427 #define SIO_SPINLOCK0_LSB _u(0) 1428 #define SIO_SPINLOCK0_ACCESS "RW" 1429 // ============================================================================= 1430 // Register : SIO_SPINLOCK1 1431 // Description : Reading from a spinlock address will: 1432 // - Return 0 if lock is already locked 1433 // - Otherwise return nonzero, and simultaneously claim the lock 1434 // 1435 // Writing (any value) releases the lock. 1436 // If core 0 and core 1 attempt to claim the same lock 1437 // simultaneously, core 0 wins. 1438 // The value returned on success is 0x1 << lock number. 1439 #define SIO_SPINLOCK1_OFFSET _u(0x00000104) 1440 #define SIO_SPINLOCK1_BITS _u(0xffffffff) 1441 #define SIO_SPINLOCK1_RESET _u(0x00000000) 1442 #define SIO_SPINLOCK1_MSB _u(31) 1443 #define SIO_SPINLOCK1_LSB _u(0) 1444 #define SIO_SPINLOCK1_ACCESS "RW" 1445 // ============================================================================= 1446 // Register : SIO_SPINLOCK2 1447 // Description : Reading from a spinlock address will: 1448 // - Return 0 if lock is already locked 1449 // - Otherwise return nonzero, and simultaneously claim the lock 1450 // 1451 // Writing (any value) releases the lock. 1452 // If core 0 and core 1 attempt to claim the same lock 1453 // simultaneously, core 0 wins. 1454 // The value returned on success is 0x1 << lock number. 1455 #define SIO_SPINLOCK2_OFFSET _u(0x00000108) 1456 #define SIO_SPINLOCK2_BITS _u(0xffffffff) 1457 #define SIO_SPINLOCK2_RESET _u(0x00000000) 1458 #define SIO_SPINLOCK2_MSB _u(31) 1459 #define SIO_SPINLOCK2_LSB _u(0) 1460 #define SIO_SPINLOCK2_ACCESS "RW" 1461 // ============================================================================= 1462 // Register : SIO_SPINLOCK3 1463 // Description : Reading from a spinlock address will: 1464 // - Return 0 if lock is already locked 1465 // - Otherwise return nonzero, and simultaneously claim the lock 1466 // 1467 // Writing (any value) releases the lock. 1468 // If core 0 and core 1 attempt to claim the same lock 1469 // simultaneously, core 0 wins. 1470 // The value returned on success is 0x1 << lock number. 1471 #define SIO_SPINLOCK3_OFFSET _u(0x0000010c) 1472 #define SIO_SPINLOCK3_BITS _u(0xffffffff) 1473 #define SIO_SPINLOCK3_RESET _u(0x00000000) 1474 #define SIO_SPINLOCK3_MSB _u(31) 1475 #define SIO_SPINLOCK3_LSB _u(0) 1476 #define SIO_SPINLOCK3_ACCESS "RW" 1477 // ============================================================================= 1478 // Register : SIO_SPINLOCK4 1479 // Description : Reading from a spinlock address will: 1480 // - Return 0 if lock is already locked 1481 // - Otherwise return nonzero, and simultaneously claim the lock 1482 // 1483 // Writing (any value) releases the lock. 1484 // If core 0 and core 1 attempt to claim the same lock 1485 // simultaneously, core 0 wins. 1486 // The value returned on success is 0x1 << lock number. 1487 #define SIO_SPINLOCK4_OFFSET _u(0x00000110) 1488 #define SIO_SPINLOCK4_BITS _u(0xffffffff) 1489 #define SIO_SPINLOCK4_RESET _u(0x00000000) 1490 #define SIO_SPINLOCK4_MSB _u(31) 1491 #define SIO_SPINLOCK4_LSB _u(0) 1492 #define SIO_SPINLOCK4_ACCESS "RW" 1493 // ============================================================================= 1494 // Register : SIO_SPINLOCK5 1495 // Description : Reading from a spinlock address will: 1496 // - Return 0 if lock is already locked 1497 // - Otherwise return nonzero, and simultaneously claim the lock 1498 // 1499 // Writing (any value) releases the lock. 1500 // If core 0 and core 1 attempt to claim the same lock 1501 // simultaneously, core 0 wins. 1502 // The value returned on success is 0x1 << lock number. 1503 #define SIO_SPINLOCK5_OFFSET _u(0x00000114) 1504 #define SIO_SPINLOCK5_BITS _u(0xffffffff) 1505 #define SIO_SPINLOCK5_RESET _u(0x00000000) 1506 #define SIO_SPINLOCK5_MSB _u(31) 1507 #define SIO_SPINLOCK5_LSB _u(0) 1508 #define SIO_SPINLOCK5_ACCESS "RW" 1509 // ============================================================================= 1510 // Register : SIO_SPINLOCK6 1511 // Description : Reading from a spinlock address will: 1512 // - Return 0 if lock is already locked 1513 // - Otherwise return nonzero, and simultaneously claim the lock 1514 // 1515 // Writing (any value) releases the lock. 1516 // If core 0 and core 1 attempt to claim the same lock 1517 // simultaneously, core 0 wins. 1518 // The value returned on success is 0x1 << lock number. 1519 #define SIO_SPINLOCK6_OFFSET _u(0x00000118) 1520 #define SIO_SPINLOCK6_BITS _u(0xffffffff) 1521 #define SIO_SPINLOCK6_RESET _u(0x00000000) 1522 #define SIO_SPINLOCK6_MSB _u(31) 1523 #define SIO_SPINLOCK6_LSB _u(0) 1524 #define SIO_SPINLOCK6_ACCESS "RW" 1525 // ============================================================================= 1526 // Register : SIO_SPINLOCK7 1527 // Description : Reading from a spinlock address will: 1528 // - Return 0 if lock is already locked 1529 // - Otherwise return nonzero, and simultaneously claim the lock 1530 // 1531 // Writing (any value) releases the lock. 1532 // If core 0 and core 1 attempt to claim the same lock 1533 // simultaneously, core 0 wins. 1534 // The value returned on success is 0x1 << lock number. 1535 #define SIO_SPINLOCK7_OFFSET _u(0x0000011c) 1536 #define SIO_SPINLOCK7_BITS _u(0xffffffff) 1537 #define SIO_SPINLOCK7_RESET _u(0x00000000) 1538 #define SIO_SPINLOCK7_MSB _u(31) 1539 #define SIO_SPINLOCK7_LSB _u(0) 1540 #define SIO_SPINLOCK7_ACCESS "RW" 1541 // ============================================================================= 1542 // Register : SIO_SPINLOCK8 1543 // Description : Reading from a spinlock address will: 1544 // - Return 0 if lock is already locked 1545 // - Otherwise return nonzero, and simultaneously claim the lock 1546 // 1547 // Writing (any value) releases the lock. 1548 // If core 0 and core 1 attempt to claim the same lock 1549 // simultaneously, core 0 wins. 1550 // The value returned on success is 0x1 << lock number. 1551 #define SIO_SPINLOCK8_OFFSET _u(0x00000120) 1552 #define SIO_SPINLOCK8_BITS _u(0xffffffff) 1553 #define SIO_SPINLOCK8_RESET _u(0x00000000) 1554 #define SIO_SPINLOCK8_MSB _u(31) 1555 #define SIO_SPINLOCK8_LSB _u(0) 1556 #define SIO_SPINLOCK8_ACCESS "RW" 1557 // ============================================================================= 1558 // Register : SIO_SPINLOCK9 1559 // Description : Reading from a spinlock address will: 1560 // - Return 0 if lock is already locked 1561 // - Otherwise return nonzero, and simultaneously claim the lock 1562 // 1563 // Writing (any value) releases the lock. 1564 // If core 0 and core 1 attempt to claim the same lock 1565 // simultaneously, core 0 wins. 1566 // The value returned on success is 0x1 << lock number. 1567 #define SIO_SPINLOCK9_OFFSET _u(0x00000124) 1568 #define SIO_SPINLOCK9_BITS _u(0xffffffff) 1569 #define SIO_SPINLOCK9_RESET _u(0x00000000) 1570 #define SIO_SPINLOCK9_MSB _u(31) 1571 #define SIO_SPINLOCK9_LSB _u(0) 1572 #define SIO_SPINLOCK9_ACCESS "RW" 1573 // ============================================================================= 1574 // Register : SIO_SPINLOCK10 1575 // Description : Reading from a spinlock address will: 1576 // - Return 0 if lock is already locked 1577 // - Otherwise return nonzero, and simultaneously claim the lock 1578 // 1579 // Writing (any value) releases the lock. 1580 // If core 0 and core 1 attempt to claim the same lock 1581 // simultaneously, core 0 wins. 1582 // The value returned on success is 0x1 << lock number. 1583 #define SIO_SPINLOCK10_OFFSET _u(0x00000128) 1584 #define SIO_SPINLOCK10_BITS _u(0xffffffff) 1585 #define SIO_SPINLOCK10_RESET _u(0x00000000) 1586 #define SIO_SPINLOCK10_MSB _u(31) 1587 #define SIO_SPINLOCK10_LSB _u(0) 1588 #define SIO_SPINLOCK10_ACCESS "RW" 1589 // ============================================================================= 1590 // Register : SIO_SPINLOCK11 1591 // Description : Reading from a spinlock address will: 1592 // - Return 0 if lock is already locked 1593 // - Otherwise return nonzero, and simultaneously claim the lock 1594 // 1595 // Writing (any value) releases the lock. 1596 // If core 0 and core 1 attempt to claim the same lock 1597 // simultaneously, core 0 wins. 1598 // The value returned on success is 0x1 << lock number. 1599 #define SIO_SPINLOCK11_OFFSET _u(0x0000012c) 1600 #define SIO_SPINLOCK11_BITS _u(0xffffffff) 1601 #define SIO_SPINLOCK11_RESET _u(0x00000000) 1602 #define SIO_SPINLOCK11_MSB _u(31) 1603 #define SIO_SPINLOCK11_LSB _u(0) 1604 #define SIO_SPINLOCK11_ACCESS "RW" 1605 // ============================================================================= 1606 // Register : SIO_SPINLOCK12 1607 // Description : Reading from a spinlock address will: 1608 // - Return 0 if lock is already locked 1609 // - Otherwise return nonzero, and simultaneously claim the lock 1610 // 1611 // Writing (any value) releases the lock. 1612 // If core 0 and core 1 attempt to claim the same lock 1613 // simultaneously, core 0 wins. 1614 // The value returned on success is 0x1 << lock number. 1615 #define SIO_SPINLOCK12_OFFSET _u(0x00000130) 1616 #define SIO_SPINLOCK12_BITS _u(0xffffffff) 1617 #define SIO_SPINLOCK12_RESET _u(0x00000000) 1618 #define SIO_SPINLOCK12_MSB _u(31) 1619 #define SIO_SPINLOCK12_LSB _u(0) 1620 #define SIO_SPINLOCK12_ACCESS "RW" 1621 // ============================================================================= 1622 // Register : SIO_SPINLOCK13 1623 // Description : Reading from a spinlock address will: 1624 // - Return 0 if lock is already locked 1625 // - Otherwise return nonzero, and simultaneously claim the lock 1626 // 1627 // Writing (any value) releases the lock. 1628 // If core 0 and core 1 attempt to claim the same lock 1629 // simultaneously, core 0 wins. 1630 // The value returned on success is 0x1 << lock number. 1631 #define SIO_SPINLOCK13_OFFSET _u(0x00000134) 1632 #define SIO_SPINLOCK13_BITS _u(0xffffffff) 1633 #define SIO_SPINLOCK13_RESET _u(0x00000000) 1634 #define SIO_SPINLOCK13_MSB _u(31) 1635 #define SIO_SPINLOCK13_LSB _u(0) 1636 #define SIO_SPINLOCK13_ACCESS "RW" 1637 // ============================================================================= 1638 // Register : SIO_SPINLOCK14 1639 // Description : Reading from a spinlock address will: 1640 // - Return 0 if lock is already locked 1641 // - Otherwise return nonzero, and simultaneously claim the lock 1642 // 1643 // Writing (any value) releases the lock. 1644 // If core 0 and core 1 attempt to claim the same lock 1645 // simultaneously, core 0 wins. 1646 // The value returned on success is 0x1 << lock number. 1647 #define SIO_SPINLOCK14_OFFSET _u(0x00000138) 1648 #define SIO_SPINLOCK14_BITS _u(0xffffffff) 1649 #define SIO_SPINLOCK14_RESET _u(0x00000000) 1650 #define SIO_SPINLOCK14_MSB _u(31) 1651 #define SIO_SPINLOCK14_LSB _u(0) 1652 #define SIO_SPINLOCK14_ACCESS "RW" 1653 // ============================================================================= 1654 // Register : SIO_SPINLOCK15 1655 // Description : Reading from a spinlock address will: 1656 // - Return 0 if lock is already locked 1657 // - Otherwise return nonzero, and simultaneously claim the lock 1658 // 1659 // Writing (any value) releases the lock. 1660 // If core 0 and core 1 attempt to claim the same lock 1661 // simultaneously, core 0 wins. 1662 // The value returned on success is 0x1 << lock number. 1663 #define SIO_SPINLOCK15_OFFSET _u(0x0000013c) 1664 #define SIO_SPINLOCK15_BITS _u(0xffffffff) 1665 #define SIO_SPINLOCK15_RESET _u(0x00000000) 1666 #define SIO_SPINLOCK15_MSB _u(31) 1667 #define SIO_SPINLOCK15_LSB _u(0) 1668 #define SIO_SPINLOCK15_ACCESS "RW" 1669 // ============================================================================= 1670 // Register : SIO_SPINLOCK16 1671 // Description : Reading from a spinlock address will: 1672 // - Return 0 if lock is already locked 1673 // - Otherwise return nonzero, and simultaneously claim the lock 1674 // 1675 // Writing (any value) releases the lock. 1676 // If core 0 and core 1 attempt to claim the same lock 1677 // simultaneously, core 0 wins. 1678 // The value returned on success is 0x1 << lock number. 1679 #define SIO_SPINLOCK16_OFFSET _u(0x00000140) 1680 #define SIO_SPINLOCK16_BITS _u(0xffffffff) 1681 #define SIO_SPINLOCK16_RESET _u(0x00000000) 1682 #define SIO_SPINLOCK16_MSB _u(31) 1683 #define SIO_SPINLOCK16_LSB _u(0) 1684 #define SIO_SPINLOCK16_ACCESS "RW" 1685 // ============================================================================= 1686 // Register : SIO_SPINLOCK17 1687 // Description : Reading from a spinlock address will: 1688 // - Return 0 if lock is already locked 1689 // - Otherwise return nonzero, and simultaneously claim the lock 1690 // 1691 // Writing (any value) releases the lock. 1692 // If core 0 and core 1 attempt to claim the same lock 1693 // simultaneously, core 0 wins. 1694 // The value returned on success is 0x1 << lock number. 1695 #define SIO_SPINLOCK17_OFFSET _u(0x00000144) 1696 #define SIO_SPINLOCK17_BITS _u(0xffffffff) 1697 #define SIO_SPINLOCK17_RESET _u(0x00000000) 1698 #define SIO_SPINLOCK17_MSB _u(31) 1699 #define SIO_SPINLOCK17_LSB _u(0) 1700 #define SIO_SPINLOCK17_ACCESS "RW" 1701 // ============================================================================= 1702 // Register : SIO_SPINLOCK18 1703 // Description : Reading from a spinlock address will: 1704 // - Return 0 if lock is already locked 1705 // - Otherwise return nonzero, and simultaneously claim the lock 1706 // 1707 // Writing (any value) releases the lock. 1708 // If core 0 and core 1 attempt to claim the same lock 1709 // simultaneously, core 0 wins. 1710 // The value returned on success is 0x1 << lock number. 1711 #define SIO_SPINLOCK18_OFFSET _u(0x00000148) 1712 #define SIO_SPINLOCK18_BITS _u(0xffffffff) 1713 #define SIO_SPINLOCK18_RESET _u(0x00000000) 1714 #define SIO_SPINLOCK18_MSB _u(31) 1715 #define SIO_SPINLOCK18_LSB _u(0) 1716 #define SIO_SPINLOCK18_ACCESS "RW" 1717 // ============================================================================= 1718 // Register : SIO_SPINLOCK19 1719 // Description : Reading from a spinlock address will: 1720 // - Return 0 if lock is already locked 1721 // - Otherwise return nonzero, and simultaneously claim the lock 1722 // 1723 // Writing (any value) releases the lock. 1724 // If core 0 and core 1 attempt to claim the same lock 1725 // simultaneously, core 0 wins. 1726 // The value returned on success is 0x1 << lock number. 1727 #define SIO_SPINLOCK19_OFFSET _u(0x0000014c) 1728 #define SIO_SPINLOCK19_BITS _u(0xffffffff) 1729 #define SIO_SPINLOCK19_RESET _u(0x00000000) 1730 #define SIO_SPINLOCK19_MSB _u(31) 1731 #define SIO_SPINLOCK19_LSB _u(0) 1732 #define SIO_SPINLOCK19_ACCESS "RW" 1733 // ============================================================================= 1734 // Register : SIO_SPINLOCK20 1735 // Description : Reading from a spinlock address will: 1736 // - Return 0 if lock is already locked 1737 // - Otherwise return nonzero, and simultaneously claim the lock 1738 // 1739 // Writing (any value) releases the lock. 1740 // If core 0 and core 1 attempt to claim the same lock 1741 // simultaneously, core 0 wins. 1742 // The value returned on success is 0x1 << lock number. 1743 #define SIO_SPINLOCK20_OFFSET _u(0x00000150) 1744 #define SIO_SPINLOCK20_BITS _u(0xffffffff) 1745 #define SIO_SPINLOCK20_RESET _u(0x00000000) 1746 #define SIO_SPINLOCK20_MSB _u(31) 1747 #define SIO_SPINLOCK20_LSB _u(0) 1748 #define SIO_SPINLOCK20_ACCESS "RW" 1749 // ============================================================================= 1750 // Register : SIO_SPINLOCK21 1751 // Description : Reading from a spinlock address will: 1752 // - Return 0 if lock is already locked 1753 // - Otherwise return nonzero, and simultaneously claim the lock 1754 // 1755 // Writing (any value) releases the lock. 1756 // If core 0 and core 1 attempt to claim the same lock 1757 // simultaneously, core 0 wins. 1758 // The value returned on success is 0x1 << lock number. 1759 #define SIO_SPINLOCK21_OFFSET _u(0x00000154) 1760 #define SIO_SPINLOCK21_BITS _u(0xffffffff) 1761 #define SIO_SPINLOCK21_RESET _u(0x00000000) 1762 #define SIO_SPINLOCK21_MSB _u(31) 1763 #define SIO_SPINLOCK21_LSB _u(0) 1764 #define SIO_SPINLOCK21_ACCESS "RW" 1765 // ============================================================================= 1766 // Register : SIO_SPINLOCK22 1767 // Description : Reading from a spinlock address will: 1768 // - Return 0 if lock is already locked 1769 // - Otherwise return nonzero, and simultaneously claim the lock 1770 // 1771 // Writing (any value) releases the lock. 1772 // If core 0 and core 1 attempt to claim the same lock 1773 // simultaneously, core 0 wins. 1774 // The value returned on success is 0x1 << lock number. 1775 #define SIO_SPINLOCK22_OFFSET _u(0x00000158) 1776 #define SIO_SPINLOCK22_BITS _u(0xffffffff) 1777 #define SIO_SPINLOCK22_RESET _u(0x00000000) 1778 #define SIO_SPINLOCK22_MSB _u(31) 1779 #define SIO_SPINLOCK22_LSB _u(0) 1780 #define SIO_SPINLOCK22_ACCESS "RW" 1781 // ============================================================================= 1782 // Register : SIO_SPINLOCK23 1783 // Description : Reading from a spinlock address will: 1784 // - Return 0 if lock is already locked 1785 // - Otherwise return nonzero, and simultaneously claim the lock 1786 // 1787 // Writing (any value) releases the lock. 1788 // If core 0 and core 1 attempt to claim the same lock 1789 // simultaneously, core 0 wins. 1790 // The value returned on success is 0x1 << lock number. 1791 #define SIO_SPINLOCK23_OFFSET _u(0x0000015c) 1792 #define SIO_SPINLOCK23_BITS _u(0xffffffff) 1793 #define SIO_SPINLOCK23_RESET _u(0x00000000) 1794 #define SIO_SPINLOCK23_MSB _u(31) 1795 #define SIO_SPINLOCK23_LSB _u(0) 1796 #define SIO_SPINLOCK23_ACCESS "RW" 1797 // ============================================================================= 1798 // Register : SIO_SPINLOCK24 1799 // Description : Reading from a spinlock address will: 1800 // - Return 0 if lock is already locked 1801 // - Otherwise return nonzero, and simultaneously claim the lock 1802 // 1803 // Writing (any value) releases the lock. 1804 // If core 0 and core 1 attempt to claim the same lock 1805 // simultaneously, core 0 wins. 1806 // The value returned on success is 0x1 << lock number. 1807 #define SIO_SPINLOCK24_OFFSET _u(0x00000160) 1808 #define SIO_SPINLOCK24_BITS _u(0xffffffff) 1809 #define SIO_SPINLOCK24_RESET _u(0x00000000) 1810 #define SIO_SPINLOCK24_MSB _u(31) 1811 #define SIO_SPINLOCK24_LSB _u(0) 1812 #define SIO_SPINLOCK24_ACCESS "RW" 1813 // ============================================================================= 1814 // Register : SIO_SPINLOCK25 1815 // Description : Reading from a spinlock address will: 1816 // - Return 0 if lock is already locked 1817 // - Otherwise return nonzero, and simultaneously claim the lock 1818 // 1819 // Writing (any value) releases the lock. 1820 // If core 0 and core 1 attempt to claim the same lock 1821 // simultaneously, core 0 wins. 1822 // The value returned on success is 0x1 << lock number. 1823 #define SIO_SPINLOCK25_OFFSET _u(0x00000164) 1824 #define SIO_SPINLOCK25_BITS _u(0xffffffff) 1825 #define SIO_SPINLOCK25_RESET _u(0x00000000) 1826 #define SIO_SPINLOCK25_MSB _u(31) 1827 #define SIO_SPINLOCK25_LSB _u(0) 1828 #define SIO_SPINLOCK25_ACCESS "RW" 1829 // ============================================================================= 1830 // Register : SIO_SPINLOCK26 1831 // Description : Reading from a spinlock address will: 1832 // - Return 0 if lock is already locked 1833 // - Otherwise return nonzero, and simultaneously claim the lock 1834 // 1835 // Writing (any value) releases the lock. 1836 // If core 0 and core 1 attempt to claim the same lock 1837 // simultaneously, core 0 wins. 1838 // The value returned on success is 0x1 << lock number. 1839 #define SIO_SPINLOCK26_OFFSET _u(0x00000168) 1840 #define SIO_SPINLOCK26_BITS _u(0xffffffff) 1841 #define SIO_SPINLOCK26_RESET _u(0x00000000) 1842 #define SIO_SPINLOCK26_MSB _u(31) 1843 #define SIO_SPINLOCK26_LSB _u(0) 1844 #define SIO_SPINLOCK26_ACCESS "RW" 1845 // ============================================================================= 1846 // Register : SIO_SPINLOCK27 1847 // Description : Reading from a spinlock address will: 1848 // - Return 0 if lock is already locked 1849 // - Otherwise return nonzero, and simultaneously claim the lock 1850 // 1851 // Writing (any value) releases the lock. 1852 // If core 0 and core 1 attempt to claim the same lock 1853 // simultaneously, core 0 wins. 1854 // The value returned on success is 0x1 << lock number. 1855 #define SIO_SPINLOCK27_OFFSET _u(0x0000016c) 1856 #define SIO_SPINLOCK27_BITS _u(0xffffffff) 1857 #define SIO_SPINLOCK27_RESET _u(0x00000000) 1858 #define SIO_SPINLOCK27_MSB _u(31) 1859 #define SIO_SPINLOCK27_LSB _u(0) 1860 #define SIO_SPINLOCK27_ACCESS "RW" 1861 // ============================================================================= 1862 // Register : SIO_SPINLOCK28 1863 // Description : Reading from a spinlock address will: 1864 // - Return 0 if lock is already locked 1865 // - Otherwise return nonzero, and simultaneously claim the lock 1866 // 1867 // Writing (any value) releases the lock. 1868 // If core 0 and core 1 attempt to claim the same lock 1869 // simultaneously, core 0 wins. 1870 // The value returned on success is 0x1 << lock number. 1871 #define SIO_SPINLOCK28_OFFSET _u(0x00000170) 1872 #define SIO_SPINLOCK28_BITS _u(0xffffffff) 1873 #define SIO_SPINLOCK28_RESET _u(0x00000000) 1874 #define SIO_SPINLOCK28_MSB _u(31) 1875 #define SIO_SPINLOCK28_LSB _u(0) 1876 #define SIO_SPINLOCK28_ACCESS "RW" 1877 // ============================================================================= 1878 // Register : SIO_SPINLOCK29 1879 // Description : Reading from a spinlock address will: 1880 // - Return 0 if lock is already locked 1881 // - Otherwise return nonzero, and simultaneously claim the lock 1882 // 1883 // Writing (any value) releases the lock. 1884 // If core 0 and core 1 attempt to claim the same lock 1885 // simultaneously, core 0 wins. 1886 // The value returned on success is 0x1 << lock number. 1887 #define SIO_SPINLOCK29_OFFSET _u(0x00000174) 1888 #define SIO_SPINLOCK29_BITS _u(0xffffffff) 1889 #define SIO_SPINLOCK29_RESET _u(0x00000000) 1890 #define SIO_SPINLOCK29_MSB _u(31) 1891 #define SIO_SPINLOCK29_LSB _u(0) 1892 #define SIO_SPINLOCK29_ACCESS "RW" 1893 // ============================================================================= 1894 // Register : SIO_SPINLOCK30 1895 // Description : Reading from a spinlock address will: 1896 // - Return 0 if lock is already locked 1897 // - Otherwise return nonzero, and simultaneously claim the lock 1898 // 1899 // Writing (any value) releases the lock. 1900 // If core 0 and core 1 attempt to claim the same lock 1901 // simultaneously, core 0 wins. 1902 // The value returned on success is 0x1 << lock number. 1903 #define SIO_SPINLOCK30_OFFSET _u(0x00000178) 1904 #define SIO_SPINLOCK30_BITS _u(0xffffffff) 1905 #define SIO_SPINLOCK30_RESET _u(0x00000000) 1906 #define SIO_SPINLOCK30_MSB _u(31) 1907 #define SIO_SPINLOCK30_LSB _u(0) 1908 #define SIO_SPINLOCK30_ACCESS "RW" 1909 // ============================================================================= 1910 // Register : SIO_SPINLOCK31 1911 // Description : Reading from a spinlock address will: 1912 // - Return 0 if lock is already locked 1913 // - Otherwise return nonzero, and simultaneously claim the lock 1914 // 1915 // Writing (any value) releases the lock. 1916 // If core 0 and core 1 attempt to claim the same lock 1917 // simultaneously, core 0 wins. 1918 // The value returned on success is 0x1 << lock number. 1919 #define SIO_SPINLOCK31_OFFSET _u(0x0000017c) 1920 #define SIO_SPINLOCK31_BITS _u(0xffffffff) 1921 #define SIO_SPINLOCK31_RESET _u(0x00000000) 1922 #define SIO_SPINLOCK31_MSB _u(31) 1923 #define SIO_SPINLOCK31_LSB _u(0) 1924 #define SIO_SPINLOCK31_ACCESS "RW" 1925 // ============================================================================= 1926 // Register : SIO_DOORBELL_OUT_SET 1927 // Description : Trigger a doorbell interrupt on the opposite core. 1928 // 1929 // Write 1 to a bit to set the corresponding bit in DOORBELL_IN on 1930 // the opposite core. This raises the opposite core's doorbell 1931 // interrupt. 1932 // 1933 // Read to get the status of the doorbells currently asserted on 1934 // the opposite core. This is equivalent to that core reading its 1935 // own DOORBELL_IN status. 1936 #define SIO_DOORBELL_OUT_SET_OFFSET _u(0x00000180) 1937 #define SIO_DOORBELL_OUT_SET_BITS _u(0x000000ff) 1938 #define SIO_DOORBELL_OUT_SET_RESET _u(0x00000000) 1939 #define SIO_DOORBELL_OUT_SET_MSB _u(7) 1940 #define SIO_DOORBELL_OUT_SET_LSB _u(0) 1941 #define SIO_DOORBELL_OUT_SET_ACCESS "RW" 1942 // ============================================================================= 1943 // Register : SIO_DOORBELL_OUT_CLR 1944 // Description : Clear doorbells which have been posted to the opposite core. 1945 // This register is intended for debugging and initialisation 1946 // purposes. 1947 // 1948 // Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding 1949 // bit in DOORBELL_IN on the opposite core. Clearing all bits will 1950 // cause that core's doorbell interrupt to deassert. Since the 1951 // usual order of events is for software to send events using 1952 // DOORBELL_OUT_SET, and acknowledge incoming events by writing to 1953 // DOORBELL_IN_CLR, this register should be used with caution to 1954 // avoid race conditions. 1955 // 1956 // Reading returns the status of the doorbells currently asserted 1957 // on the other core, i.e. is equivalent to that core reading its 1958 // own DOORBELL_IN status. 1959 #define SIO_DOORBELL_OUT_CLR_OFFSET _u(0x00000184) 1960 #define SIO_DOORBELL_OUT_CLR_BITS _u(0x000000ff) 1961 #define SIO_DOORBELL_OUT_CLR_RESET _u(0x00000000) 1962 #define SIO_DOORBELL_OUT_CLR_MSB _u(7) 1963 #define SIO_DOORBELL_OUT_CLR_LSB _u(0) 1964 #define SIO_DOORBELL_OUT_CLR_ACCESS "WC" 1965 // ============================================================================= 1966 // Register : SIO_DOORBELL_IN_SET 1967 // Description : Write 1s to trigger doorbell interrupts on this core. Read to 1968 // get status of doorbells currently asserted on this core. 1969 #define SIO_DOORBELL_IN_SET_OFFSET _u(0x00000188) 1970 #define SIO_DOORBELL_IN_SET_BITS _u(0x000000ff) 1971 #define SIO_DOORBELL_IN_SET_RESET _u(0x00000000) 1972 #define SIO_DOORBELL_IN_SET_MSB _u(7) 1973 #define SIO_DOORBELL_IN_SET_LSB _u(0) 1974 #define SIO_DOORBELL_IN_SET_ACCESS "RW" 1975 // ============================================================================= 1976 // Register : SIO_DOORBELL_IN_CLR 1977 // Description : Check and acknowledge doorbells posted to this core. This 1978 // core's doorbell interrupt is asserted when any bit in this 1979 // register is 1. 1980 // 1981 // Write 1 to each bit to clear that bit. The doorbell interrupt 1982 // deasserts once all bits are cleared. Read to get status of 1983 // doorbells currently asserted on this core. 1984 #define SIO_DOORBELL_IN_CLR_OFFSET _u(0x0000018c) 1985 #define SIO_DOORBELL_IN_CLR_BITS _u(0x000000ff) 1986 #define SIO_DOORBELL_IN_CLR_RESET _u(0x00000000) 1987 #define SIO_DOORBELL_IN_CLR_MSB _u(7) 1988 #define SIO_DOORBELL_IN_CLR_LSB _u(0) 1989 #define SIO_DOORBELL_IN_CLR_ACCESS "WC" 1990 // ============================================================================= 1991 // Register : SIO_PERI_NONSEC 1992 // Description : Detach certain core-local peripherals from Secure SIO, and 1993 // attach them to Non-secure SIO, so that Non-secure software can 1994 // use them. Attempting to access one of these peripherals from 1995 // the Secure SIO when it is attached to the Non-secure SIO, or 1996 // vice versa, will generate a bus error. 1997 // 1998 // This register is per-core, and is only present on the Secure 1999 // SIO. 2000 // 2001 // Most SIO hardware is duplicated across the Secure and Non- 2002 // secure SIO, so is not listed in this register. 2003 #define SIO_PERI_NONSEC_OFFSET _u(0x00000190) 2004 #define SIO_PERI_NONSEC_BITS _u(0x00000023) 2005 #define SIO_PERI_NONSEC_RESET _u(0x00000000) 2006 // ----------------------------------------------------------------------------- 2007 // Field : SIO_PERI_NONSEC_TMDS 2008 // Description : IF 1, detach TMDS encoder (of this core) from the Secure SIO, 2009 // and attach to the Non-secure SIO. 2010 #define SIO_PERI_NONSEC_TMDS_RESET _u(0x0) 2011 #define SIO_PERI_NONSEC_TMDS_BITS _u(0x00000020) 2012 #define SIO_PERI_NONSEC_TMDS_MSB _u(5) 2013 #define SIO_PERI_NONSEC_TMDS_LSB _u(5) 2014 #define SIO_PERI_NONSEC_TMDS_ACCESS "RW" 2015 // ----------------------------------------------------------------------------- 2016 // Field : SIO_PERI_NONSEC_INTERP1 2017 // Description : If 1, detach interpolator 1 (of this core) from the Secure SIO, 2018 // and attach to the Non-secure SIO. 2019 #define SIO_PERI_NONSEC_INTERP1_RESET _u(0x0) 2020 #define SIO_PERI_NONSEC_INTERP1_BITS _u(0x00000002) 2021 #define SIO_PERI_NONSEC_INTERP1_MSB _u(1) 2022 #define SIO_PERI_NONSEC_INTERP1_LSB _u(1) 2023 #define SIO_PERI_NONSEC_INTERP1_ACCESS "RW" 2024 // ----------------------------------------------------------------------------- 2025 // Field : SIO_PERI_NONSEC_INTERP0 2026 // Description : If 1, detach interpolator 0 (of this core) from the Secure SIO, 2027 // and attach to the Non-secure SIO. 2028 #define SIO_PERI_NONSEC_INTERP0_RESET _u(0x0) 2029 #define SIO_PERI_NONSEC_INTERP0_BITS _u(0x00000001) 2030 #define SIO_PERI_NONSEC_INTERP0_MSB _u(0) 2031 #define SIO_PERI_NONSEC_INTERP0_LSB _u(0) 2032 #define SIO_PERI_NONSEC_INTERP0_ACCESS "RW" 2033 // ============================================================================= 2034 // Register : SIO_RISCV_SOFTIRQ 2035 // Description : Control the assertion of the standard software interrupt 2036 // (MIP.MSIP) on the RISC-V cores. 2037 // 2038 // Unlike the RISC-V timer, this interrupt is not routed to a 2039 // normal system-level interrupt line, so can not be used by the 2040 // Arm cores. 2041 // 2042 // It is safe for both cores to write to this register on the same 2043 // cycle. The set/clear effect is accumulated across both cores, 2044 // and then applied. If a flag is both set and cleared on the same 2045 // cycle, only the set takes effect. 2046 #define SIO_RISCV_SOFTIRQ_OFFSET _u(0x000001a0) 2047 #define SIO_RISCV_SOFTIRQ_BITS _u(0x00000303) 2048 #define SIO_RISCV_SOFTIRQ_RESET _u(0x00000000) 2049 // ----------------------------------------------------------------------------- 2050 // Field : SIO_RISCV_SOFTIRQ_CORE1_CLR 2051 // Description : Write 1 to atomically clear the core 1 software interrupt flag. 2052 // Read to get the status of this flag. 2053 #define SIO_RISCV_SOFTIRQ_CORE1_CLR_RESET _u(0x0) 2054 #define SIO_RISCV_SOFTIRQ_CORE1_CLR_BITS _u(0x00000200) 2055 #define SIO_RISCV_SOFTIRQ_CORE1_CLR_MSB _u(9) 2056 #define SIO_RISCV_SOFTIRQ_CORE1_CLR_LSB _u(9) 2057 #define SIO_RISCV_SOFTIRQ_CORE1_CLR_ACCESS "RW" 2058 // ----------------------------------------------------------------------------- 2059 // Field : SIO_RISCV_SOFTIRQ_CORE0_CLR 2060 // Description : Write 1 to atomically clear the core 0 software interrupt flag. 2061 // Read to get the status of this flag. 2062 #define SIO_RISCV_SOFTIRQ_CORE0_CLR_RESET _u(0x0) 2063 #define SIO_RISCV_SOFTIRQ_CORE0_CLR_BITS _u(0x00000100) 2064 #define SIO_RISCV_SOFTIRQ_CORE0_CLR_MSB _u(8) 2065 #define SIO_RISCV_SOFTIRQ_CORE0_CLR_LSB _u(8) 2066 #define SIO_RISCV_SOFTIRQ_CORE0_CLR_ACCESS "RW" 2067 // ----------------------------------------------------------------------------- 2068 // Field : SIO_RISCV_SOFTIRQ_CORE1_SET 2069 // Description : Write 1 to atomically set the core 1 software interrupt flag. 2070 // Read to get the status of this flag. 2071 #define SIO_RISCV_SOFTIRQ_CORE1_SET_RESET _u(0x0) 2072 #define SIO_RISCV_SOFTIRQ_CORE1_SET_BITS _u(0x00000002) 2073 #define SIO_RISCV_SOFTIRQ_CORE1_SET_MSB _u(1) 2074 #define SIO_RISCV_SOFTIRQ_CORE1_SET_LSB _u(1) 2075 #define SIO_RISCV_SOFTIRQ_CORE1_SET_ACCESS "RW" 2076 // ----------------------------------------------------------------------------- 2077 // Field : SIO_RISCV_SOFTIRQ_CORE0_SET 2078 // Description : Write 1 to atomically set the core 0 software interrupt flag. 2079 // Read to get the status of this flag. 2080 #define SIO_RISCV_SOFTIRQ_CORE0_SET_RESET _u(0x0) 2081 #define SIO_RISCV_SOFTIRQ_CORE0_SET_BITS _u(0x00000001) 2082 #define SIO_RISCV_SOFTIRQ_CORE0_SET_MSB _u(0) 2083 #define SIO_RISCV_SOFTIRQ_CORE0_SET_LSB _u(0) 2084 #define SIO_RISCV_SOFTIRQ_CORE0_SET_ACCESS "RW" 2085 // ============================================================================= 2086 // Register : SIO_MTIME_CTRL 2087 // Description : Control register for the RISC-V 64-bit Machine-mode timer. This 2088 // timer is only present in the Secure SIO, so is only accessible 2089 // to an Arm core in Secure mode or a RISC-V core in Machine mode. 2090 // 2091 // Note whilst this timer follows the RISC-V privileged 2092 // specification, it is equally usable by the Arm cores. The 2093 // interrupts are routed to normal system-level interrupt lines as 2094 // well as to the MIP.MTIP inputs on the RISC-V cores. 2095 #define SIO_MTIME_CTRL_OFFSET _u(0x000001a4) 2096 #define SIO_MTIME_CTRL_BITS _u(0x0000000f) 2097 #define SIO_MTIME_CTRL_RESET _u(0x0000000d) 2098 // ----------------------------------------------------------------------------- 2099 // Field : SIO_MTIME_CTRL_DBGPAUSE_CORE1 2100 // Description : If 1, the timer pauses when core 1 is in the debug halt state. 2101 #define SIO_MTIME_CTRL_DBGPAUSE_CORE1_RESET _u(0x1) 2102 #define SIO_MTIME_CTRL_DBGPAUSE_CORE1_BITS _u(0x00000008) 2103 #define SIO_MTIME_CTRL_DBGPAUSE_CORE1_MSB _u(3) 2104 #define SIO_MTIME_CTRL_DBGPAUSE_CORE1_LSB _u(3) 2105 #define SIO_MTIME_CTRL_DBGPAUSE_CORE1_ACCESS "RW" 2106 // ----------------------------------------------------------------------------- 2107 // Field : SIO_MTIME_CTRL_DBGPAUSE_CORE0 2108 // Description : If 1, the timer pauses when core 0 is in the debug halt state. 2109 #define SIO_MTIME_CTRL_DBGPAUSE_CORE0_RESET _u(0x1) 2110 #define SIO_MTIME_CTRL_DBGPAUSE_CORE0_BITS _u(0x00000004) 2111 #define SIO_MTIME_CTRL_DBGPAUSE_CORE0_MSB _u(2) 2112 #define SIO_MTIME_CTRL_DBGPAUSE_CORE0_LSB _u(2) 2113 #define SIO_MTIME_CTRL_DBGPAUSE_CORE0_ACCESS "RW" 2114 // ----------------------------------------------------------------------------- 2115 // Field : SIO_MTIME_CTRL_FULLSPEED 2116 // Description : If 1, increment the timer every cycle (i.e. run directly from 2117 // the system clock), rather than incrementing on the system-level 2118 // timer tick input. 2119 #define SIO_MTIME_CTRL_FULLSPEED_RESET _u(0x0) 2120 #define SIO_MTIME_CTRL_FULLSPEED_BITS _u(0x00000002) 2121 #define SIO_MTIME_CTRL_FULLSPEED_MSB _u(1) 2122 #define SIO_MTIME_CTRL_FULLSPEED_LSB _u(1) 2123 #define SIO_MTIME_CTRL_FULLSPEED_ACCESS "RW" 2124 // ----------------------------------------------------------------------------- 2125 // Field : SIO_MTIME_CTRL_EN 2126 // Description : Timer enable bit. When 0, the timer will not increment 2127 // automatically. 2128 #define SIO_MTIME_CTRL_EN_RESET _u(0x1) 2129 #define SIO_MTIME_CTRL_EN_BITS _u(0x00000001) 2130 #define SIO_MTIME_CTRL_EN_MSB _u(0) 2131 #define SIO_MTIME_CTRL_EN_LSB _u(0) 2132 #define SIO_MTIME_CTRL_EN_ACCESS "RW" 2133 // ============================================================================= 2134 // Register : SIO_MTIME 2135 // Description : Read/write access to the high half of RISC-V Machine-mode 2136 // timer. This register is shared between both cores. If both 2137 // cores write on the same cycle, core 1 takes precedence. 2138 #define SIO_MTIME_OFFSET _u(0x000001b0) 2139 #define SIO_MTIME_BITS _u(0xffffffff) 2140 #define SIO_MTIME_RESET _u(0x00000000) 2141 #define SIO_MTIME_MSB _u(31) 2142 #define SIO_MTIME_LSB _u(0) 2143 #define SIO_MTIME_ACCESS "RW" 2144 // ============================================================================= 2145 // Register : SIO_MTIMEH 2146 // Description : Read/write access to the high half of RISC-V Machine-mode 2147 // timer. This register is shared between both cores. If both 2148 // cores write on the same cycle, core 1 takes precedence. 2149 #define SIO_MTIMEH_OFFSET _u(0x000001b4) 2150 #define SIO_MTIMEH_BITS _u(0xffffffff) 2151 #define SIO_MTIMEH_RESET _u(0x00000000) 2152 #define SIO_MTIMEH_MSB _u(31) 2153 #define SIO_MTIMEH_LSB _u(0) 2154 #define SIO_MTIMEH_ACCESS "RW" 2155 // ============================================================================= 2156 // Register : SIO_MTIMECMP 2157 // Description : Low half of RISC-V Machine-mode timer comparator. This register 2158 // is core-local, i.e., each core gets a copy of this register, 2159 // with the comparison result routed to its own interrupt line. 2160 // 2161 // The timer interrupt is asserted whenever MTIME is greater than 2162 // or equal to MTIMECMP. This comparison is unsigned, and 2163 // performed on the full 64-bit values. 2164 #define SIO_MTIMECMP_OFFSET _u(0x000001b8) 2165 #define SIO_MTIMECMP_BITS _u(0xffffffff) 2166 #define SIO_MTIMECMP_RESET _u(0xffffffff) 2167 #define SIO_MTIMECMP_MSB _u(31) 2168 #define SIO_MTIMECMP_LSB _u(0) 2169 #define SIO_MTIMECMP_ACCESS "RW" 2170 // ============================================================================= 2171 // Register : SIO_MTIMECMPH 2172 // Description : High half of RISC-V Machine-mode timer comparator. This 2173 // register is core-local. 2174 // 2175 // The timer interrupt is asserted whenever MTIME is greater than 2176 // or equal to MTIMECMP. This comparison is unsigned, and 2177 // performed on the full 64-bit values. 2178 #define SIO_MTIMECMPH_OFFSET _u(0x000001bc) 2179 #define SIO_MTIMECMPH_BITS _u(0xffffffff) 2180 #define SIO_MTIMECMPH_RESET _u(0xffffffff) 2181 #define SIO_MTIMECMPH_MSB _u(31) 2182 #define SIO_MTIMECMPH_LSB _u(0) 2183 #define SIO_MTIMECMPH_ACCESS "RW" 2184 // ============================================================================= 2185 // Register : SIO_TMDS_CTRL 2186 // Description : Control register for TMDS encoder. 2187 #define SIO_TMDS_CTRL_OFFSET _u(0x000001c0) 2188 #define SIO_TMDS_CTRL_BITS _u(0x1f9fffff) 2189 #define SIO_TMDS_CTRL_RESET _u(0x00000000) 2190 // ----------------------------------------------------------------------------- 2191 // Field : SIO_TMDS_CTRL_CLEAR_BALANCE 2192 // Description : Clear the running DC balance state of the TMDS encoders. This 2193 // bit should be written once at the beginning of each scanline. 2194 #define SIO_TMDS_CTRL_CLEAR_BALANCE_RESET _u(0x0) 2195 #define SIO_TMDS_CTRL_CLEAR_BALANCE_BITS _u(0x10000000) 2196 #define SIO_TMDS_CTRL_CLEAR_BALANCE_MSB _u(28) 2197 #define SIO_TMDS_CTRL_CLEAR_BALANCE_LSB _u(28) 2198 #define SIO_TMDS_CTRL_CLEAR_BALANCE_ACCESS "SC" 2199 // ----------------------------------------------------------------------------- 2200 // Field : SIO_TMDS_CTRL_PIX2_NOSHIFT 2201 // Description : When encoding two pixels's worth of symbols in one cycle (a 2202 // read of a PEEK/POP_DOUBLE register), the second encoder sees a 2203 // shifted version of the colour data register. 2204 // 2205 // This control disables that shift, so that both encoder layers 2206 // see the same pixel data. This is used for pixel doubling. 2207 #define SIO_TMDS_CTRL_PIX2_NOSHIFT_RESET _u(0x0) 2208 #define SIO_TMDS_CTRL_PIX2_NOSHIFT_BITS _u(0x08000000) 2209 #define SIO_TMDS_CTRL_PIX2_NOSHIFT_MSB _u(27) 2210 #define SIO_TMDS_CTRL_PIX2_NOSHIFT_LSB _u(27) 2211 #define SIO_TMDS_CTRL_PIX2_NOSHIFT_ACCESS "RW" 2212 // ----------------------------------------------------------------------------- 2213 // Field : SIO_TMDS_CTRL_PIX_SHIFT 2214 // Description : Shift applied to the colour data register with each read of a 2215 // POP alias register. 2216 // 2217 // Reading from the POP_SINGLE register, or reading from the 2218 // POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), 2219 // shifts by the indicated amount. 2220 // 2221 // Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear 2222 // will shift by double the indicated amount. (Shift by 32 means 2223 // no shift.) 2224 // 0x0 -> Do not shift the colour data register. 2225 // 0x1 -> Shift the colour data register by 1 bit 2226 // 0x2 -> Shift the colour data register by 2 bits 2227 // 0x3 -> Shift the colour data register by 4 bits 2228 // 0x4 -> Shift the colour data register by 8 bits 2229 // 0x5 -> Shift the colour data register by 16 bits 2230 #define SIO_TMDS_CTRL_PIX_SHIFT_RESET _u(0x0) 2231 #define SIO_TMDS_CTRL_PIX_SHIFT_BITS _u(0x07000000) 2232 #define SIO_TMDS_CTRL_PIX_SHIFT_MSB _u(26) 2233 #define SIO_TMDS_CTRL_PIX_SHIFT_LSB _u(24) 2234 #define SIO_TMDS_CTRL_PIX_SHIFT_ACCESS "RW" 2235 #define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_0 _u(0x0) 2236 #define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_1 _u(0x1) 2237 #define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_2 _u(0x2) 2238 #define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_4 _u(0x3) 2239 #define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_8 _u(0x4) 2240 #define SIO_TMDS_CTRL_PIX_SHIFT_VALUE_16 _u(0x5) 2241 // ----------------------------------------------------------------------------- 2242 // Field : SIO_TMDS_CTRL_INTERLEAVE 2243 // Description : Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. 2244 // 2245 // When interleaving is disabled, each of the 3 symbols appears as 2246 // a contiguous 10-bit field, with lane 0 being the least- 2247 // significant and starting at bit 0 of the register. 2248 // 2249 // When interleaving is enabled, the symbols are packed into 5 2250 // chunks of 3 lanes times 2 bits (30 bits total). Each chunk 2251 // contains two bits of a TMDS symbol per lane, with lane 0 being 2252 // the least significant. 2253 #define SIO_TMDS_CTRL_INTERLEAVE_RESET _u(0x0) 2254 #define SIO_TMDS_CTRL_INTERLEAVE_BITS _u(0x00800000) 2255 #define SIO_TMDS_CTRL_INTERLEAVE_MSB _u(23) 2256 #define SIO_TMDS_CTRL_INTERLEAVE_LSB _u(23) 2257 #define SIO_TMDS_CTRL_INTERLEAVE_ACCESS "RW" 2258 // ----------------------------------------------------------------------------- 2259 // Field : SIO_TMDS_CTRL_L2_NBITS 2260 // Description : Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 2261 // through 7). Remaining LSBs are masked to 0 after the rotate. 2262 #define SIO_TMDS_CTRL_L2_NBITS_RESET _u(0x0) 2263 #define SIO_TMDS_CTRL_L2_NBITS_BITS _u(0x001c0000) 2264 #define SIO_TMDS_CTRL_L2_NBITS_MSB _u(20) 2265 #define SIO_TMDS_CTRL_L2_NBITS_LSB _u(18) 2266 #define SIO_TMDS_CTRL_L2_NBITS_ACCESS "RW" 2267 // ----------------------------------------------------------------------------- 2268 // Field : SIO_TMDS_CTRL_L1_NBITS 2269 // Description : Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 2270 // through 7). Remaining LSBs are masked to 0 after the rotate. 2271 #define SIO_TMDS_CTRL_L1_NBITS_RESET _u(0x0) 2272 #define SIO_TMDS_CTRL_L1_NBITS_BITS _u(0x00038000) 2273 #define SIO_TMDS_CTRL_L1_NBITS_MSB _u(17) 2274 #define SIO_TMDS_CTRL_L1_NBITS_LSB _u(15) 2275 #define SIO_TMDS_CTRL_L1_NBITS_ACCESS "RW" 2276 // ----------------------------------------------------------------------------- 2277 // Field : SIO_TMDS_CTRL_L0_NBITS 2278 // Description : Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 2279 // through 7). Remaining LSBs are masked to 0 after the rotate. 2280 #define SIO_TMDS_CTRL_L0_NBITS_RESET _u(0x0) 2281 #define SIO_TMDS_CTRL_L0_NBITS_BITS _u(0x00007000) 2282 #define SIO_TMDS_CTRL_L0_NBITS_MSB _u(14) 2283 #define SIO_TMDS_CTRL_L0_NBITS_LSB _u(12) 2284 #define SIO_TMDS_CTRL_L0_NBITS_ACCESS "RW" 2285 // ----------------------------------------------------------------------------- 2286 // Field : SIO_TMDS_CTRL_L2_ROT 2287 // Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 2288 // bits, in order to get the MSB of the lane 2 (red) colour data 2289 // aligned with the MSB of the 8-bit encoder input. 2290 // 2291 // For example, for RGB565 (red most significant), red is bits 2292 // 15:11, so should be right-rotated by 8 bits to align with bits 2293 // 7:3 of the encoder input. 2294 #define SIO_TMDS_CTRL_L2_ROT_RESET _u(0x0) 2295 #define SIO_TMDS_CTRL_L2_ROT_BITS _u(0x00000f00) 2296 #define SIO_TMDS_CTRL_L2_ROT_MSB _u(11) 2297 #define SIO_TMDS_CTRL_L2_ROT_LSB _u(8) 2298 #define SIO_TMDS_CTRL_L2_ROT_ACCESS "RW" 2299 // ----------------------------------------------------------------------------- 2300 // Field : SIO_TMDS_CTRL_L1_ROT 2301 // Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 2302 // bits, in order to get the MSB of the lane 1 (green) colour data 2303 // aligned with the MSB of the 8-bit encoder input. 2304 // 2305 // For example, for RGB565, green is bits 10:5, so should be 2306 // right-rotated by 3 bits to align with bits 7:2 of the encoder 2307 // input. 2308 #define SIO_TMDS_CTRL_L1_ROT_RESET _u(0x0) 2309 #define SIO_TMDS_CTRL_L1_ROT_BITS _u(0x000000f0) 2310 #define SIO_TMDS_CTRL_L1_ROT_MSB _u(7) 2311 #define SIO_TMDS_CTRL_L1_ROT_LSB _u(4) 2312 #define SIO_TMDS_CTRL_L1_ROT_ACCESS "RW" 2313 // ----------------------------------------------------------------------------- 2314 // Field : SIO_TMDS_CTRL_L0_ROT 2315 // Description : Right-rotate the 16 LSBs of the colour accumulator by 0-15 2316 // bits, in order to get the MSB of the lane 0 (blue) colour data 2317 // aligned with the MSB of the 8-bit encoder input. 2318 // 2319 // For example, for RGB565 (red most significant), blue is bits 2320 // 4:0, so should be right-rotated by 13 to align with bits 7:3 of 2321 // the encoder input. 2322 #define SIO_TMDS_CTRL_L0_ROT_RESET _u(0x0) 2323 #define SIO_TMDS_CTRL_L0_ROT_BITS _u(0x0000000f) 2324 #define SIO_TMDS_CTRL_L0_ROT_MSB _u(3) 2325 #define SIO_TMDS_CTRL_L0_ROT_LSB _u(0) 2326 #define SIO_TMDS_CTRL_L0_ROT_ACCESS "RW" 2327 // ============================================================================= 2328 // Register : SIO_TMDS_WDATA 2329 // Description : Write-only access to the TMDS colour data register. 2330 #define SIO_TMDS_WDATA_OFFSET _u(0x000001c4) 2331 #define SIO_TMDS_WDATA_BITS _u(0xffffffff) 2332 #define SIO_TMDS_WDATA_RESET _u(0x00000000) 2333 #define SIO_TMDS_WDATA_MSB _u(31) 2334 #define SIO_TMDS_WDATA_LSB _u(0) 2335 #define SIO_TMDS_WDATA_ACCESS "WO" 2336 // ============================================================================= 2337 // Register : SIO_TMDS_PEEK_SINGLE 2338 // Description : Get the encoding of one pixel's worth of colour data, packed 2339 // into a 32-bit value (3x10-bit symbols). 2340 // 2341 // The PEEK alias does not shift the colour register when read, 2342 // but still advances the running DC balance state of each 2343 // encoder. This is useful for pixel doubling. 2344 #define SIO_TMDS_PEEK_SINGLE_OFFSET _u(0x000001c8) 2345 #define SIO_TMDS_PEEK_SINGLE_BITS _u(0xffffffff) 2346 #define SIO_TMDS_PEEK_SINGLE_RESET _u(0x00000000) 2347 #define SIO_TMDS_PEEK_SINGLE_MSB _u(31) 2348 #define SIO_TMDS_PEEK_SINGLE_LSB _u(0) 2349 #define SIO_TMDS_PEEK_SINGLE_ACCESS "RF" 2350 // ============================================================================= 2351 // Register : SIO_TMDS_POP_SINGLE 2352 // Description : Get the encoding of one pixel's worth of colour data, packed 2353 // into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 2354 // bits (30 bits total). Each chunk contains two bits of a TMDS 2355 // symbol per lane. This format is intended for shifting out with 2356 // the HSTX peripheral on RP2350. 2357 // 2358 // The POP alias shifts the colour register when read, as well as 2359 // advancing the running DC balance state of each encoder. 2360 #define SIO_TMDS_POP_SINGLE_OFFSET _u(0x000001cc) 2361 #define SIO_TMDS_POP_SINGLE_BITS _u(0xffffffff) 2362 #define SIO_TMDS_POP_SINGLE_RESET _u(0x00000000) 2363 #define SIO_TMDS_POP_SINGLE_MSB _u(31) 2364 #define SIO_TMDS_POP_SINGLE_LSB _u(0) 2365 #define SIO_TMDS_POP_SINGLE_ACCESS "RF" 2366 // ============================================================================= 2367 // Register : SIO_TMDS_PEEK_DOUBLE_L0 2368 // Description : Get lane 0 of the encoding of two pixels' worth of colour data. 2369 // Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 2370 // word. 2371 // 2372 // The PEEK alias does not shift the colour register when read, 2373 // but still advances the lane 0 DC balance state. This is useful 2374 // if all 3 lanes' worth of encode are to be read at once, rather 2375 // than processing the entire scanline for one lane before moving 2376 // to the next lane. 2377 #define SIO_TMDS_PEEK_DOUBLE_L0_OFFSET _u(0x000001d0) 2378 #define SIO_TMDS_PEEK_DOUBLE_L0_BITS _u(0xffffffff) 2379 #define SIO_TMDS_PEEK_DOUBLE_L0_RESET _u(0x00000000) 2380 #define SIO_TMDS_PEEK_DOUBLE_L0_MSB _u(31) 2381 #define SIO_TMDS_PEEK_DOUBLE_L0_LSB _u(0) 2382 #define SIO_TMDS_PEEK_DOUBLE_L0_ACCESS "RF" 2383 // ============================================================================= 2384 // Register : SIO_TMDS_POP_DOUBLE_L0 2385 // Description : Get lane 0 of the encoding of two pixels' worth of colour data. 2386 // Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 2387 // word. 2388 // 2389 // The POP alias shifts the colour register when read, according 2390 // to the values of PIX_SHIFT and PIX2_NOSHIFT. 2391 #define SIO_TMDS_POP_DOUBLE_L0_OFFSET _u(0x000001d4) 2392 #define SIO_TMDS_POP_DOUBLE_L0_BITS _u(0xffffffff) 2393 #define SIO_TMDS_POP_DOUBLE_L0_RESET _u(0x00000000) 2394 #define SIO_TMDS_POP_DOUBLE_L0_MSB _u(31) 2395 #define SIO_TMDS_POP_DOUBLE_L0_LSB _u(0) 2396 #define SIO_TMDS_POP_DOUBLE_L0_ACCESS "RF" 2397 // ============================================================================= 2398 // Register : SIO_TMDS_PEEK_DOUBLE_L1 2399 // Description : Get lane 1 of the encoding of two pixels' worth of colour data. 2400 // Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 2401 // word. 2402 // 2403 // The PEEK alias does not shift the colour register when read, 2404 // but still advances the lane 1 DC balance state. This is useful 2405 // if all 3 lanes' worth of encode are to be read at once, rather 2406 // than processing the entire scanline for one lane before moving 2407 // to the next lane. 2408 #define SIO_TMDS_PEEK_DOUBLE_L1_OFFSET _u(0x000001d8) 2409 #define SIO_TMDS_PEEK_DOUBLE_L1_BITS _u(0xffffffff) 2410 #define SIO_TMDS_PEEK_DOUBLE_L1_RESET _u(0x00000000) 2411 #define SIO_TMDS_PEEK_DOUBLE_L1_MSB _u(31) 2412 #define SIO_TMDS_PEEK_DOUBLE_L1_LSB _u(0) 2413 #define SIO_TMDS_PEEK_DOUBLE_L1_ACCESS "RF" 2414 // ============================================================================= 2415 // Register : SIO_TMDS_POP_DOUBLE_L1 2416 // Description : Get lane 1 of the encoding of two pixels' worth of colour data. 2417 // Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 2418 // word. 2419 // 2420 // The POP alias shifts the colour register when read, according 2421 // to the values of PIX_SHIFT and PIX2_NOSHIFT. 2422 #define SIO_TMDS_POP_DOUBLE_L1_OFFSET _u(0x000001dc) 2423 #define SIO_TMDS_POP_DOUBLE_L1_BITS _u(0xffffffff) 2424 #define SIO_TMDS_POP_DOUBLE_L1_RESET _u(0x00000000) 2425 #define SIO_TMDS_POP_DOUBLE_L1_MSB _u(31) 2426 #define SIO_TMDS_POP_DOUBLE_L1_LSB _u(0) 2427 #define SIO_TMDS_POP_DOUBLE_L1_ACCESS "RF" 2428 // ============================================================================= 2429 // Register : SIO_TMDS_PEEK_DOUBLE_L2 2430 // Description : Get lane 2 of the encoding of two pixels' worth of colour data. 2431 // Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 2432 // word. 2433 // 2434 // The PEEK alias does not shift the colour register when read, 2435 // but still advances the lane 2 DC balance state. This is useful 2436 // if all 3 lanes' worth of encode are to be read at once, rather 2437 // than processing the entire scanline for one lane before moving 2438 // to the next lane. 2439 #define SIO_TMDS_PEEK_DOUBLE_L2_OFFSET _u(0x000001e0) 2440 #define SIO_TMDS_PEEK_DOUBLE_L2_BITS _u(0xffffffff) 2441 #define SIO_TMDS_PEEK_DOUBLE_L2_RESET _u(0x00000000) 2442 #define SIO_TMDS_PEEK_DOUBLE_L2_MSB _u(31) 2443 #define SIO_TMDS_PEEK_DOUBLE_L2_LSB _u(0) 2444 #define SIO_TMDS_PEEK_DOUBLE_L2_ACCESS "RF" 2445 // ============================================================================= 2446 // Register : SIO_TMDS_POP_DOUBLE_L2 2447 // Description : Get lane 2 of the encoding of two pixels' worth of colour data. 2448 // Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 2449 // word. 2450 // 2451 // The POP alias shifts the colour register when read, according 2452 // to the values of PIX_SHIFT and PIX2_NOSHIFT. 2453 #define SIO_TMDS_POP_DOUBLE_L2_OFFSET _u(0x000001e4) 2454 #define SIO_TMDS_POP_DOUBLE_L2_BITS _u(0xffffffff) 2455 #define SIO_TMDS_POP_DOUBLE_L2_RESET _u(0x00000000) 2456 #define SIO_TMDS_POP_DOUBLE_L2_MSB _u(31) 2457 #define SIO_TMDS_POP_DOUBLE_L2_LSB _u(0) 2458 #define SIO_TMDS_POP_DOUBLE_L2_ACCESS "RF" 2459 // ============================================================================= 2460 #endif // _HARDWARE_REGS_SIO_H 2461 2462
