1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : RVCSR 10 // Version : 1 11 // Bus type : apb 12 // Description : CSR listing for Hazard3 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_RVCSR_H 15 #define _HARDWARE_REGS_RVCSR_H 16 // ============================================================================= 17 // Register : RVCSR_MSTATUS 18 // Description : Machine status register 19 #define RVCSR_MSTATUS_OFFSET _u(0x00000300) 20 #define RVCSR_MSTATUS_BITS _u(0x00221888) 21 #define RVCSR_MSTATUS_RESET _u(0x00001800) 22 // ----------------------------------------------------------------------------- 23 // Field : RVCSR_MSTATUS_TW 24 // Description : Timeout wait. When 1, attempting to execute a WFI instruction 25 // in U-mode will instantly cause an illegal instruction 26 // exception. 27 #define RVCSR_MSTATUS_TW_RESET _u(0x0) 28 #define RVCSR_MSTATUS_TW_BITS _u(0x00200000) 29 #define RVCSR_MSTATUS_TW_MSB _u(21) 30 #define RVCSR_MSTATUS_TW_LSB _u(21) 31 #define RVCSR_MSTATUS_TW_ACCESS "RW" 32 // ----------------------------------------------------------------------------- 33 // Field : RVCSR_MSTATUS_MPRV 34 // Description : Modify privilege. If 1, loads and stores behave as though the 35 // current privilege level were `mpp`. This includes physical 36 // memory protection checks, and the privilege level asserted on 37 // the system bus alongside the load/store address. 38 #define RVCSR_MSTATUS_MPRV_RESET _u(0x0) 39 #define RVCSR_MSTATUS_MPRV_BITS _u(0x00020000) 40 #define RVCSR_MSTATUS_MPRV_MSB _u(17) 41 #define RVCSR_MSTATUS_MPRV_LSB _u(17) 42 #define RVCSR_MSTATUS_MPRV_ACCESS "RW" 43 // ----------------------------------------------------------------------------- 44 // Field : RVCSR_MSTATUS_MPP 45 // Description : Previous privilege level. Can store the values 3 (M-mode) or 0 46 // (U-mode). If another value is written, hardware rounds to the 47 // nearest supported mode. 48 #define RVCSR_MSTATUS_MPP_RESET _u(0x3) 49 #define RVCSR_MSTATUS_MPP_BITS _u(0x00001800) 50 #define RVCSR_MSTATUS_MPP_MSB _u(12) 51 #define RVCSR_MSTATUS_MPP_LSB _u(11) 52 #define RVCSR_MSTATUS_MPP_ACCESS "RW" 53 // ----------------------------------------------------------------------------- 54 // Field : RVCSR_MSTATUS_MPIE 55 // Description : Previous interrupt enable. Readable and writable. Is set to the 56 // current value of `mstatus.mie` on trap entry. Is set to 1 on 57 // trap return. 58 #define RVCSR_MSTATUS_MPIE_RESET _u(0x0) 59 #define RVCSR_MSTATUS_MPIE_BITS _u(0x00000080) 60 #define RVCSR_MSTATUS_MPIE_MSB _u(7) 61 #define RVCSR_MSTATUS_MPIE_LSB _u(7) 62 #define RVCSR_MSTATUS_MPIE_ACCESS "RW" 63 // ----------------------------------------------------------------------------- 64 // Field : RVCSR_MSTATUS_MIE 65 // Description : Interrupt enable. Readable and writable. Is set to 0 on trap 66 // entry. Is set to the current value of `mstatus.mpie` on trap 67 // return. 68 #define RVCSR_MSTATUS_MIE_RESET _u(0x0) 69 #define RVCSR_MSTATUS_MIE_BITS _u(0x00000008) 70 #define RVCSR_MSTATUS_MIE_MSB _u(3) 71 #define RVCSR_MSTATUS_MIE_LSB _u(3) 72 #define RVCSR_MSTATUS_MIE_ACCESS "RW" 73 // ============================================================================= 74 // Register : RVCSR_MISA 75 // Description : Summary of ISA extension support 76 // 77 // On RP2350, Hazard3's full `-march` string is: 78 // `rv32ima_zicsr_zifencei_zba_zbb_zbs_zbkb_zca_zcb_zcmp` 79 // 80 // Note Zca is equivalent to the C extension in this case; all 81 // instructions from the RISC-V C extension relevant to a 32-bit 82 // non-floating-point processor are supported. On older toolchains 83 // which do not support the Zc extensions, the appropriate 84 // `-march` string is: `rv32imac_zicsr_zifencei_zba_zbb_zbs_zbkb` 85 // 86 // In addition the following custom extensions are configured: 87 // Xh3bm, Xh3power, Xh3irq, Xh3pmpm 88 #define RVCSR_MISA_OFFSET _u(0x00000301) 89 #define RVCSR_MISA_BITS _u(0xc0901107) 90 #define RVCSR_MISA_RESET _u(0x40901105) 91 // ----------------------------------------------------------------------------- 92 // Field : RVCSR_MISA_MXL 93 // Description : Value of 0x1 indicates this is a 32-bit processor. 94 #define RVCSR_MISA_MXL_RESET _u(0x1) 95 #define RVCSR_MISA_MXL_BITS _u(0xc0000000) 96 #define RVCSR_MISA_MXL_MSB _u(31) 97 #define RVCSR_MISA_MXL_LSB _u(30) 98 #define RVCSR_MISA_MXL_ACCESS "RO" 99 // ----------------------------------------------------------------------------- 100 // Field : RVCSR_MISA_X 101 // Description : Value of 1 indicates nonstandard extensions are present. (Xh3b 102 // bit manipulation, and custom sleep and interrupt control CSRs) 103 #define RVCSR_MISA_X_RESET _u(0x1) 104 #define RVCSR_MISA_X_BITS _u(0x00800000) 105 #define RVCSR_MISA_X_MSB _u(23) 106 #define RVCSR_MISA_X_LSB _u(23) 107 #define RVCSR_MISA_X_ACCESS "RO" 108 // ----------------------------------------------------------------------------- 109 // Field : RVCSR_MISA_U 110 // Description : Value of 1 indicates U-mode is implemented. 111 #define RVCSR_MISA_U_RESET _u(0x1) 112 #define RVCSR_MISA_U_BITS _u(0x00100000) 113 #define RVCSR_MISA_U_MSB _u(20) 114 #define RVCSR_MISA_U_LSB _u(20) 115 #define RVCSR_MISA_U_ACCESS "RO" 116 // ----------------------------------------------------------------------------- 117 // Field : RVCSR_MISA_M 118 // Description : Value of 1 indicates the M extension (integer multiply/divide) 119 // is implemented. 120 #define RVCSR_MISA_M_RESET _u(0x1) 121 #define RVCSR_MISA_M_BITS _u(0x00001000) 122 #define RVCSR_MISA_M_MSB _u(12) 123 #define RVCSR_MISA_M_LSB _u(12) 124 #define RVCSR_MISA_M_ACCESS "RO" 125 // ----------------------------------------------------------------------------- 126 // Field : RVCSR_MISA_I 127 // Description : Value of 1 indicates the RVI base ISA is implemented (as 128 // opposed to RVE) 129 #define RVCSR_MISA_I_RESET _u(0x1) 130 #define RVCSR_MISA_I_BITS _u(0x00000100) 131 #define RVCSR_MISA_I_MSB _u(8) 132 #define RVCSR_MISA_I_LSB _u(8) 133 #define RVCSR_MISA_I_ACCESS "RO" 134 // ----------------------------------------------------------------------------- 135 // Field : RVCSR_MISA_C 136 // Description : Value of 1 indicates the C extension (compressed instructions) 137 // is implemented. 138 #define RVCSR_MISA_C_RESET _u(0x1) 139 #define RVCSR_MISA_C_BITS _u(0x00000004) 140 #define RVCSR_MISA_C_MSB _u(2) 141 #define RVCSR_MISA_C_LSB _u(2) 142 #define RVCSR_MISA_C_ACCESS "RO" 143 // ----------------------------------------------------------------------------- 144 // Field : RVCSR_MISA_B 145 // Description : Value of 1 indicates the B extension (bit manipulation) is 146 // implemented. B is the combination of Zba, Zbb and Zbs. 147 // 148 // Hazard3 implements all of these extensions, but the definition 149 // of B as ZbaZbbZbs did not exist at the point this version of 150 // Hazard3 was taped out. This bit was reserved-0 at that point. 151 // Therefore this bit reads as 0. 152 #define RVCSR_MISA_B_RESET _u(0x0) 153 #define RVCSR_MISA_B_BITS _u(0x00000002) 154 #define RVCSR_MISA_B_MSB _u(1) 155 #define RVCSR_MISA_B_LSB _u(1) 156 #define RVCSR_MISA_B_ACCESS "RO" 157 // ----------------------------------------------------------------------------- 158 // Field : RVCSR_MISA_A 159 // Description : Value of 1 indicates the A extension (atomics) is implemented. 160 #define RVCSR_MISA_A_RESET _u(0x1) 161 #define RVCSR_MISA_A_BITS _u(0x00000001) 162 #define RVCSR_MISA_A_MSB _u(0) 163 #define RVCSR_MISA_A_LSB _u(0) 164 #define RVCSR_MISA_A_ACCESS "RO" 165 // ============================================================================= 166 // Register : RVCSR_MEDELEG 167 // Description : Machine exception delegation register. Not implemented, as no 168 // S-mode support. 169 #define RVCSR_MEDELEG_OFFSET _u(0x00000302) 170 #define RVCSR_MEDELEG_BITS _u(0xffffffff) 171 #define RVCSR_MEDELEG_RESET "-" 172 #define RVCSR_MEDELEG_MSB _u(31) 173 #define RVCSR_MEDELEG_LSB _u(0) 174 #define RVCSR_MEDELEG_ACCESS "RW" 175 // ============================================================================= 176 // Register : RVCSR_MIDELEG 177 // Description : Machine interrupt delegation register. Not implemented, as no 178 // S-mode support. 179 #define RVCSR_MIDELEG_OFFSET _u(0x00000303) 180 #define RVCSR_MIDELEG_BITS _u(0xffffffff) 181 #define RVCSR_MIDELEG_RESET "-" 182 #define RVCSR_MIDELEG_MSB _u(31) 183 #define RVCSR_MIDELEG_LSB _u(0) 184 #define RVCSR_MIDELEG_ACCESS "RW" 185 // ============================================================================= 186 // Register : RVCSR_MIE 187 // Description : Machine interrupt enable register 188 #define RVCSR_MIE_OFFSET _u(0x00000304) 189 #define RVCSR_MIE_BITS _u(0x00000888) 190 #define RVCSR_MIE_RESET _u(0x00000000) 191 // ----------------------------------------------------------------------------- 192 // Field : RVCSR_MIE_MEIE 193 // Description : External interrupt enable. The processor transfers to the 194 // external interrupt vector when `mie.meie`, `mip.meip` and 195 // `mstatus.mie` are all 1. 196 // 197 // Hazard3 has internal registers to individually filter external 198 // interrupts (see `meiea`), but this standard control can be used 199 // to mask all external interrupts at once. 200 #define RVCSR_MIE_MEIE_RESET _u(0x0) 201 #define RVCSR_MIE_MEIE_BITS _u(0x00000800) 202 #define RVCSR_MIE_MEIE_MSB _u(11) 203 #define RVCSR_MIE_MEIE_LSB _u(11) 204 #define RVCSR_MIE_MEIE_ACCESS "RW" 205 // ----------------------------------------------------------------------------- 206 // Field : RVCSR_MIE_MTIE 207 // Description : Timer interrupt enable. The processor transfers to the timer 208 // interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` 209 // are all 1, unless a software or external interrupt request is 210 // also valid at this time. 211 #define RVCSR_MIE_MTIE_RESET _u(0x0) 212 #define RVCSR_MIE_MTIE_BITS _u(0x00000080) 213 #define RVCSR_MIE_MTIE_MSB _u(7) 214 #define RVCSR_MIE_MTIE_LSB _u(7) 215 #define RVCSR_MIE_MTIE_ACCESS "RW" 216 // ----------------------------------------------------------------------------- 217 // Field : RVCSR_MIE_MSIE 218 // Description : Software interrupt enable. The processor transfers to the 219 // software interrupt vector `mie.msie`, `mip.msip` and 220 // `mstatus.mie` are all 1, unless an external interrupt request 221 // is also valid at this time. 222 #define RVCSR_MIE_MSIE_RESET _u(0x0) 223 #define RVCSR_MIE_MSIE_BITS _u(0x00000008) 224 #define RVCSR_MIE_MSIE_MSB _u(3) 225 #define RVCSR_MIE_MSIE_LSB _u(3) 226 #define RVCSR_MIE_MSIE_ACCESS "RW" 227 // ============================================================================= 228 // Register : RVCSR_MTVEC 229 // Description : Machine trap handler base address. 230 #define RVCSR_MTVEC_OFFSET _u(0x00000305) 231 #define RVCSR_MTVEC_BITS _u(0xffffffff) 232 #define RVCSR_MTVEC_RESET _u(0x00007ffc) 233 // ----------------------------------------------------------------------------- 234 // Field : RVCSR_MTVEC_BASE 235 // Description : The upper 30 bits of the trap vector address (2 LSBs are 236 // implicitly 0). Must be 64-byte-aligned if vectoring is enabled. 237 // Otherwise, must be 4-byte-aligned. 238 #define RVCSR_MTVEC_BASE_RESET _u(0x00001fff) 239 #define RVCSR_MTVEC_BASE_BITS _u(0xfffffffc) 240 #define RVCSR_MTVEC_BASE_MSB _u(31) 241 #define RVCSR_MTVEC_BASE_LSB _u(2) 242 #define RVCSR_MTVEC_BASE_ACCESS "RW" 243 // ----------------------------------------------------------------------------- 244 // Field : RVCSR_MTVEC_MODE 245 // Description : If 0 (direct mode), all traps set pc to the trap vector base. 246 // If 1 (vectored), exceptions set pc to the trap vector base, and 247 // interrupts set pc to 4 times the interrupt cause (3=soft IRQ, 248 // 7=timer IRQ, 11=external IRQ). 249 // 250 // The upper bit is hardwired to zero, so attempting to set mode 251 // to 2 or 3 will result in a value of 0 or 1 respectively. 252 // 0x0 -> Direct entry to mtvec 253 // 0x1 -> Vectored entry to a 16-entry jump table starting at mtvec 254 #define RVCSR_MTVEC_MODE_RESET _u(0x0) 255 #define RVCSR_MTVEC_MODE_BITS _u(0x00000003) 256 #define RVCSR_MTVEC_MODE_MSB _u(1) 257 #define RVCSR_MTVEC_MODE_LSB _u(0) 258 #define RVCSR_MTVEC_MODE_ACCESS "RW" 259 #define RVCSR_MTVEC_MODE_VALUE_DIRECT _u(0x0) 260 #define RVCSR_MTVEC_MODE_VALUE_VECTORED _u(0x1) 261 // ============================================================================= 262 // Register : RVCSR_MCOUNTEREN 263 // Description : Counter enable. Control access to counters from U-mode. Not to 264 // be confused with mcountinhibit. 265 #define RVCSR_MCOUNTEREN_OFFSET _u(0x00000306) 266 #define RVCSR_MCOUNTEREN_BITS _u(0x00000007) 267 #define RVCSR_MCOUNTEREN_RESET _u(0x00000000) 268 // ----------------------------------------------------------------------------- 269 // Field : RVCSR_MCOUNTEREN_IR 270 // Description : If 1, U-mode is permitted to access the `instret`/`instreth` 271 // instruction retire counter CSRs. Otherwise, U-mode accesses to 272 // these CSRs will trap. 273 #define RVCSR_MCOUNTEREN_IR_RESET _u(0x0) 274 #define RVCSR_MCOUNTEREN_IR_BITS _u(0x00000004) 275 #define RVCSR_MCOUNTEREN_IR_MSB _u(2) 276 #define RVCSR_MCOUNTEREN_IR_LSB _u(2) 277 #define RVCSR_MCOUNTEREN_IR_ACCESS "RW" 278 // ----------------------------------------------------------------------------- 279 // Field : RVCSR_MCOUNTEREN_TM 280 // Description : No hardware effect, as the `time`/`timeh` CSRs are not 281 // implemented. However, this field still exists, as M-mode 282 // software can use it to track whether it should emulate U-mode 283 // attempts to access those CSRs. 284 #define RVCSR_MCOUNTEREN_TM_RESET _u(0x0) 285 #define RVCSR_MCOUNTEREN_TM_BITS _u(0x00000002) 286 #define RVCSR_MCOUNTEREN_TM_MSB _u(1) 287 #define RVCSR_MCOUNTEREN_TM_LSB _u(1) 288 #define RVCSR_MCOUNTEREN_TM_ACCESS "RW" 289 // ----------------------------------------------------------------------------- 290 // Field : RVCSR_MCOUNTEREN_CY 291 // Description : If 1, U-mode is permitted to access the `cycle`/`cycleh` cycle 292 // counter CSRs. Otherwise, U-mode accesses to these CSRs will 293 // trap. 294 #define RVCSR_MCOUNTEREN_CY_RESET _u(0x0) 295 #define RVCSR_MCOUNTEREN_CY_BITS _u(0x00000001) 296 #define RVCSR_MCOUNTEREN_CY_MSB _u(0) 297 #define RVCSR_MCOUNTEREN_CY_LSB _u(0) 298 #define RVCSR_MCOUNTEREN_CY_ACCESS "RW" 299 // ============================================================================= 300 // Register : RVCSR_MENVCFG 301 // Description : Machine environment configuration register, low half 302 #define RVCSR_MENVCFG_OFFSET _u(0x0000030a) 303 #define RVCSR_MENVCFG_BITS _u(0x00000001) 304 #define RVCSR_MENVCFG_RESET _u(0x00000000) 305 // ----------------------------------------------------------------------------- 306 // Field : RVCSR_MENVCFG_FIOM 307 // Description : When set, fence instructions in modes less privileged than 308 // M-mode which specify that IO memory accesses are ordered will 309 // also cause ordering of main memory accesses. 310 // 311 // FIOM is hardwired to zero on Hazard3, because S-mode is not 312 // supported, and because fence instructions execute as NOPs (with 313 // the exception of `fence.i`) 314 #define RVCSR_MENVCFG_FIOM_RESET _u(0x0) 315 #define RVCSR_MENVCFG_FIOM_BITS _u(0x00000001) 316 #define RVCSR_MENVCFG_FIOM_MSB _u(0) 317 #define RVCSR_MENVCFG_FIOM_LSB _u(0) 318 #define RVCSR_MENVCFG_FIOM_ACCESS "RO" 319 // ============================================================================= 320 // Register : RVCSR_MSTATUSH 321 // Description : High half of mstatus, hardwired to 0. 322 #define RVCSR_MSTATUSH_OFFSET _u(0x00000310) 323 #define RVCSR_MSTATUSH_BITS _u(0xffffffff) 324 #define RVCSR_MSTATUSH_RESET _u(0x00000000) 325 #define RVCSR_MSTATUSH_MSB _u(31) 326 #define RVCSR_MSTATUSH_LSB _u(0) 327 #define RVCSR_MSTATUSH_ACCESS "RO" 328 // ============================================================================= 329 // Register : RVCSR_MENVCFGH 330 // Description : Machine environment configuration register, high half 331 // 332 // This register is fully reserved, as Hazard3 does not implement 333 // the relevant extensions. It is implemented as hardwired-0. 334 #define RVCSR_MENVCFGH_OFFSET _u(0x0000031a) 335 #define RVCSR_MENVCFGH_BITS _u(0x00000000) 336 #define RVCSR_MENVCFGH_RESET _u(0x00000000) 337 #define RVCSR_MENVCFGH_MSB _u(31) 338 #define RVCSR_MENVCFGH_LSB _u(0) 339 #define RVCSR_MENVCFGH_ACCESS "RW" 340 // ============================================================================= 341 // Register : RVCSR_MCOUNTINHIBIT 342 // Description : Count inhibit register for `mcycle`/`minstret` 343 #define RVCSR_MCOUNTINHIBIT_OFFSET _u(0x00000320) 344 #define RVCSR_MCOUNTINHIBIT_BITS _u(0x00000005) 345 #define RVCSR_MCOUNTINHIBIT_RESET _u(0x00000005) 346 // ----------------------------------------------------------------------------- 347 // Field : RVCSR_MCOUNTINHIBIT_IR 348 // Description : Inhibit counting of the `minstret` and `minstreth` registers. 349 // Set by default to save power. 350 #define RVCSR_MCOUNTINHIBIT_IR_RESET _u(0x1) 351 #define RVCSR_MCOUNTINHIBIT_IR_BITS _u(0x00000004) 352 #define RVCSR_MCOUNTINHIBIT_IR_MSB _u(2) 353 #define RVCSR_MCOUNTINHIBIT_IR_LSB _u(2) 354 #define RVCSR_MCOUNTINHIBIT_IR_ACCESS "RW" 355 // ----------------------------------------------------------------------------- 356 // Field : RVCSR_MCOUNTINHIBIT_CY 357 // Description : Inhibit counting of the `mcycle` and `mcycleh` registers. Set 358 // by default to save power. 359 #define RVCSR_MCOUNTINHIBIT_CY_RESET _u(0x1) 360 #define RVCSR_MCOUNTINHIBIT_CY_BITS _u(0x00000001) 361 #define RVCSR_MCOUNTINHIBIT_CY_MSB _u(0) 362 #define RVCSR_MCOUNTINHIBIT_CY_LSB _u(0) 363 #define RVCSR_MCOUNTINHIBIT_CY_ACCESS "RW" 364 // ============================================================================= 365 // Register : RVCSR_MHPMEVENT3 366 // Description : Extended performance event selector, hardwired to 0. 367 #define RVCSR_MHPMEVENT3_OFFSET _u(0x00000323) 368 #define RVCSR_MHPMEVENT3_BITS _u(0xffffffff) 369 #define RVCSR_MHPMEVENT3_RESET _u(0x00000000) 370 #define RVCSR_MHPMEVENT3_MSB _u(31) 371 #define RVCSR_MHPMEVENT3_LSB _u(0) 372 #define RVCSR_MHPMEVENT3_ACCESS "RO" 373 // ============================================================================= 374 // Register : RVCSR_MHPMEVENT4 375 // Description : Extended performance event selector, hardwired to 0. 376 #define RVCSR_MHPMEVENT4_OFFSET _u(0x00000324) 377 #define RVCSR_MHPMEVENT4_BITS _u(0xffffffff) 378 #define RVCSR_MHPMEVENT4_RESET _u(0x00000000) 379 #define RVCSR_MHPMEVENT4_MSB _u(31) 380 #define RVCSR_MHPMEVENT4_LSB _u(0) 381 #define RVCSR_MHPMEVENT4_ACCESS "RO" 382 // ============================================================================= 383 // Register : RVCSR_MHPMEVENT5 384 // Description : Extended performance event selector, hardwired to 0. 385 #define RVCSR_MHPMEVENT5_OFFSET _u(0x00000325) 386 #define RVCSR_MHPMEVENT5_BITS _u(0xffffffff) 387 #define RVCSR_MHPMEVENT5_RESET _u(0x00000000) 388 #define RVCSR_MHPMEVENT5_MSB _u(31) 389 #define RVCSR_MHPMEVENT5_LSB _u(0) 390 #define RVCSR_MHPMEVENT5_ACCESS "RO" 391 // ============================================================================= 392 // Register : RVCSR_MHPMEVENT6 393 // Description : Extended performance event selector, hardwired to 0. 394 #define RVCSR_MHPMEVENT6_OFFSET _u(0x00000326) 395 #define RVCSR_MHPMEVENT6_BITS _u(0xffffffff) 396 #define RVCSR_MHPMEVENT6_RESET _u(0x00000000) 397 #define RVCSR_MHPMEVENT6_MSB _u(31) 398 #define RVCSR_MHPMEVENT6_LSB _u(0) 399 #define RVCSR_MHPMEVENT6_ACCESS "RO" 400 // ============================================================================= 401 // Register : RVCSR_MHPMEVENT7 402 // Description : Extended performance event selector, hardwired to 0. 403 #define RVCSR_MHPMEVENT7_OFFSET _u(0x00000327) 404 #define RVCSR_MHPMEVENT7_BITS _u(0xffffffff) 405 #define RVCSR_MHPMEVENT7_RESET _u(0x00000000) 406 #define RVCSR_MHPMEVENT7_MSB _u(31) 407 #define RVCSR_MHPMEVENT7_LSB _u(0) 408 #define RVCSR_MHPMEVENT7_ACCESS "RO" 409 // ============================================================================= 410 // Register : RVCSR_MHPMEVENT8 411 // Description : Extended performance event selector, hardwired to 0. 412 #define RVCSR_MHPMEVENT8_OFFSET _u(0x00000328) 413 #define RVCSR_MHPMEVENT8_BITS _u(0xffffffff) 414 #define RVCSR_MHPMEVENT8_RESET _u(0x00000000) 415 #define RVCSR_MHPMEVENT8_MSB _u(31) 416 #define RVCSR_MHPMEVENT8_LSB _u(0) 417 #define RVCSR_MHPMEVENT8_ACCESS "RO" 418 // ============================================================================= 419 // Register : RVCSR_MHPMEVENT9 420 // Description : Extended performance event selector, hardwired to 0. 421 #define RVCSR_MHPMEVENT9_OFFSET _u(0x00000329) 422 #define RVCSR_MHPMEVENT9_BITS _u(0xffffffff) 423 #define RVCSR_MHPMEVENT9_RESET _u(0x00000000) 424 #define RVCSR_MHPMEVENT9_MSB _u(31) 425 #define RVCSR_MHPMEVENT9_LSB _u(0) 426 #define RVCSR_MHPMEVENT9_ACCESS "RO" 427 // ============================================================================= 428 // Register : RVCSR_MHPMEVENT10 429 // Description : Extended performance event selector, hardwired to 0. 430 #define RVCSR_MHPMEVENT10_OFFSET _u(0x0000032a) 431 #define RVCSR_MHPMEVENT10_BITS _u(0xffffffff) 432 #define RVCSR_MHPMEVENT10_RESET _u(0x00000000) 433 #define RVCSR_MHPMEVENT10_MSB _u(31) 434 #define RVCSR_MHPMEVENT10_LSB _u(0) 435 #define RVCSR_MHPMEVENT10_ACCESS "RO" 436 // ============================================================================= 437 // Register : RVCSR_MHPMEVENT11 438 // Description : Extended performance event selector, hardwired to 0. 439 #define RVCSR_MHPMEVENT11_OFFSET _u(0x0000032b) 440 #define RVCSR_MHPMEVENT11_BITS _u(0xffffffff) 441 #define RVCSR_MHPMEVENT11_RESET _u(0x00000000) 442 #define RVCSR_MHPMEVENT11_MSB _u(31) 443 #define RVCSR_MHPMEVENT11_LSB _u(0) 444 #define RVCSR_MHPMEVENT11_ACCESS "RO" 445 // ============================================================================= 446 // Register : RVCSR_MHPMEVENT12 447 // Description : Extended performance event selector, hardwired to 0. 448 #define RVCSR_MHPMEVENT12_OFFSET _u(0x0000032c) 449 #define RVCSR_MHPMEVENT12_BITS _u(0xffffffff) 450 #define RVCSR_MHPMEVENT12_RESET _u(0x00000000) 451 #define RVCSR_MHPMEVENT12_MSB _u(31) 452 #define RVCSR_MHPMEVENT12_LSB _u(0) 453 #define RVCSR_MHPMEVENT12_ACCESS "RO" 454 // ============================================================================= 455 // Register : RVCSR_MHPMEVENT13 456 // Description : Extended performance event selector, hardwired to 0. 457 #define RVCSR_MHPMEVENT13_OFFSET _u(0x0000032d) 458 #define RVCSR_MHPMEVENT13_BITS _u(0xffffffff) 459 #define RVCSR_MHPMEVENT13_RESET _u(0x00000000) 460 #define RVCSR_MHPMEVENT13_MSB _u(31) 461 #define RVCSR_MHPMEVENT13_LSB _u(0) 462 #define RVCSR_MHPMEVENT13_ACCESS "RO" 463 // ============================================================================= 464 // Register : RVCSR_MHPMEVENT14 465 // Description : Extended performance event selector, hardwired to 0. 466 #define RVCSR_MHPMEVENT14_OFFSET _u(0x0000032e) 467 #define RVCSR_MHPMEVENT14_BITS _u(0xffffffff) 468 #define RVCSR_MHPMEVENT14_RESET _u(0x00000000) 469 #define RVCSR_MHPMEVENT14_MSB _u(31) 470 #define RVCSR_MHPMEVENT14_LSB _u(0) 471 #define RVCSR_MHPMEVENT14_ACCESS "RO" 472 // ============================================================================= 473 // Register : RVCSR_MHPMEVENT15 474 // Description : Extended performance event selector, hardwired to 0. 475 #define RVCSR_MHPMEVENT15_OFFSET _u(0x0000032f) 476 #define RVCSR_MHPMEVENT15_BITS _u(0xffffffff) 477 #define RVCSR_MHPMEVENT15_RESET _u(0x00000000) 478 #define RVCSR_MHPMEVENT15_MSB _u(31) 479 #define RVCSR_MHPMEVENT15_LSB _u(0) 480 #define RVCSR_MHPMEVENT15_ACCESS "RO" 481 // ============================================================================= 482 // Register : RVCSR_MHPMEVENT16 483 // Description : Extended performance event selector, hardwired to 0. 484 #define RVCSR_MHPMEVENT16_OFFSET _u(0x00000330) 485 #define RVCSR_MHPMEVENT16_BITS _u(0xffffffff) 486 #define RVCSR_MHPMEVENT16_RESET _u(0x00000000) 487 #define RVCSR_MHPMEVENT16_MSB _u(31) 488 #define RVCSR_MHPMEVENT16_LSB _u(0) 489 #define RVCSR_MHPMEVENT16_ACCESS "RO" 490 // ============================================================================= 491 // Register : RVCSR_MHPMEVENT17 492 // Description : Extended performance event selector, hardwired to 0. 493 #define RVCSR_MHPMEVENT17_OFFSET _u(0x00000331) 494 #define RVCSR_MHPMEVENT17_BITS _u(0xffffffff) 495 #define RVCSR_MHPMEVENT17_RESET _u(0x00000000) 496 #define RVCSR_MHPMEVENT17_MSB _u(31) 497 #define RVCSR_MHPMEVENT17_LSB _u(0) 498 #define RVCSR_MHPMEVENT17_ACCESS "RO" 499 // ============================================================================= 500 // Register : RVCSR_MHPMEVENT18 501 // Description : Extended performance event selector, hardwired to 0. 502 #define RVCSR_MHPMEVENT18_OFFSET _u(0x00000332) 503 #define RVCSR_MHPMEVENT18_BITS _u(0xffffffff) 504 #define RVCSR_MHPMEVENT18_RESET _u(0x00000000) 505 #define RVCSR_MHPMEVENT18_MSB _u(31) 506 #define RVCSR_MHPMEVENT18_LSB _u(0) 507 #define RVCSR_MHPMEVENT18_ACCESS "RO" 508 // ============================================================================= 509 // Register : RVCSR_MHPMEVENT19 510 // Description : Extended performance event selector, hardwired to 0. 511 #define RVCSR_MHPMEVENT19_OFFSET _u(0x00000333) 512 #define RVCSR_MHPMEVENT19_BITS _u(0xffffffff) 513 #define RVCSR_MHPMEVENT19_RESET _u(0x00000000) 514 #define RVCSR_MHPMEVENT19_MSB _u(31) 515 #define RVCSR_MHPMEVENT19_LSB _u(0) 516 #define RVCSR_MHPMEVENT19_ACCESS "RO" 517 // ============================================================================= 518 // Register : RVCSR_MHPMEVENT20 519 // Description : Extended performance event selector, hardwired to 0. 520 #define RVCSR_MHPMEVENT20_OFFSET _u(0x00000334) 521 #define RVCSR_MHPMEVENT20_BITS _u(0xffffffff) 522 #define RVCSR_MHPMEVENT20_RESET _u(0x00000000) 523 #define RVCSR_MHPMEVENT20_MSB _u(31) 524 #define RVCSR_MHPMEVENT20_LSB _u(0) 525 #define RVCSR_MHPMEVENT20_ACCESS "RO" 526 // ============================================================================= 527 // Register : RVCSR_MHPMEVENT21 528 // Description : Extended performance event selector, hardwired to 0. 529 #define RVCSR_MHPMEVENT21_OFFSET _u(0x00000335) 530 #define RVCSR_MHPMEVENT21_BITS _u(0xffffffff) 531 #define RVCSR_MHPMEVENT21_RESET _u(0x00000000) 532 #define RVCSR_MHPMEVENT21_MSB _u(31) 533 #define RVCSR_MHPMEVENT21_LSB _u(0) 534 #define RVCSR_MHPMEVENT21_ACCESS "RO" 535 // ============================================================================= 536 // Register : RVCSR_MHPMEVENT22 537 // Description : Extended performance event selector, hardwired to 0. 538 #define RVCSR_MHPMEVENT22_OFFSET _u(0x00000336) 539 #define RVCSR_MHPMEVENT22_BITS _u(0xffffffff) 540 #define RVCSR_MHPMEVENT22_RESET _u(0x00000000) 541 #define RVCSR_MHPMEVENT22_MSB _u(31) 542 #define RVCSR_MHPMEVENT22_LSB _u(0) 543 #define RVCSR_MHPMEVENT22_ACCESS "RO" 544 // ============================================================================= 545 // Register : RVCSR_MHPMEVENT23 546 // Description : Extended performance event selector, hardwired to 0. 547 #define RVCSR_MHPMEVENT23_OFFSET _u(0x00000337) 548 #define RVCSR_MHPMEVENT23_BITS _u(0xffffffff) 549 #define RVCSR_MHPMEVENT23_RESET _u(0x00000000) 550 #define RVCSR_MHPMEVENT23_MSB _u(31) 551 #define RVCSR_MHPMEVENT23_LSB _u(0) 552 #define RVCSR_MHPMEVENT23_ACCESS "RO" 553 // ============================================================================= 554 // Register : RVCSR_MHPMEVENT24 555 // Description : Extended performance event selector, hardwired to 0. 556 #define RVCSR_MHPMEVENT24_OFFSET _u(0x00000338) 557 #define RVCSR_MHPMEVENT24_BITS _u(0xffffffff) 558 #define RVCSR_MHPMEVENT24_RESET _u(0x00000000) 559 #define RVCSR_MHPMEVENT24_MSB _u(31) 560 #define RVCSR_MHPMEVENT24_LSB _u(0) 561 #define RVCSR_MHPMEVENT24_ACCESS "RO" 562 // ============================================================================= 563 // Register : RVCSR_MHPMEVENT25 564 // Description : Extended performance event selector, hardwired to 0. 565 #define RVCSR_MHPMEVENT25_OFFSET _u(0x00000339) 566 #define RVCSR_MHPMEVENT25_BITS _u(0xffffffff) 567 #define RVCSR_MHPMEVENT25_RESET _u(0x00000000) 568 #define RVCSR_MHPMEVENT25_MSB _u(31) 569 #define RVCSR_MHPMEVENT25_LSB _u(0) 570 #define RVCSR_MHPMEVENT25_ACCESS "RO" 571 // ============================================================================= 572 // Register : RVCSR_MHPMEVENT26 573 // Description : Extended performance event selector, hardwired to 0. 574 #define RVCSR_MHPMEVENT26_OFFSET _u(0x0000033a) 575 #define RVCSR_MHPMEVENT26_BITS _u(0xffffffff) 576 #define RVCSR_MHPMEVENT26_RESET _u(0x00000000) 577 #define RVCSR_MHPMEVENT26_MSB _u(31) 578 #define RVCSR_MHPMEVENT26_LSB _u(0) 579 #define RVCSR_MHPMEVENT26_ACCESS "RO" 580 // ============================================================================= 581 // Register : RVCSR_MHPMEVENT27 582 // Description : Extended performance event selector, hardwired to 0. 583 #define RVCSR_MHPMEVENT27_OFFSET _u(0x0000033b) 584 #define RVCSR_MHPMEVENT27_BITS _u(0xffffffff) 585 #define RVCSR_MHPMEVENT27_RESET _u(0x00000000) 586 #define RVCSR_MHPMEVENT27_MSB _u(31) 587 #define RVCSR_MHPMEVENT27_LSB _u(0) 588 #define RVCSR_MHPMEVENT27_ACCESS "RO" 589 // ============================================================================= 590 // Register : RVCSR_MHPMEVENT28 591 // Description : Extended performance event selector, hardwired to 0. 592 #define RVCSR_MHPMEVENT28_OFFSET _u(0x0000033c) 593 #define RVCSR_MHPMEVENT28_BITS _u(0xffffffff) 594 #define RVCSR_MHPMEVENT28_RESET _u(0x00000000) 595 #define RVCSR_MHPMEVENT28_MSB _u(31) 596 #define RVCSR_MHPMEVENT28_LSB _u(0) 597 #define RVCSR_MHPMEVENT28_ACCESS "RO" 598 // ============================================================================= 599 // Register : RVCSR_MHPMEVENT29 600 // Description : Extended performance event selector, hardwired to 0. 601 #define RVCSR_MHPMEVENT29_OFFSET _u(0x0000033d) 602 #define RVCSR_MHPMEVENT29_BITS _u(0xffffffff) 603 #define RVCSR_MHPMEVENT29_RESET _u(0x00000000) 604 #define RVCSR_MHPMEVENT29_MSB _u(31) 605 #define RVCSR_MHPMEVENT29_LSB _u(0) 606 #define RVCSR_MHPMEVENT29_ACCESS "RO" 607 // ============================================================================= 608 // Register : RVCSR_MHPMEVENT30 609 // Description : Extended performance event selector, hardwired to 0. 610 #define RVCSR_MHPMEVENT30_OFFSET _u(0x0000033e) 611 #define RVCSR_MHPMEVENT30_BITS _u(0xffffffff) 612 #define RVCSR_MHPMEVENT30_RESET _u(0x00000000) 613 #define RVCSR_MHPMEVENT30_MSB _u(31) 614 #define RVCSR_MHPMEVENT30_LSB _u(0) 615 #define RVCSR_MHPMEVENT30_ACCESS "RO" 616 // ============================================================================= 617 // Register : RVCSR_MHPMEVENT31 618 // Description : Extended performance event selector, hardwired to 0. 619 #define RVCSR_MHPMEVENT31_OFFSET _u(0x0000033f) 620 #define RVCSR_MHPMEVENT31_BITS _u(0xffffffff) 621 #define RVCSR_MHPMEVENT31_RESET _u(0x00000000) 622 #define RVCSR_MHPMEVENT31_MSB _u(31) 623 #define RVCSR_MHPMEVENT31_LSB _u(0) 624 #define RVCSR_MHPMEVENT31_ACCESS "RO" 625 // ============================================================================= 626 // Register : RVCSR_MSCRATCH 627 // Description : Scratch register for machine trap handlers. 628 // 629 // 32-bit read/write register with no specific hardware function. 630 // Software may use this to do a fast save/restore of a core 631 // register in a trap handler. 632 #define RVCSR_MSCRATCH_OFFSET _u(0x00000340) 633 #define RVCSR_MSCRATCH_BITS _u(0xffffffff) 634 #define RVCSR_MSCRATCH_RESET _u(0x00000000) 635 #define RVCSR_MSCRATCH_MSB _u(31) 636 #define RVCSR_MSCRATCH_LSB _u(0) 637 #define RVCSR_MSCRATCH_ACCESS "RW" 638 // ============================================================================= 639 // Register : RVCSR_MEPC 640 // Description : Machine exception program counter. 641 // 642 // When entering a trap, the current value of the program counter 643 // is recorded here. When executing an `mret`, the processor jumps 644 // to `mepc`. Can also be read and written by software. 645 #define RVCSR_MEPC_OFFSET _u(0x00000341) 646 #define RVCSR_MEPC_BITS _u(0xfffffffc) 647 #define RVCSR_MEPC_RESET _u(0x00000000) 648 #define RVCSR_MEPC_MSB _u(31) 649 #define RVCSR_MEPC_LSB _u(2) 650 #define RVCSR_MEPC_ACCESS "RW" 651 // ============================================================================= 652 // Register : RVCSR_MCAUSE 653 // Description : Machine trap cause. Set when entering a trap to indicate the 654 // reason for the trap. Readable and writable by software. 655 #define RVCSR_MCAUSE_OFFSET _u(0x00000342) 656 #define RVCSR_MCAUSE_BITS _u(0x8000000f) 657 #define RVCSR_MCAUSE_RESET _u(0x00000000) 658 // ----------------------------------------------------------------------------- 659 // Field : RVCSR_MCAUSE_INTERRUPT 660 // Description : If 1, the trap was caused by an interrupt. If 0, it was caused 661 // by an exception. 662 #define RVCSR_MCAUSE_INTERRUPT_RESET _u(0x0) 663 #define RVCSR_MCAUSE_INTERRUPT_BITS _u(0x80000000) 664 #define RVCSR_MCAUSE_INTERRUPT_MSB _u(31) 665 #define RVCSR_MCAUSE_INTERRUPT_LSB _u(31) 666 #define RVCSR_MCAUSE_INTERRUPT_ACCESS "RW" 667 // ----------------------------------------------------------------------------- 668 // Field : RVCSR_MCAUSE_CODE 669 // Description : If `interrupt` is set, `code` indicates the index of the bit in 670 // mip that caused the trap (3=soft IRQ, 7=timer IRQ, 11=external 671 // IRQ). Otherwise, `code` is set according to the cause of the 672 // exception. 673 // 0x0 -> Instruction fetch was misaligned. Will never fire on RP2350, since the C extension is enabled. 674 // 0x1 -> Instruction access fault. Instruction fetch failed a PMP check, or encountered a downstream bus fault, and then passed the point of no speculation. 675 // 0x2 -> Illegal instruction was executed (including illegal CSR accesses) 676 // 0x3 -> Breakpoint. An ebreak instruction was executed when the relevant dcsr.ebreak bit was clear. 677 // 0x4 -> Load address misaligned. Hazard3 requires natural alignment of all accesses. 678 // 0x5 -> Load access fault. A load failed a PMP check, or encountered a downstream bus error. 679 // 0x6 -> Store/AMO address misaligned. Hazard3 requires natural alignment of all accesses. 680 // 0x7 -> Store/AMO access fault. A store/AMO failed a PMP check, or encountered a downstream bus error. Also set if an AMO is attempted on a region that does not support atomics (on RP2350, anything but SRAM). 681 // 0x8 -> Environment call from U-mode. 682 // 0xb -> Environment call from M-mode. 683 #define RVCSR_MCAUSE_CODE_RESET _u(0x0) 684 #define RVCSR_MCAUSE_CODE_BITS _u(0x0000000f) 685 #define RVCSR_MCAUSE_CODE_MSB _u(3) 686 #define RVCSR_MCAUSE_CODE_LSB _u(0) 687 #define RVCSR_MCAUSE_CODE_ACCESS "RW" 688 #define RVCSR_MCAUSE_CODE_VALUE_INSTR_ALIGN _u(0x0) 689 #define RVCSR_MCAUSE_CODE_VALUE_INSTR_FAULT _u(0x1) 690 #define RVCSR_MCAUSE_CODE_VALUE_ILLEGAL_INSTR _u(0x2) 691 #define RVCSR_MCAUSE_CODE_VALUE_BREAKPOINT _u(0x3) 692 #define RVCSR_MCAUSE_CODE_VALUE_LOAD_ALIGN _u(0x4) 693 #define RVCSR_MCAUSE_CODE_VALUE_LOAD_FAULT _u(0x5) 694 #define RVCSR_MCAUSE_CODE_VALUE_STORE_ALIGN _u(0x6) 695 #define RVCSR_MCAUSE_CODE_VALUE_STORE_FAULT _u(0x7) 696 #define RVCSR_MCAUSE_CODE_VALUE_U_ECALL _u(0x8) 697 #define RVCSR_MCAUSE_CODE_VALUE_M_ECALL _u(0xb) 698 // ============================================================================= 699 // Register : RVCSR_MTVAL 700 // Description : Machine bad address or instruction. Hardwired to zero. 701 #define RVCSR_MTVAL_OFFSET _u(0x00000343) 702 #define RVCSR_MTVAL_BITS _u(0xffffffff) 703 #define RVCSR_MTVAL_RESET _u(0x00000000) 704 #define RVCSR_MTVAL_MSB _u(31) 705 #define RVCSR_MTVAL_LSB _u(0) 706 #define RVCSR_MTVAL_ACCESS "RO" 707 // ============================================================================= 708 // Register : RVCSR_MIP 709 // Description : Machine interrupt pending 710 #define RVCSR_MIP_OFFSET _u(0x00000344) 711 #define RVCSR_MIP_BITS _u(0x00000888) 712 #define RVCSR_MIP_RESET _u(0x00000000) 713 // ----------------------------------------------------------------------------- 714 // Field : RVCSR_MIP_MEIP 715 // Description : External interrupt pending. The processor transfers to the 716 // external interrupt vector when `mie.meie`, `mip.meip` and 717 // `mstatus.mie` are all 1. 718 // 719 // Hazard3 has internal registers to individually filter which 720 // external IRQs appear in `meip`. When `meip` is 1, this 721 // indicates there is at least one external interrupt which is 722 // asserted (hence pending in `mieipa`), enabled in `meiea`, and 723 // of priority greater than or equal to the current preemption 724 // level in `meicontext.preempt`. 725 #define RVCSR_MIP_MEIP_RESET _u(0x0) 726 #define RVCSR_MIP_MEIP_BITS _u(0x00000800) 727 #define RVCSR_MIP_MEIP_MSB _u(11) 728 #define RVCSR_MIP_MEIP_LSB _u(11) 729 #define RVCSR_MIP_MEIP_ACCESS "RO" 730 // ----------------------------------------------------------------------------- 731 // Field : RVCSR_MIP_MTIP 732 // Description : Timer interrupt pending. The processor transfers to the timer 733 // interrupt vector when `mie.mtie`, `mip.mtip` and `mstatus.mie` 734 // are all 1, unless a software or external interrupt request is 735 // also valid at this time. 736 #define RVCSR_MIP_MTIP_RESET _u(0x0) 737 #define RVCSR_MIP_MTIP_BITS _u(0x00000080) 738 #define RVCSR_MIP_MTIP_MSB _u(7) 739 #define RVCSR_MIP_MTIP_LSB _u(7) 740 #define RVCSR_MIP_MTIP_ACCESS "RW" 741 // ----------------------------------------------------------------------------- 742 // Field : RVCSR_MIP_MSIP 743 // Description : Software interrupt pending. The processor transfers to the 744 // software interrupt vector `mie.msie`, `mip.msip` and 745 // `mstatus.mie` are all 1, unless an external interrupt request 746 // is also valid at this time. 747 #define RVCSR_MIP_MSIP_RESET _u(0x0) 748 #define RVCSR_MIP_MSIP_BITS _u(0x00000008) 749 #define RVCSR_MIP_MSIP_MSB _u(3) 750 #define RVCSR_MIP_MSIP_LSB _u(3) 751 #define RVCSR_MIP_MSIP_ACCESS "RW" 752 // ============================================================================= 753 // Register : RVCSR_PMPCFG0 754 // Description : Physical memory protection configuration for regions 0 through 755 // 3 756 #define RVCSR_PMPCFG0_OFFSET _u(0x000003a0) 757 #define RVCSR_PMPCFG0_BITS _u(0x9f9f9f9f) 758 #define RVCSR_PMPCFG0_RESET _u(0x00000000) 759 // ----------------------------------------------------------------------------- 760 // Field : RVCSR_PMPCFG0_R3_L 761 // Description : Lock region 3, and apply it to M-mode as well as U-mode. 762 #define RVCSR_PMPCFG0_R3_L_RESET _u(0x0) 763 #define RVCSR_PMPCFG0_R3_L_BITS _u(0x80000000) 764 #define RVCSR_PMPCFG0_R3_L_MSB _u(31) 765 #define RVCSR_PMPCFG0_R3_L_LSB _u(31) 766 #define RVCSR_PMPCFG0_R3_L_ACCESS "RW" 767 // ----------------------------------------------------------------------------- 768 // Field : RVCSR_PMPCFG0_R3_A 769 // Description : Address matching type for region 3. Writing an unsupported 770 // value (TOR) will set the region to OFF. 771 // 0x0 -> Disable region 772 // 0x2 -> Naturally aligned 4-byte 773 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 774 #define RVCSR_PMPCFG0_R3_A_RESET _u(0x0) 775 #define RVCSR_PMPCFG0_R3_A_BITS _u(0x18000000) 776 #define RVCSR_PMPCFG0_R3_A_MSB _u(28) 777 #define RVCSR_PMPCFG0_R3_A_LSB _u(27) 778 #define RVCSR_PMPCFG0_R3_A_ACCESS "RW" 779 #define RVCSR_PMPCFG0_R3_A_VALUE_OFF _u(0x0) 780 #define RVCSR_PMPCFG0_R3_A_VALUE_NA4 _u(0x2) 781 #define RVCSR_PMPCFG0_R3_A_VALUE_NAPOT _u(0x3) 782 // ----------------------------------------------------------------------------- 783 // Field : RVCSR_PMPCFG0_R3_R 784 // Description : Read permission for region 3. Note R and X are transposed from 785 // the standard bit order due to erratum RP2350-E6. 786 #define RVCSR_PMPCFG0_R3_R_RESET _u(0x0) 787 #define RVCSR_PMPCFG0_R3_R_BITS _u(0x04000000) 788 #define RVCSR_PMPCFG0_R3_R_MSB _u(26) 789 #define RVCSR_PMPCFG0_R3_R_LSB _u(26) 790 #define RVCSR_PMPCFG0_R3_R_ACCESS "RW" 791 // ----------------------------------------------------------------------------- 792 // Field : RVCSR_PMPCFG0_R3_W 793 // Description : Write permission for region 3 794 #define RVCSR_PMPCFG0_R3_W_RESET _u(0x0) 795 #define RVCSR_PMPCFG0_R3_W_BITS _u(0x02000000) 796 #define RVCSR_PMPCFG0_R3_W_MSB _u(25) 797 #define RVCSR_PMPCFG0_R3_W_LSB _u(25) 798 #define RVCSR_PMPCFG0_R3_W_ACCESS "RW" 799 // ----------------------------------------------------------------------------- 800 // Field : RVCSR_PMPCFG0_R3_X 801 // Description : Execute permission for region 3. Note R and X are transposed 802 // from the standard bit order due to erratum RP2350-E6. 803 #define RVCSR_PMPCFG0_R3_X_RESET _u(0x0) 804 #define RVCSR_PMPCFG0_R3_X_BITS _u(0x01000000) 805 #define RVCSR_PMPCFG0_R3_X_MSB _u(24) 806 #define RVCSR_PMPCFG0_R3_X_LSB _u(24) 807 #define RVCSR_PMPCFG0_R3_X_ACCESS "RW" 808 // ----------------------------------------------------------------------------- 809 // Field : RVCSR_PMPCFG0_R2_L 810 // Description : Lock region 2, and apply it to M-mode as well as U-mode. 811 #define RVCSR_PMPCFG0_R2_L_RESET _u(0x0) 812 #define RVCSR_PMPCFG0_R2_L_BITS _u(0x00800000) 813 #define RVCSR_PMPCFG0_R2_L_MSB _u(23) 814 #define RVCSR_PMPCFG0_R2_L_LSB _u(23) 815 #define RVCSR_PMPCFG0_R2_L_ACCESS "RW" 816 // ----------------------------------------------------------------------------- 817 // Field : RVCSR_PMPCFG0_R2_A 818 // Description : Address matching type for region 2. Writing an unsupported 819 // value (TOR) will set the region to OFF. 820 // 0x0 -> Disable region 821 // 0x2 -> Naturally aligned 4-byte 822 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 823 #define RVCSR_PMPCFG0_R2_A_RESET _u(0x0) 824 #define RVCSR_PMPCFG0_R2_A_BITS _u(0x00180000) 825 #define RVCSR_PMPCFG0_R2_A_MSB _u(20) 826 #define RVCSR_PMPCFG0_R2_A_LSB _u(19) 827 #define RVCSR_PMPCFG0_R2_A_ACCESS "RW" 828 #define RVCSR_PMPCFG0_R2_A_VALUE_OFF _u(0x0) 829 #define RVCSR_PMPCFG0_R2_A_VALUE_NA4 _u(0x2) 830 #define RVCSR_PMPCFG0_R2_A_VALUE_NAPOT _u(0x3) 831 // ----------------------------------------------------------------------------- 832 // Field : RVCSR_PMPCFG0_R2_R 833 // Description : Read permission for region 2. Note R and X are transposed from 834 // the standard bit order due to erratum RP2350-E6. 835 #define RVCSR_PMPCFG0_R2_R_RESET _u(0x0) 836 #define RVCSR_PMPCFG0_R2_R_BITS _u(0x00040000) 837 #define RVCSR_PMPCFG0_R2_R_MSB _u(18) 838 #define RVCSR_PMPCFG0_R2_R_LSB _u(18) 839 #define RVCSR_PMPCFG0_R2_R_ACCESS "RW" 840 // ----------------------------------------------------------------------------- 841 // Field : RVCSR_PMPCFG0_R2_W 842 // Description : Write permission for region 2 843 #define RVCSR_PMPCFG0_R2_W_RESET _u(0x0) 844 #define RVCSR_PMPCFG0_R2_W_BITS _u(0x00020000) 845 #define RVCSR_PMPCFG0_R2_W_MSB _u(17) 846 #define RVCSR_PMPCFG0_R2_W_LSB _u(17) 847 #define RVCSR_PMPCFG0_R2_W_ACCESS "RW" 848 // ----------------------------------------------------------------------------- 849 // Field : RVCSR_PMPCFG0_R2_X 850 // Description : Execute permission for region 2. Note R and X are transposed 851 // from the standard bit order due to erratum RP2350-E6. 852 #define RVCSR_PMPCFG0_R2_X_RESET _u(0x0) 853 #define RVCSR_PMPCFG0_R2_X_BITS _u(0x00010000) 854 #define RVCSR_PMPCFG0_R2_X_MSB _u(16) 855 #define RVCSR_PMPCFG0_R2_X_LSB _u(16) 856 #define RVCSR_PMPCFG0_R2_X_ACCESS "RW" 857 // ----------------------------------------------------------------------------- 858 // Field : RVCSR_PMPCFG0_R1_L 859 // Description : Lock region 1, and apply it to M-mode as well as U-mode. 860 #define RVCSR_PMPCFG0_R1_L_RESET _u(0x0) 861 #define RVCSR_PMPCFG0_R1_L_BITS _u(0x00008000) 862 #define RVCSR_PMPCFG0_R1_L_MSB _u(15) 863 #define RVCSR_PMPCFG0_R1_L_LSB _u(15) 864 #define RVCSR_PMPCFG0_R1_L_ACCESS "RW" 865 // ----------------------------------------------------------------------------- 866 // Field : RVCSR_PMPCFG0_R1_A 867 // Description : Address matching type for region 1. Writing an unsupported 868 // value (TOR) will set the region to OFF. 869 // 0x0 -> Disable region 870 // 0x2 -> Naturally aligned 4-byte 871 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 872 #define RVCSR_PMPCFG0_R1_A_RESET _u(0x0) 873 #define RVCSR_PMPCFG0_R1_A_BITS _u(0x00001800) 874 #define RVCSR_PMPCFG0_R1_A_MSB _u(12) 875 #define RVCSR_PMPCFG0_R1_A_LSB _u(11) 876 #define RVCSR_PMPCFG0_R1_A_ACCESS "RW" 877 #define RVCSR_PMPCFG0_R1_A_VALUE_OFF _u(0x0) 878 #define RVCSR_PMPCFG0_R1_A_VALUE_NA4 _u(0x2) 879 #define RVCSR_PMPCFG0_R1_A_VALUE_NAPOT _u(0x3) 880 // ----------------------------------------------------------------------------- 881 // Field : RVCSR_PMPCFG0_R1_R 882 // Description : Read permission for region 1. Note R and X are transposed from 883 // the standard bit order due to erratum RP2350-E6. 884 #define RVCSR_PMPCFG0_R1_R_RESET _u(0x0) 885 #define RVCSR_PMPCFG0_R1_R_BITS _u(0x00000400) 886 #define RVCSR_PMPCFG0_R1_R_MSB _u(10) 887 #define RVCSR_PMPCFG0_R1_R_LSB _u(10) 888 #define RVCSR_PMPCFG0_R1_R_ACCESS "RW" 889 // ----------------------------------------------------------------------------- 890 // Field : RVCSR_PMPCFG0_R1_W 891 // Description : Write permission for region 1 892 #define RVCSR_PMPCFG0_R1_W_RESET _u(0x0) 893 #define RVCSR_PMPCFG0_R1_W_BITS _u(0x00000200) 894 #define RVCSR_PMPCFG0_R1_W_MSB _u(9) 895 #define RVCSR_PMPCFG0_R1_W_LSB _u(9) 896 #define RVCSR_PMPCFG0_R1_W_ACCESS "RW" 897 // ----------------------------------------------------------------------------- 898 // Field : RVCSR_PMPCFG0_R1_X 899 // Description : Execute permission for region 1. Note R and X are transposed 900 // from the standard bit order due to erratum RP2350-E6. 901 #define RVCSR_PMPCFG0_R1_X_RESET _u(0x0) 902 #define RVCSR_PMPCFG0_R1_X_BITS _u(0x00000100) 903 #define RVCSR_PMPCFG0_R1_X_MSB _u(8) 904 #define RVCSR_PMPCFG0_R1_X_LSB _u(8) 905 #define RVCSR_PMPCFG0_R1_X_ACCESS "RW" 906 // ----------------------------------------------------------------------------- 907 // Field : RVCSR_PMPCFG0_R0_L 908 // Description : Lock region 0, and apply it to M-mode as well as U-mode. 909 #define RVCSR_PMPCFG0_R0_L_RESET _u(0x0) 910 #define RVCSR_PMPCFG0_R0_L_BITS _u(0x00000080) 911 #define RVCSR_PMPCFG0_R0_L_MSB _u(7) 912 #define RVCSR_PMPCFG0_R0_L_LSB _u(7) 913 #define RVCSR_PMPCFG0_R0_L_ACCESS "RW" 914 // ----------------------------------------------------------------------------- 915 // Field : RVCSR_PMPCFG0_R0_A 916 // Description : Address matching type for region 0. Writing an unsupported 917 // value (TOR) will set the region to OFF. 918 // 0x0 -> Disable region 919 // 0x2 -> Naturally aligned 4-byte 920 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 921 #define RVCSR_PMPCFG0_R0_A_RESET _u(0x0) 922 #define RVCSR_PMPCFG0_R0_A_BITS _u(0x00000018) 923 #define RVCSR_PMPCFG0_R0_A_MSB _u(4) 924 #define RVCSR_PMPCFG0_R0_A_LSB _u(3) 925 #define RVCSR_PMPCFG0_R0_A_ACCESS "RW" 926 #define RVCSR_PMPCFG0_R0_A_VALUE_OFF _u(0x0) 927 #define RVCSR_PMPCFG0_R0_A_VALUE_NA4 _u(0x2) 928 #define RVCSR_PMPCFG0_R0_A_VALUE_NAPOT _u(0x3) 929 // ----------------------------------------------------------------------------- 930 // Field : RVCSR_PMPCFG0_R0_R 931 // Description : Read permission for region 0. Note R and X are transposed from 932 // the standard bit order due to erratum RP2350-E6. 933 #define RVCSR_PMPCFG0_R0_R_RESET _u(0x0) 934 #define RVCSR_PMPCFG0_R0_R_BITS _u(0x00000004) 935 #define RVCSR_PMPCFG0_R0_R_MSB _u(2) 936 #define RVCSR_PMPCFG0_R0_R_LSB _u(2) 937 #define RVCSR_PMPCFG0_R0_R_ACCESS "RW" 938 // ----------------------------------------------------------------------------- 939 // Field : RVCSR_PMPCFG0_R0_W 940 // Description : Write permission for region 0 941 #define RVCSR_PMPCFG0_R0_W_RESET _u(0x0) 942 #define RVCSR_PMPCFG0_R0_W_BITS _u(0x00000002) 943 #define RVCSR_PMPCFG0_R0_W_MSB _u(1) 944 #define RVCSR_PMPCFG0_R0_W_LSB _u(1) 945 #define RVCSR_PMPCFG0_R0_W_ACCESS "RW" 946 // ----------------------------------------------------------------------------- 947 // Field : RVCSR_PMPCFG0_R0_X 948 // Description : Execute permission for region 0. Note R and X are transposed 949 // from the standard bit order due to erratum RP2350-E6. 950 #define RVCSR_PMPCFG0_R0_X_RESET _u(0x0) 951 #define RVCSR_PMPCFG0_R0_X_BITS _u(0x00000001) 952 #define RVCSR_PMPCFG0_R0_X_MSB _u(0) 953 #define RVCSR_PMPCFG0_R0_X_LSB _u(0) 954 #define RVCSR_PMPCFG0_R0_X_ACCESS "RW" 955 // ============================================================================= 956 // Register : RVCSR_PMPCFG1 957 // Description : Physical memory protection configuration for regions 4 through 958 // 7 959 #define RVCSR_PMPCFG1_OFFSET _u(0x000003a1) 960 #define RVCSR_PMPCFG1_BITS _u(0x9f9f9f9f) 961 #define RVCSR_PMPCFG1_RESET _u(0x00000000) 962 // ----------------------------------------------------------------------------- 963 // Field : RVCSR_PMPCFG1_R7_L 964 // Description : Lock region 7, and apply it to M-mode as well as U-mode. 965 #define RVCSR_PMPCFG1_R7_L_RESET _u(0x0) 966 #define RVCSR_PMPCFG1_R7_L_BITS _u(0x80000000) 967 #define RVCSR_PMPCFG1_R7_L_MSB _u(31) 968 #define RVCSR_PMPCFG1_R7_L_LSB _u(31) 969 #define RVCSR_PMPCFG1_R7_L_ACCESS "RW" 970 // ----------------------------------------------------------------------------- 971 // Field : RVCSR_PMPCFG1_R7_A 972 // Description : Address matching type for region 7. Writing an unsupported 973 // value (TOR) will set the region to OFF. 974 // 0x0 -> Disable region 975 // 0x2 -> Naturally aligned 4-byte 976 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 977 #define RVCSR_PMPCFG1_R7_A_RESET _u(0x0) 978 #define RVCSR_PMPCFG1_R7_A_BITS _u(0x18000000) 979 #define RVCSR_PMPCFG1_R7_A_MSB _u(28) 980 #define RVCSR_PMPCFG1_R7_A_LSB _u(27) 981 #define RVCSR_PMPCFG1_R7_A_ACCESS "RW" 982 #define RVCSR_PMPCFG1_R7_A_VALUE_OFF _u(0x0) 983 #define RVCSR_PMPCFG1_R7_A_VALUE_NA4 _u(0x2) 984 #define RVCSR_PMPCFG1_R7_A_VALUE_NAPOT _u(0x3) 985 // ----------------------------------------------------------------------------- 986 // Field : RVCSR_PMPCFG1_R7_R 987 // Description : Read permission for region 7. Note R and X are transposed from 988 // the standard bit order due to erratum RP2350-E6. 989 #define RVCSR_PMPCFG1_R7_R_RESET _u(0x0) 990 #define RVCSR_PMPCFG1_R7_R_BITS _u(0x04000000) 991 #define RVCSR_PMPCFG1_R7_R_MSB _u(26) 992 #define RVCSR_PMPCFG1_R7_R_LSB _u(26) 993 #define RVCSR_PMPCFG1_R7_R_ACCESS "RW" 994 // ----------------------------------------------------------------------------- 995 // Field : RVCSR_PMPCFG1_R7_W 996 // Description : Write permission for region 7 997 #define RVCSR_PMPCFG1_R7_W_RESET _u(0x0) 998 #define RVCSR_PMPCFG1_R7_W_BITS _u(0x02000000) 999 #define RVCSR_PMPCFG1_R7_W_MSB _u(25) 1000 #define RVCSR_PMPCFG1_R7_W_LSB _u(25) 1001 #define RVCSR_PMPCFG1_R7_W_ACCESS "RW" 1002 // ----------------------------------------------------------------------------- 1003 // Field : RVCSR_PMPCFG1_R7_X 1004 // Description : Execute permission for region 7. Note R and X are transposed 1005 // from the standard bit order due to erratum RP2350-E6. 1006 #define RVCSR_PMPCFG1_R7_X_RESET _u(0x0) 1007 #define RVCSR_PMPCFG1_R7_X_BITS _u(0x01000000) 1008 #define RVCSR_PMPCFG1_R7_X_MSB _u(24) 1009 #define RVCSR_PMPCFG1_R7_X_LSB _u(24) 1010 #define RVCSR_PMPCFG1_R7_X_ACCESS "RW" 1011 // ----------------------------------------------------------------------------- 1012 // Field : RVCSR_PMPCFG1_R6_L 1013 // Description : Lock region 6, and apply it to M-mode as well as U-mode. 1014 #define RVCSR_PMPCFG1_R6_L_RESET _u(0x0) 1015 #define RVCSR_PMPCFG1_R6_L_BITS _u(0x00800000) 1016 #define RVCSR_PMPCFG1_R6_L_MSB _u(23) 1017 #define RVCSR_PMPCFG1_R6_L_LSB _u(23) 1018 #define RVCSR_PMPCFG1_R6_L_ACCESS "RW" 1019 // ----------------------------------------------------------------------------- 1020 // Field : RVCSR_PMPCFG1_R6_A 1021 // Description : Address matching type for region 6. Writing an unsupported 1022 // value (TOR) will set the region to OFF. 1023 // 0x0 -> Disable region 1024 // 0x2 -> Naturally aligned 4-byte 1025 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1026 #define RVCSR_PMPCFG1_R6_A_RESET _u(0x0) 1027 #define RVCSR_PMPCFG1_R6_A_BITS _u(0x00180000) 1028 #define RVCSR_PMPCFG1_R6_A_MSB _u(20) 1029 #define RVCSR_PMPCFG1_R6_A_LSB _u(19) 1030 #define RVCSR_PMPCFG1_R6_A_ACCESS "RW" 1031 #define RVCSR_PMPCFG1_R6_A_VALUE_OFF _u(0x0) 1032 #define RVCSR_PMPCFG1_R6_A_VALUE_NA4 _u(0x2) 1033 #define RVCSR_PMPCFG1_R6_A_VALUE_NAPOT _u(0x3) 1034 // ----------------------------------------------------------------------------- 1035 // Field : RVCSR_PMPCFG1_R6_R 1036 // Description : Read permission for region 6. Note R and X are transposed from 1037 // the standard bit order due to erratum RP2350-E6. 1038 #define RVCSR_PMPCFG1_R6_R_RESET _u(0x0) 1039 #define RVCSR_PMPCFG1_R6_R_BITS _u(0x00040000) 1040 #define RVCSR_PMPCFG1_R6_R_MSB _u(18) 1041 #define RVCSR_PMPCFG1_R6_R_LSB _u(18) 1042 #define RVCSR_PMPCFG1_R6_R_ACCESS "RW" 1043 // ----------------------------------------------------------------------------- 1044 // Field : RVCSR_PMPCFG1_R6_W 1045 // Description : Write permission for region 6 1046 #define RVCSR_PMPCFG1_R6_W_RESET _u(0x0) 1047 #define RVCSR_PMPCFG1_R6_W_BITS _u(0x00020000) 1048 #define RVCSR_PMPCFG1_R6_W_MSB _u(17) 1049 #define RVCSR_PMPCFG1_R6_W_LSB _u(17) 1050 #define RVCSR_PMPCFG1_R6_W_ACCESS "RW" 1051 // ----------------------------------------------------------------------------- 1052 // Field : RVCSR_PMPCFG1_R6_X 1053 // Description : Execute permission for region 6. Note R and X are transposed 1054 // from the standard bit order due to erratum RP2350-E6. 1055 #define RVCSR_PMPCFG1_R6_X_RESET _u(0x0) 1056 #define RVCSR_PMPCFG1_R6_X_BITS _u(0x00010000) 1057 #define RVCSR_PMPCFG1_R6_X_MSB _u(16) 1058 #define RVCSR_PMPCFG1_R6_X_LSB _u(16) 1059 #define RVCSR_PMPCFG1_R6_X_ACCESS "RW" 1060 // ----------------------------------------------------------------------------- 1061 // Field : RVCSR_PMPCFG1_R5_L 1062 // Description : Lock region 5, and apply it to M-mode as well as U-mode. 1063 #define RVCSR_PMPCFG1_R5_L_RESET _u(0x0) 1064 #define RVCSR_PMPCFG1_R5_L_BITS _u(0x00008000) 1065 #define RVCSR_PMPCFG1_R5_L_MSB _u(15) 1066 #define RVCSR_PMPCFG1_R5_L_LSB _u(15) 1067 #define RVCSR_PMPCFG1_R5_L_ACCESS "RW" 1068 // ----------------------------------------------------------------------------- 1069 // Field : RVCSR_PMPCFG1_R5_A 1070 // Description : Address matching type for region 5. Writing an unsupported 1071 // value (TOR) will set the region to OFF. 1072 // 0x0 -> Disable region 1073 // 0x2 -> Naturally aligned 4-byte 1074 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1075 #define RVCSR_PMPCFG1_R5_A_RESET _u(0x0) 1076 #define RVCSR_PMPCFG1_R5_A_BITS _u(0x00001800) 1077 #define RVCSR_PMPCFG1_R5_A_MSB _u(12) 1078 #define RVCSR_PMPCFG1_R5_A_LSB _u(11) 1079 #define RVCSR_PMPCFG1_R5_A_ACCESS "RW" 1080 #define RVCSR_PMPCFG1_R5_A_VALUE_OFF _u(0x0) 1081 #define RVCSR_PMPCFG1_R5_A_VALUE_NA4 _u(0x2) 1082 #define RVCSR_PMPCFG1_R5_A_VALUE_NAPOT _u(0x3) 1083 // ----------------------------------------------------------------------------- 1084 // Field : RVCSR_PMPCFG1_R5_R 1085 // Description : Read permission for region 5. Note R and X are transposed from 1086 // the standard bit order due to erratum RP2350-E6. 1087 #define RVCSR_PMPCFG1_R5_R_RESET _u(0x0) 1088 #define RVCSR_PMPCFG1_R5_R_BITS _u(0x00000400) 1089 #define RVCSR_PMPCFG1_R5_R_MSB _u(10) 1090 #define RVCSR_PMPCFG1_R5_R_LSB _u(10) 1091 #define RVCSR_PMPCFG1_R5_R_ACCESS "RW" 1092 // ----------------------------------------------------------------------------- 1093 // Field : RVCSR_PMPCFG1_R5_W 1094 // Description : Write permission for region 5 1095 #define RVCSR_PMPCFG1_R5_W_RESET _u(0x0) 1096 #define RVCSR_PMPCFG1_R5_W_BITS _u(0x00000200) 1097 #define RVCSR_PMPCFG1_R5_W_MSB _u(9) 1098 #define RVCSR_PMPCFG1_R5_W_LSB _u(9) 1099 #define RVCSR_PMPCFG1_R5_W_ACCESS "RW" 1100 // ----------------------------------------------------------------------------- 1101 // Field : RVCSR_PMPCFG1_R5_X 1102 // Description : Execute permission for region 5. Note R and X are transposed 1103 // from the standard bit order due to erratum RP2350-E6. 1104 #define RVCSR_PMPCFG1_R5_X_RESET _u(0x0) 1105 #define RVCSR_PMPCFG1_R5_X_BITS _u(0x00000100) 1106 #define RVCSR_PMPCFG1_R5_X_MSB _u(8) 1107 #define RVCSR_PMPCFG1_R5_X_LSB _u(8) 1108 #define RVCSR_PMPCFG1_R5_X_ACCESS "RW" 1109 // ----------------------------------------------------------------------------- 1110 // Field : RVCSR_PMPCFG1_R4_L 1111 // Description : Lock region 4, and apply it to M-mode as well as U-mode. 1112 #define RVCSR_PMPCFG1_R4_L_RESET _u(0x0) 1113 #define RVCSR_PMPCFG1_R4_L_BITS _u(0x00000080) 1114 #define RVCSR_PMPCFG1_R4_L_MSB _u(7) 1115 #define RVCSR_PMPCFG1_R4_L_LSB _u(7) 1116 #define RVCSR_PMPCFG1_R4_L_ACCESS "RW" 1117 // ----------------------------------------------------------------------------- 1118 // Field : RVCSR_PMPCFG1_R4_A 1119 // Description : Address matching type for region 4. Writing an unsupported 1120 // value (TOR) will set the region to OFF. 1121 // 0x0 -> Disable region 1122 // 0x2 -> Naturally aligned 4-byte 1123 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1124 #define RVCSR_PMPCFG1_R4_A_RESET _u(0x0) 1125 #define RVCSR_PMPCFG1_R4_A_BITS _u(0x00000018) 1126 #define RVCSR_PMPCFG1_R4_A_MSB _u(4) 1127 #define RVCSR_PMPCFG1_R4_A_LSB _u(3) 1128 #define RVCSR_PMPCFG1_R4_A_ACCESS "RW" 1129 #define RVCSR_PMPCFG1_R4_A_VALUE_OFF _u(0x0) 1130 #define RVCSR_PMPCFG1_R4_A_VALUE_NA4 _u(0x2) 1131 #define RVCSR_PMPCFG1_R4_A_VALUE_NAPOT _u(0x3) 1132 // ----------------------------------------------------------------------------- 1133 // Field : RVCSR_PMPCFG1_R4_R 1134 // Description : Read permission for region 4. Note R and X are transposed from 1135 // the standard bit order due to erratum RP2350-E6. 1136 #define RVCSR_PMPCFG1_R4_R_RESET _u(0x0) 1137 #define RVCSR_PMPCFG1_R4_R_BITS _u(0x00000004) 1138 #define RVCSR_PMPCFG1_R4_R_MSB _u(2) 1139 #define RVCSR_PMPCFG1_R4_R_LSB _u(2) 1140 #define RVCSR_PMPCFG1_R4_R_ACCESS "RW" 1141 // ----------------------------------------------------------------------------- 1142 // Field : RVCSR_PMPCFG1_R4_W 1143 // Description : Write permission for region 4 1144 #define RVCSR_PMPCFG1_R4_W_RESET _u(0x0) 1145 #define RVCSR_PMPCFG1_R4_W_BITS _u(0x00000002) 1146 #define RVCSR_PMPCFG1_R4_W_MSB _u(1) 1147 #define RVCSR_PMPCFG1_R4_W_LSB _u(1) 1148 #define RVCSR_PMPCFG1_R4_W_ACCESS "RW" 1149 // ----------------------------------------------------------------------------- 1150 // Field : RVCSR_PMPCFG1_R4_X 1151 // Description : Execute permission for region 4. Note R and X are transposed 1152 // from the standard bit order due to erratum RP2350-E6. 1153 #define RVCSR_PMPCFG1_R4_X_RESET _u(0x0) 1154 #define RVCSR_PMPCFG1_R4_X_BITS _u(0x00000001) 1155 #define RVCSR_PMPCFG1_R4_X_MSB _u(0) 1156 #define RVCSR_PMPCFG1_R4_X_LSB _u(0) 1157 #define RVCSR_PMPCFG1_R4_X_ACCESS "RW" 1158 // ============================================================================= 1159 // Register : RVCSR_PMPCFG2 1160 // Description : Physical memory protection configuration for regions 8 through 1161 // 11 1162 #define RVCSR_PMPCFG2_OFFSET _u(0x000003a2) 1163 #define RVCSR_PMPCFG2_BITS _u(0x9f9f9f9f) 1164 #define RVCSR_PMPCFG2_RESET _u(0x001f1f1f) 1165 // ----------------------------------------------------------------------------- 1166 // Field : RVCSR_PMPCFG2_R11_L 1167 // Description : Lock region 11, and apply it to M-mode as well as U-mode. 1168 #define RVCSR_PMPCFG2_R11_L_RESET _u(0x0) 1169 #define RVCSR_PMPCFG2_R11_L_BITS _u(0x80000000) 1170 #define RVCSR_PMPCFG2_R11_L_MSB _u(31) 1171 #define RVCSR_PMPCFG2_R11_L_LSB _u(31) 1172 #define RVCSR_PMPCFG2_R11_L_ACCESS "RO" 1173 // ----------------------------------------------------------------------------- 1174 // Field : RVCSR_PMPCFG2_R11_A 1175 // Description : Address matching type for region 11. Writing an unsupported 1176 // value (TOR) will set the region to OFF. 1177 // 0x0 -> Disable region 1178 // 0x2 -> Naturally aligned 4-byte 1179 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1180 #define RVCSR_PMPCFG2_R11_A_RESET _u(0x0) 1181 #define RVCSR_PMPCFG2_R11_A_BITS _u(0x18000000) 1182 #define RVCSR_PMPCFG2_R11_A_MSB _u(28) 1183 #define RVCSR_PMPCFG2_R11_A_LSB _u(27) 1184 #define RVCSR_PMPCFG2_R11_A_ACCESS "RO" 1185 #define RVCSR_PMPCFG2_R11_A_VALUE_OFF _u(0x0) 1186 #define RVCSR_PMPCFG2_R11_A_VALUE_NA4 _u(0x2) 1187 #define RVCSR_PMPCFG2_R11_A_VALUE_NAPOT _u(0x3) 1188 // ----------------------------------------------------------------------------- 1189 // Field : RVCSR_PMPCFG2_R11_R 1190 // Description : Read permission for region 11. Note R and X are transposed from 1191 // the standard bit order due to erratum RP2350-E6. 1192 #define RVCSR_PMPCFG2_R11_R_RESET _u(0x0) 1193 #define RVCSR_PMPCFG2_R11_R_BITS _u(0x04000000) 1194 #define RVCSR_PMPCFG2_R11_R_MSB _u(26) 1195 #define RVCSR_PMPCFG2_R11_R_LSB _u(26) 1196 #define RVCSR_PMPCFG2_R11_R_ACCESS "RO" 1197 // ----------------------------------------------------------------------------- 1198 // Field : RVCSR_PMPCFG2_R11_W 1199 // Description : Write permission for region 11 1200 #define RVCSR_PMPCFG2_R11_W_RESET _u(0x0) 1201 #define RVCSR_PMPCFG2_R11_W_BITS _u(0x02000000) 1202 #define RVCSR_PMPCFG2_R11_W_MSB _u(25) 1203 #define RVCSR_PMPCFG2_R11_W_LSB _u(25) 1204 #define RVCSR_PMPCFG2_R11_W_ACCESS "RO" 1205 // ----------------------------------------------------------------------------- 1206 // Field : RVCSR_PMPCFG2_R11_X 1207 // Description : Execute permission for region 11. Note R and X are transposed 1208 // from the standard bit order due to erratum RP2350-E6. 1209 #define RVCSR_PMPCFG2_R11_X_RESET _u(0x0) 1210 #define RVCSR_PMPCFG2_R11_X_BITS _u(0x01000000) 1211 #define RVCSR_PMPCFG2_R11_X_MSB _u(24) 1212 #define RVCSR_PMPCFG2_R11_X_LSB _u(24) 1213 #define RVCSR_PMPCFG2_R11_X_ACCESS "RO" 1214 // ----------------------------------------------------------------------------- 1215 // Field : RVCSR_PMPCFG2_R10_L 1216 // Description : Lock region 10, and apply it to M-mode as well as U-mode. 1217 #define RVCSR_PMPCFG2_R10_L_RESET _u(0x0) 1218 #define RVCSR_PMPCFG2_R10_L_BITS _u(0x00800000) 1219 #define RVCSR_PMPCFG2_R10_L_MSB _u(23) 1220 #define RVCSR_PMPCFG2_R10_L_LSB _u(23) 1221 #define RVCSR_PMPCFG2_R10_L_ACCESS "RO" 1222 // ----------------------------------------------------------------------------- 1223 // Field : RVCSR_PMPCFG2_R10_A 1224 // Description : Address matching type for region 10. Writing an unsupported 1225 // value (TOR) will set the region to OFF. 1226 // 0x0 -> Disable region 1227 // 0x2 -> Naturally aligned 4-byte 1228 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1229 #define RVCSR_PMPCFG2_R10_A_RESET _u(0x3) 1230 #define RVCSR_PMPCFG2_R10_A_BITS _u(0x00180000) 1231 #define RVCSR_PMPCFG2_R10_A_MSB _u(20) 1232 #define RVCSR_PMPCFG2_R10_A_LSB _u(19) 1233 #define RVCSR_PMPCFG2_R10_A_ACCESS "RO" 1234 #define RVCSR_PMPCFG2_R10_A_VALUE_OFF _u(0x0) 1235 #define RVCSR_PMPCFG2_R10_A_VALUE_NA4 _u(0x2) 1236 #define RVCSR_PMPCFG2_R10_A_VALUE_NAPOT _u(0x3) 1237 // ----------------------------------------------------------------------------- 1238 // Field : RVCSR_PMPCFG2_R10_R 1239 // Description : Read permission for region 10. Note R and X are transposed from 1240 // the standard bit order due to erratum RP2350-E6. 1241 #define RVCSR_PMPCFG2_R10_R_RESET _u(0x1) 1242 #define RVCSR_PMPCFG2_R10_R_BITS _u(0x00040000) 1243 #define RVCSR_PMPCFG2_R10_R_MSB _u(18) 1244 #define RVCSR_PMPCFG2_R10_R_LSB _u(18) 1245 #define RVCSR_PMPCFG2_R10_R_ACCESS "RO" 1246 // ----------------------------------------------------------------------------- 1247 // Field : RVCSR_PMPCFG2_R10_W 1248 // Description : Write permission for region 10 1249 #define RVCSR_PMPCFG2_R10_W_RESET _u(0x1) 1250 #define RVCSR_PMPCFG2_R10_W_BITS _u(0x00020000) 1251 #define RVCSR_PMPCFG2_R10_W_MSB _u(17) 1252 #define RVCSR_PMPCFG2_R10_W_LSB _u(17) 1253 #define RVCSR_PMPCFG2_R10_W_ACCESS "RO" 1254 // ----------------------------------------------------------------------------- 1255 // Field : RVCSR_PMPCFG2_R10_X 1256 // Description : Execute permission for region 10. Note R and X are transposed 1257 // from the standard bit order due to erratum RP2350-E6. 1258 #define RVCSR_PMPCFG2_R10_X_RESET _u(0x1) 1259 #define RVCSR_PMPCFG2_R10_X_BITS _u(0x00010000) 1260 #define RVCSR_PMPCFG2_R10_X_MSB _u(16) 1261 #define RVCSR_PMPCFG2_R10_X_LSB _u(16) 1262 #define RVCSR_PMPCFG2_R10_X_ACCESS "RO" 1263 // ----------------------------------------------------------------------------- 1264 // Field : RVCSR_PMPCFG2_R9_L 1265 // Description : Lock region 9, and apply it to M-mode as well as U-mode. 1266 #define RVCSR_PMPCFG2_R9_L_RESET _u(0x0) 1267 #define RVCSR_PMPCFG2_R9_L_BITS _u(0x00008000) 1268 #define RVCSR_PMPCFG2_R9_L_MSB _u(15) 1269 #define RVCSR_PMPCFG2_R9_L_LSB _u(15) 1270 #define RVCSR_PMPCFG2_R9_L_ACCESS "RO" 1271 // ----------------------------------------------------------------------------- 1272 // Field : RVCSR_PMPCFG2_R9_A 1273 // Description : Address matching type for region 9. Writing an unsupported 1274 // value (TOR) will set the region to OFF. 1275 // 0x0 -> Disable region 1276 // 0x2 -> Naturally aligned 4-byte 1277 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1278 #define RVCSR_PMPCFG2_R9_A_RESET _u(0x3) 1279 #define RVCSR_PMPCFG2_R9_A_BITS _u(0x00001800) 1280 #define RVCSR_PMPCFG2_R9_A_MSB _u(12) 1281 #define RVCSR_PMPCFG2_R9_A_LSB _u(11) 1282 #define RVCSR_PMPCFG2_R9_A_ACCESS "RO" 1283 #define RVCSR_PMPCFG2_R9_A_VALUE_OFF _u(0x0) 1284 #define RVCSR_PMPCFG2_R9_A_VALUE_NA4 _u(0x2) 1285 #define RVCSR_PMPCFG2_R9_A_VALUE_NAPOT _u(0x3) 1286 // ----------------------------------------------------------------------------- 1287 // Field : RVCSR_PMPCFG2_R9_R 1288 // Description : Read permission for region 9. Note R and X are transposed from 1289 // the standard bit order due to erratum RP2350-E6. 1290 #define RVCSR_PMPCFG2_R9_R_RESET _u(0x1) 1291 #define RVCSR_PMPCFG2_R9_R_BITS _u(0x00000400) 1292 #define RVCSR_PMPCFG2_R9_R_MSB _u(10) 1293 #define RVCSR_PMPCFG2_R9_R_LSB _u(10) 1294 #define RVCSR_PMPCFG2_R9_R_ACCESS "RO" 1295 // ----------------------------------------------------------------------------- 1296 // Field : RVCSR_PMPCFG2_R9_W 1297 // Description : Write permission for region 9 1298 #define RVCSR_PMPCFG2_R9_W_RESET _u(0x1) 1299 #define RVCSR_PMPCFG2_R9_W_BITS _u(0x00000200) 1300 #define RVCSR_PMPCFG2_R9_W_MSB _u(9) 1301 #define RVCSR_PMPCFG2_R9_W_LSB _u(9) 1302 #define RVCSR_PMPCFG2_R9_W_ACCESS "RO" 1303 // ----------------------------------------------------------------------------- 1304 // Field : RVCSR_PMPCFG2_R9_X 1305 // Description : Execute permission for region 9. Note R and X are transposed 1306 // from the standard bit order due to erratum RP2350-E6. 1307 #define RVCSR_PMPCFG2_R9_X_RESET _u(0x1) 1308 #define RVCSR_PMPCFG2_R9_X_BITS _u(0x00000100) 1309 #define RVCSR_PMPCFG2_R9_X_MSB _u(8) 1310 #define RVCSR_PMPCFG2_R9_X_LSB _u(8) 1311 #define RVCSR_PMPCFG2_R9_X_ACCESS "RO" 1312 // ----------------------------------------------------------------------------- 1313 // Field : RVCSR_PMPCFG2_R8_L 1314 // Description : Lock region 8, and apply it to M-mode as well as U-mode. 1315 #define RVCSR_PMPCFG2_R8_L_RESET _u(0x0) 1316 #define RVCSR_PMPCFG2_R8_L_BITS _u(0x00000080) 1317 #define RVCSR_PMPCFG2_R8_L_MSB _u(7) 1318 #define RVCSR_PMPCFG2_R8_L_LSB _u(7) 1319 #define RVCSR_PMPCFG2_R8_L_ACCESS "RO" 1320 // ----------------------------------------------------------------------------- 1321 // Field : RVCSR_PMPCFG2_R8_A 1322 // Description : Address matching type for region 8. Writing an unsupported 1323 // value (TOR) will set the region to OFF. 1324 // 0x0 -> Disable region 1325 // 0x2 -> Naturally aligned 4-byte 1326 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1327 #define RVCSR_PMPCFG2_R8_A_RESET _u(0x3) 1328 #define RVCSR_PMPCFG2_R8_A_BITS _u(0x00000018) 1329 #define RVCSR_PMPCFG2_R8_A_MSB _u(4) 1330 #define RVCSR_PMPCFG2_R8_A_LSB _u(3) 1331 #define RVCSR_PMPCFG2_R8_A_ACCESS "RO" 1332 #define RVCSR_PMPCFG2_R8_A_VALUE_OFF _u(0x0) 1333 #define RVCSR_PMPCFG2_R8_A_VALUE_NA4 _u(0x2) 1334 #define RVCSR_PMPCFG2_R8_A_VALUE_NAPOT _u(0x3) 1335 // ----------------------------------------------------------------------------- 1336 // Field : RVCSR_PMPCFG2_R8_R 1337 // Description : Read permission for region 8. Note R and X are transposed from 1338 // the standard bit order due to erratum RP2350-E6. 1339 #define RVCSR_PMPCFG2_R8_R_RESET _u(0x1) 1340 #define RVCSR_PMPCFG2_R8_R_BITS _u(0x00000004) 1341 #define RVCSR_PMPCFG2_R8_R_MSB _u(2) 1342 #define RVCSR_PMPCFG2_R8_R_LSB _u(2) 1343 #define RVCSR_PMPCFG2_R8_R_ACCESS "RO" 1344 // ----------------------------------------------------------------------------- 1345 // Field : RVCSR_PMPCFG2_R8_W 1346 // Description : Write permission for region 8 1347 #define RVCSR_PMPCFG2_R8_W_RESET _u(0x1) 1348 #define RVCSR_PMPCFG2_R8_W_BITS _u(0x00000002) 1349 #define RVCSR_PMPCFG2_R8_W_MSB _u(1) 1350 #define RVCSR_PMPCFG2_R8_W_LSB _u(1) 1351 #define RVCSR_PMPCFG2_R8_W_ACCESS "RO" 1352 // ----------------------------------------------------------------------------- 1353 // Field : RVCSR_PMPCFG2_R8_X 1354 // Description : Execute permission for region 8. Note R and X are transposed 1355 // from the standard bit order due to erratum RP2350-E6. 1356 #define RVCSR_PMPCFG2_R8_X_RESET _u(0x1) 1357 #define RVCSR_PMPCFG2_R8_X_BITS _u(0x00000001) 1358 #define RVCSR_PMPCFG2_R8_X_MSB _u(0) 1359 #define RVCSR_PMPCFG2_R8_X_LSB _u(0) 1360 #define RVCSR_PMPCFG2_R8_X_ACCESS "RO" 1361 // ============================================================================= 1362 // Register : RVCSR_PMPCFG3 1363 // Description : Physical memory protection configuration for regions 12 through 1364 // 15 1365 #define RVCSR_PMPCFG3_OFFSET _u(0x000003a3) 1366 #define RVCSR_PMPCFG3_BITS _u(0x9f9f9f9f) 1367 #define RVCSR_PMPCFG3_RESET _u(0x00000000) 1368 // ----------------------------------------------------------------------------- 1369 // Field : RVCSR_PMPCFG3_R15_L 1370 // Description : Lock region 15, and apply it to M-mode as well as U-mode. 1371 #define RVCSR_PMPCFG3_R15_L_RESET _u(0x0) 1372 #define RVCSR_PMPCFG3_R15_L_BITS _u(0x80000000) 1373 #define RVCSR_PMPCFG3_R15_L_MSB _u(31) 1374 #define RVCSR_PMPCFG3_R15_L_LSB _u(31) 1375 #define RVCSR_PMPCFG3_R15_L_ACCESS "RO" 1376 // ----------------------------------------------------------------------------- 1377 // Field : RVCSR_PMPCFG3_R15_A 1378 // Description : Address matching type for region 15. Writing an unsupported 1379 // value (TOR) will set the region to OFF. 1380 // 0x0 -> Disable region 1381 // 0x2 -> Naturally aligned 4-byte 1382 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1383 #define RVCSR_PMPCFG3_R15_A_RESET _u(0x0) 1384 #define RVCSR_PMPCFG3_R15_A_BITS _u(0x18000000) 1385 #define RVCSR_PMPCFG3_R15_A_MSB _u(28) 1386 #define RVCSR_PMPCFG3_R15_A_LSB _u(27) 1387 #define RVCSR_PMPCFG3_R15_A_ACCESS "RO" 1388 #define RVCSR_PMPCFG3_R15_A_VALUE_OFF _u(0x0) 1389 #define RVCSR_PMPCFG3_R15_A_VALUE_NA4 _u(0x2) 1390 #define RVCSR_PMPCFG3_R15_A_VALUE_NAPOT _u(0x3) 1391 // ----------------------------------------------------------------------------- 1392 // Field : RVCSR_PMPCFG3_R15_R 1393 // Description : Read permission for region 15. Note R and X are transposed from 1394 // the standard bit order due to erratum RP2350-E6. 1395 #define RVCSR_PMPCFG3_R15_R_RESET _u(0x0) 1396 #define RVCSR_PMPCFG3_R15_R_BITS _u(0x04000000) 1397 #define RVCSR_PMPCFG3_R15_R_MSB _u(26) 1398 #define RVCSR_PMPCFG3_R15_R_LSB _u(26) 1399 #define RVCSR_PMPCFG3_R15_R_ACCESS "RO" 1400 // ----------------------------------------------------------------------------- 1401 // Field : RVCSR_PMPCFG3_R15_W 1402 // Description : Write permission for region 15 1403 #define RVCSR_PMPCFG3_R15_W_RESET _u(0x0) 1404 #define RVCSR_PMPCFG3_R15_W_BITS _u(0x02000000) 1405 #define RVCSR_PMPCFG3_R15_W_MSB _u(25) 1406 #define RVCSR_PMPCFG3_R15_W_LSB _u(25) 1407 #define RVCSR_PMPCFG3_R15_W_ACCESS "RO" 1408 // ----------------------------------------------------------------------------- 1409 // Field : RVCSR_PMPCFG3_R15_X 1410 // Description : Execute permission for region 15. Note R and X are transposed 1411 // from the standard bit order due to erratum RP2350-E6. 1412 #define RVCSR_PMPCFG3_R15_X_RESET _u(0x0) 1413 #define RVCSR_PMPCFG3_R15_X_BITS _u(0x01000000) 1414 #define RVCSR_PMPCFG3_R15_X_MSB _u(24) 1415 #define RVCSR_PMPCFG3_R15_X_LSB _u(24) 1416 #define RVCSR_PMPCFG3_R15_X_ACCESS "RO" 1417 // ----------------------------------------------------------------------------- 1418 // Field : RVCSR_PMPCFG3_R14_L 1419 // Description : Lock region 14, and apply it to M-mode as well as U-mode. 1420 #define RVCSR_PMPCFG3_R14_L_RESET _u(0x0) 1421 #define RVCSR_PMPCFG3_R14_L_BITS _u(0x00800000) 1422 #define RVCSR_PMPCFG3_R14_L_MSB _u(23) 1423 #define RVCSR_PMPCFG3_R14_L_LSB _u(23) 1424 #define RVCSR_PMPCFG3_R14_L_ACCESS "RO" 1425 // ----------------------------------------------------------------------------- 1426 // Field : RVCSR_PMPCFG3_R14_A 1427 // Description : Address matching type for region 14. Writing an unsupported 1428 // value (TOR) will set the region to OFF. 1429 // 0x0 -> Disable region 1430 // 0x2 -> Naturally aligned 4-byte 1431 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1432 #define RVCSR_PMPCFG3_R14_A_RESET _u(0x0) 1433 #define RVCSR_PMPCFG3_R14_A_BITS _u(0x00180000) 1434 #define RVCSR_PMPCFG3_R14_A_MSB _u(20) 1435 #define RVCSR_PMPCFG3_R14_A_LSB _u(19) 1436 #define RVCSR_PMPCFG3_R14_A_ACCESS "RO" 1437 #define RVCSR_PMPCFG3_R14_A_VALUE_OFF _u(0x0) 1438 #define RVCSR_PMPCFG3_R14_A_VALUE_NA4 _u(0x2) 1439 #define RVCSR_PMPCFG3_R14_A_VALUE_NAPOT _u(0x3) 1440 // ----------------------------------------------------------------------------- 1441 // Field : RVCSR_PMPCFG3_R14_R 1442 // Description : Read permission for region 14. Note R and X are transposed from 1443 // the standard bit order due to erratum RP2350-E6. 1444 #define RVCSR_PMPCFG3_R14_R_RESET _u(0x0) 1445 #define RVCSR_PMPCFG3_R14_R_BITS _u(0x00040000) 1446 #define RVCSR_PMPCFG3_R14_R_MSB _u(18) 1447 #define RVCSR_PMPCFG3_R14_R_LSB _u(18) 1448 #define RVCSR_PMPCFG3_R14_R_ACCESS "RO" 1449 // ----------------------------------------------------------------------------- 1450 // Field : RVCSR_PMPCFG3_R14_W 1451 // Description : Write permission for region 14 1452 #define RVCSR_PMPCFG3_R14_W_RESET _u(0x0) 1453 #define RVCSR_PMPCFG3_R14_W_BITS _u(0x00020000) 1454 #define RVCSR_PMPCFG3_R14_W_MSB _u(17) 1455 #define RVCSR_PMPCFG3_R14_W_LSB _u(17) 1456 #define RVCSR_PMPCFG3_R14_W_ACCESS "RO" 1457 // ----------------------------------------------------------------------------- 1458 // Field : RVCSR_PMPCFG3_R14_X 1459 // Description : Execute permission for region 14. Note R and X are transposed 1460 // from the standard bit order due to erratum RP2350-E6. 1461 #define RVCSR_PMPCFG3_R14_X_RESET _u(0x0) 1462 #define RVCSR_PMPCFG3_R14_X_BITS _u(0x00010000) 1463 #define RVCSR_PMPCFG3_R14_X_MSB _u(16) 1464 #define RVCSR_PMPCFG3_R14_X_LSB _u(16) 1465 #define RVCSR_PMPCFG3_R14_X_ACCESS "RO" 1466 // ----------------------------------------------------------------------------- 1467 // Field : RVCSR_PMPCFG3_R13_L 1468 // Description : Lock region 13, and apply it to M-mode as well as U-mode. 1469 #define RVCSR_PMPCFG3_R13_L_RESET _u(0x0) 1470 #define RVCSR_PMPCFG3_R13_L_BITS _u(0x00008000) 1471 #define RVCSR_PMPCFG3_R13_L_MSB _u(15) 1472 #define RVCSR_PMPCFG3_R13_L_LSB _u(15) 1473 #define RVCSR_PMPCFG3_R13_L_ACCESS "RO" 1474 // ----------------------------------------------------------------------------- 1475 // Field : RVCSR_PMPCFG3_R13_A 1476 // Description : Address matching type for region 13. Writing an unsupported 1477 // value (TOR) will set the region to OFF. 1478 // 0x0 -> Disable region 1479 // 0x2 -> Naturally aligned 4-byte 1480 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1481 #define RVCSR_PMPCFG3_R13_A_RESET _u(0x0) 1482 #define RVCSR_PMPCFG3_R13_A_BITS _u(0x00001800) 1483 #define RVCSR_PMPCFG3_R13_A_MSB _u(12) 1484 #define RVCSR_PMPCFG3_R13_A_LSB _u(11) 1485 #define RVCSR_PMPCFG3_R13_A_ACCESS "RO" 1486 #define RVCSR_PMPCFG3_R13_A_VALUE_OFF _u(0x0) 1487 #define RVCSR_PMPCFG3_R13_A_VALUE_NA4 _u(0x2) 1488 #define RVCSR_PMPCFG3_R13_A_VALUE_NAPOT _u(0x3) 1489 // ----------------------------------------------------------------------------- 1490 // Field : RVCSR_PMPCFG3_R13_R 1491 // Description : Read permission for region 13. Note R and X are transposed from 1492 // the standard bit order due to erratum RP2350-E6. 1493 #define RVCSR_PMPCFG3_R13_R_RESET _u(0x0) 1494 #define RVCSR_PMPCFG3_R13_R_BITS _u(0x00000400) 1495 #define RVCSR_PMPCFG3_R13_R_MSB _u(10) 1496 #define RVCSR_PMPCFG3_R13_R_LSB _u(10) 1497 #define RVCSR_PMPCFG3_R13_R_ACCESS "RO" 1498 // ----------------------------------------------------------------------------- 1499 // Field : RVCSR_PMPCFG3_R13_W 1500 // Description : Write permission for region 13 1501 #define RVCSR_PMPCFG3_R13_W_RESET _u(0x0) 1502 #define RVCSR_PMPCFG3_R13_W_BITS _u(0x00000200) 1503 #define RVCSR_PMPCFG3_R13_W_MSB _u(9) 1504 #define RVCSR_PMPCFG3_R13_W_LSB _u(9) 1505 #define RVCSR_PMPCFG3_R13_W_ACCESS "RO" 1506 // ----------------------------------------------------------------------------- 1507 // Field : RVCSR_PMPCFG3_R13_X 1508 // Description : Execute permission for region 13. Note R and X are transposed 1509 // from the standard bit order due to erratum RP2350-E6. 1510 #define RVCSR_PMPCFG3_R13_X_RESET _u(0x0) 1511 #define RVCSR_PMPCFG3_R13_X_BITS _u(0x00000100) 1512 #define RVCSR_PMPCFG3_R13_X_MSB _u(8) 1513 #define RVCSR_PMPCFG3_R13_X_LSB _u(8) 1514 #define RVCSR_PMPCFG3_R13_X_ACCESS "RO" 1515 // ----------------------------------------------------------------------------- 1516 // Field : RVCSR_PMPCFG3_R12_L 1517 // Description : Lock region 12, and apply it to M-mode as well as U-mode. 1518 #define RVCSR_PMPCFG3_R12_L_RESET _u(0x0) 1519 #define RVCSR_PMPCFG3_R12_L_BITS _u(0x00000080) 1520 #define RVCSR_PMPCFG3_R12_L_MSB _u(7) 1521 #define RVCSR_PMPCFG3_R12_L_LSB _u(7) 1522 #define RVCSR_PMPCFG3_R12_L_ACCESS "RO" 1523 // ----------------------------------------------------------------------------- 1524 // Field : RVCSR_PMPCFG3_R12_A 1525 // Description : Address matching type for region 12. Writing an unsupported 1526 // value (TOR) will set the region to OFF. 1527 // 0x0 -> Disable region 1528 // 0x2 -> Naturally aligned 4-byte 1529 // 0x3 -> Naturally aligned power-of-two (8 bytes to 4 GiB) 1530 #define RVCSR_PMPCFG3_R12_A_RESET _u(0x0) 1531 #define RVCSR_PMPCFG3_R12_A_BITS _u(0x00000018) 1532 #define RVCSR_PMPCFG3_R12_A_MSB _u(4) 1533 #define RVCSR_PMPCFG3_R12_A_LSB _u(3) 1534 #define RVCSR_PMPCFG3_R12_A_ACCESS "RO" 1535 #define RVCSR_PMPCFG3_R12_A_VALUE_OFF _u(0x0) 1536 #define RVCSR_PMPCFG3_R12_A_VALUE_NA4 _u(0x2) 1537 #define RVCSR_PMPCFG3_R12_A_VALUE_NAPOT _u(0x3) 1538 // ----------------------------------------------------------------------------- 1539 // Field : RVCSR_PMPCFG3_R12_R 1540 // Description : Read permission for region 12. Note R and X are transposed from 1541 // the standard bit order due to erratum RP2350-E6. 1542 #define RVCSR_PMPCFG3_R12_R_RESET _u(0x0) 1543 #define RVCSR_PMPCFG3_R12_R_BITS _u(0x00000004) 1544 #define RVCSR_PMPCFG3_R12_R_MSB _u(2) 1545 #define RVCSR_PMPCFG3_R12_R_LSB _u(2) 1546 #define RVCSR_PMPCFG3_R12_R_ACCESS "RO" 1547 // ----------------------------------------------------------------------------- 1548 // Field : RVCSR_PMPCFG3_R12_W 1549 // Description : Write permission for region 12 1550 #define RVCSR_PMPCFG3_R12_W_RESET _u(0x0) 1551 #define RVCSR_PMPCFG3_R12_W_BITS _u(0x00000002) 1552 #define RVCSR_PMPCFG3_R12_W_MSB _u(1) 1553 #define RVCSR_PMPCFG3_R12_W_LSB _u(1) 1554 #define RVCSR_PMPCFG3_R12_W_ACCESS "RO" 1555 // ----------------------------------------------------------------------------- 1556 // Field : RVCSR_PMPCFG3_R12_X 1557 // Description : Execute permission for region 12. Note R and X are transposed 1558 // from the standard bit order due to erratum RP2350-E6. 1559 #define RVCSR_PMPCFG3_R12_X_RESET _u(0x0) 1560 #define RVCSR_PMPCFG3_R12_X_BITS _u(0x00000001) 1561 #define RVCSR_PMPCFG3_R12_X_MSB _u(0) 1562 #define RVCSR_PMPCFG3_R12_X_LSB _u(0) 1563 #define RVCSR_PMPCFG3_R12_X_ACCESS "RO" 1564 // ============================================================================= 1565 // Register : RVCSR_PMPADDR0 1566 // Description : Physical memory protection address for region 0. Note all PMP 1567 // addresses are in units of four bytes. 1568 #define RVCSR_PMPADDR0_OFFSET _u(0x000003b0) 1569 #define RVCSR_PMPADDR0_BITS _u(0x3fffffff) 1570 #define RVCSR_PMPADDR0_RESET _u(0x00000000) 1571 #define RVCSR_PMPADDR0_MSB _u(29) 1572 #define RVCSR_PMPADDR0_LSB _u(0) 1573 #define RVCSR_PMPADDR0_ACCESS "RW" 1574 // ============================================================================= 1575 // Register : RVCSR_PMPADDR1 1576 // Description : Physical memory protection address for region 1. Note all PMP 1577 // addresses are in units of four bytes. 1578 #define RVCSR_PMPADDR1_OFFSET _u(0x000003b1) 1579 #define RVCSR_PMPADDR1_BITS _u(0x3fffffff) 1580 #define RVCSR_PMPADDR1_RESET _u(0x00000000) 1581 #define RVCSR_PMPADDR1_MSB _u(29) 1582 #define RVCSR_PMPADDR1_LSB _u(0) 1583 #define RVCSR_PMPADDR1_ACCESS "RW" 1584 // ============================================================================= 1585 // Register : RVCSR_PMPADDR2 1586 // Description : Physical memory protection address for region 2. Note all PMP 1587 // addresses are in units of four bytes. 1588 #define RVCSR_PMPADDR2_OFFSET _u(0x000003b2) 1589 #define RVCSR_PMPADDR2_BITS _u(0x3fffffff) 1590 #define RVCSR_PMPADDR2_RESET _u(0x00000000) 1591 #define RVCSR_PMPADDR2_MSB _u(29) 1592 #define RVCSR_PMPADDR2_LSB _u(0) 1593 #define RVCSR_PMPADDR2_ACCESS "RW" 1594 // ============================================================================= 1595 // Register : RVCSR_PMPADDR3 1596 // Description : Physical memory protection address for region 3. Note all PMP 1597 // addresses are in units of four bytes. 1598 #define RVCSR_PMPADDR3_OFFSET _u(0x000003b3) 1599 #define RVCSR_PMPADDR3_BITS _u(0x3fffffff) 1600 #define RVCSR_PMPADDR3_RESET _u(0x00000000) 1601 #define RVCSR_PMPADDR3_MSB _u(29) 1602 #define RVCSR_PMPADDR3_LSB _u(0) 1603 #define RVCSR_PMPADDR3_ACCESS "RW" 1604 // ============================================================================= 1605 // Register : RVCSR_PMPADDR4 1606 // Description : Physical memory protection address for region 4. Note all PMP 1607 // addresses are in units of four bytes. 1608 #define RVCSR_PMPADDR4_OFFSET _u(0x000003b4) 1609 #define RVCSR_PMPADDR4_BITS _u(0x3fffffff) 1610 #define RVCSR_PMPADDR4_RESET _u(0x00000000) 1611 #define RVCSR_PMPADDR4_MSB _u(29) 1612 #define RVCSR_PMPADDR4_LSB _u(0) 1613 #define RVCSR_PMPADDR4_ACCESS "RW" 1614 // ============================================================================= 1615 // Register : RVCSR_PMPADDR5 1616 // Description : Physical memory protection address for region 5. Note all PMP 1617 // addresses are in units of four bytes. 1618 #define RVCSR_PMPADDR5_OFFSET _u(0x000003b5) 1619 #define RVCSR_PMPADDR5_BITS _u(0x3fffffff) 1620 #define RVCSR_PMPADDR5_RESET _u(0x00000000) 1621 #define RVCSR_PMPADDR5_MSB _u(29) 1622 #define RVCSR_PMPADDR5_LSB _u(0) 1623 #define RVCSR_PMPADDR5_ACCESS "RW" 1624 // ============================================================================= 1625 // Register : RVCSR_PMPADDR6 1626 // Description : Physical memory protection address for region 6. Note all PMP 1627 // addresses are in units of four bytes. 1628 #define RVCSR_PMPADDR6_OFFSET _u(0x000003b6) 1629 #define RVCSR_PMPADDR6_BITS _u(0x3fffffff) 1630 #define RVCSR_PMPADDR6_RESET _u(0x00000000) 1631 #define RVCSR_PMPADDR6_MSB _u(29) 1632 #define RVCSR_PMPADDR6_LSB _u(0) 1633 #define RVCSR_PMPADDR6_ACCESS "RW" 1634 // ============================================================================= 1635 // Register : RVCSR_PMPADDR7 1636 // Description : Physical memory protection address for region 7. Note all PMP 1637 // addresses are in units of four bytes. 1638 #define RVCSR_PMPADDR7_OFFSET _u(0x000003b7) 1639 #define RVCSR_PMPADDR7_BITS _u(0x3fffffff) 1640 #define RVCSR_PMPADDR7_RESET _u(0x00000000) 1641 #define RVCSR_PMPADDR7_MSB _u(29) 1642 #define RVCSR_PMPADDR7_LSB _u(0) 1643 #define RVCSR_PMPADDR7_ACCESS "RW" 1644 // ============================================================================= 1645 // Register : RVCSR_PMPADDR8 1646 // Description : Physical memory protection address for region 8. Note all PMP 1647 // addresses are in units of four bytes. 1648 // 1649 // Hardwired to the address range `0x00000000` through 1650 // `0x0fffffff`, which contains the boot ROM. This range is made 1651 // accessible to User mode by default. User mode access to this 1652 // range can be disabled using one of the dynamically configurable 1653 // PMP regions, or using the permission registers in ACCESSCTRL. 1654 #define RVCSR_PMPADDR8_OFFSET _u(0x000003b8) 1655 #define RVCSR_PMPADDR8_BITS _u(0x3fffffff) 1656 #define RVCSR_PMPADDR8_RESET _u(0x01ffffff) 1657 #define RVCSR_PMPADDR8_MSB _u(29) 1658 #define RVCSR_PMPADDR8_LSB _u(0) 1659 #define RVCSR_PMPADDR8_ACCESS "RO" 1660 // ============================================================================= 1661 // Register : RVCSR_PMPADDR9 1662 // Description : Physical memory protection address for region 9. Note all PMP 1663 // addresses are in units of four bytes. 1664 // 1665 // Hardwired to the address range `0x40000000` through 1666 // `0x5fffffff`, which contains the system peripherals. This range 1667 // is made accessible to User mode by default. User mode access to 1668 // this range can be disabled using one of the dynamically 1669 // configurable PMP regions, or using the permission registers in 1670 // ACCESSCTRL. 1671 #define RVCSR_PMPADDR9_OFFSET _u(0x000003b9) 1672 #define RVCSR_PMPADDR9_BITS _u(0x3fffffff) 1673 #define RVCSR_PMPADDR9_RESET _u(0x13ffffff) 1674 #define RVCSR_PMPADDR9_MSB _u(29) 1675 #define RVCSR_PMPADDR9_LSB _u(0) 1676 #define RVCSR_PMPADDR9_ACCESS "RO" 1677 // ============================================================================= 1678 // Register : RVCSR_PMPADDR10 1679 // Description : Physical memory protection address for region 10. Note all PMP 1680 // addresses are in units of four bytes. 1681 // 1682 // Hardwired to the address range `0xd0000000` through 1683 // `0xdfffffff`, which contains the core-local peripherals (SIO). 1684 // This range is made accessible to User mode by default. User 1685 // mode access to this range can be disabled using one of the 1686 // dynamically configurable PMP regions, or using the permission 1687 // registers in ACCESSCTRL. 1688 #define RVCSR_PMPADDR10_OFFSET _u(0x000003ba) 1689 #define RVCSR_PMPADDR10_BITS _u(0x3fffffff) 1690 #define RVCSR_PMPADDR10_RESET _u(0x35ffffff) 1691 #define RVCSR_PMPADDR10_MSB _u(29) 1692 #define RVCSR_PMPADDR10_LSB _u(0) 1693 #define RVCSR_PMPADDR10_ACCESS "RO" 1694 // ============================================================================= 1695 // Register : RVCSR_PMPADDR11 1696 // Description : Physical memory protection address for region 11. Note all PMP 1697 // addresses are in units of four bytes. 1698 // 1699 // Hardwired to all-zeroes. This region is not implemented. 1700 #define RVCSR_PMPADDR11_OFFSET _u(0x000003bb) 1701 #define RVCSR_PMPADDR11_BITS _u(0x3fffffff) 1702 #define RVCSR_PMPADDR11_RESET _u(0x00000000) 1703 #define RVCSR_PMPADDR11_MSB _u(29) 1704 #define RVCSR_PMPADDR11_LSB _u(0) 1705 #define RVCSR_PMPADDR11_ACCESS "RO" 1706 // ============================================================================= 1707 // Register : RVCSR_PMPADDR12 1708 // Description : Physical memory protection address for region 12. Note all PMP 1709 // addresses are in units of four bytes. 1710 // 1711 // Hardwired to all-zeroes. This region is not implemented. 1712 #define RVCSR_PMPADDR12_OFFSET _u(0x000003bc) 1713 #define RVCSR_PMPADDR12_BITS _u(0x3fffffff) 1714 #define RVCSR_PMPADDR12_RESET _u(0x00000000) 1715 #define RVCSR_PMPADDR12_MSB _u(29) 1716 #define RVCSR_PMPADDR12_LSB _u(0) 1717 #define RVCSR_PMPADDR12_ACCESS "RO" 1718 // ============================================================================= 1719 // Register : RVCSR_PMPADDR13 1720 // Description : Physical memory protection address for region 13. Note all PMP 1721 // addresses are in units of four bytes. 1722 // 1723 // Hardwired to all-zeroes. This region is not implemented. 1724 #define RVCSR_PMPADDR13_OFFSET _u(0x000003bd) 1725 #define RVCSR_PMPADDR13_BITS _u(0x3fffffff) 1726 #define RVCSR_PMPADDR13_RESET _u(0x00000000) 1727 #define RVCSR_PMPADDR13_MSB _u(29) 1728 #define RVCSR_PMPADDR13_LSB _u(0) 1729 #define RVCSR_PMPADDR13_ACCESS "RO" 1730 // ============================================================================= 1731 // Register : RVCSR_PMPADDR14 1732 // Description : Physical memory protection address for region 14. Note all PMP 1733 // addresses are in units of four bytes. 1734 // 1735 // Hardwired to all-zeroes. This region is not implemented. 1736 #define RVCSR_PMPADDR14_OFFSET _u(0x000003be) 1737 #define RVCSR_PMPADDR14_BITS _u(0x3fffffff) 1738 #define RVCSR_PMPADDR14_RESET _u(0x00000000) 1739 #define RVCSR_PMPADDR14_MSB _u(29) 1740 #define RVCSR_PMPADDR14_LSB _u(0) 1741 #define RVCSR_PMPADDR14_ACCESS "RO" 1742 // ============================================================================= 1743 // Register : RVCSR_PMPADDR15 1744 // Description : Physical memory protection address for region 15. Note all PMP 1745 // addresses are in units of four bytes. 1746 // 1747 // Hardwired to all-zeroes. This region is not implemented. 1748 #define RVCSR_PMPADDR15_OFFSET _u(0x000003bf) 1749 #define RVCSR_PMPADDR15_BITS _u(0x3fffffff) 1750 #define RVCSR_PMPADDR15_RESET _u(0x00000000) 1751 #define RVCSR_PMPADDR15_MSB _u(29) 1752 #define RVCSR_PMPADDR15_LSB _u(0) 1753 #define RVCSR_PMPADDR15_ACCESS "RO" 1754 // ============================================================================= 1755 // Register : RVCSR_TSELECT 1756 // Description : Select trigger to be configured via `tdata1`/`tdata2` 1757 // 1758 // On RP2350, four instruction address triggers are implemented, 1759 // so only the two LSBs of this register are writable. 1760 #define RVCSR_TSELECT_OFFSET _u(0x000007a0) 1761 #define RVCSR_TSELECT_BITS _u(0x00000003) 1762 #define RVCSR_TSELECT_RESET _u(0x00000000) 1763 #define RVCSR_TSELECT_MSB _u(1) 1764 #define RVCSR_TSELECT_LSB _u(0) 1765 #define RVCSR_TSELECT_ACCESS "RW" 1766 // ============================================================================= 1767 // Register : RVCSR_TDATA1 1768 // Description : Trigger configuration data 1 1769 // 1770 // Hazard 3 only supports address/data match triggers (type=2) so 1771 // this register description includes the `mcontrol` fields for 1772 // this type. 1773 // 1774 // More precisely, Hazard3 only supports exact instruction address 1775 // match triggers (hardware breakpoints) so many of this 1776 // register's fields are hardwired. 1777 #define RVCSR_TDATA1_OFFSET _u(0x000007a1) 1778 #define RVCSR_TDATA1_BITS _u(0xffffffcf) 1779 #define RVCSR_TDATA1_RESET _u(0x20000000) 1780 // ----------------------------------------------------------------------------- 1781 // Field : RVCSR_TDATA1_TYPE 1782 // Description : Trigger type. Hardwired to type=2, meaning an address/data 1783 // match trigger 1784 #define RVCSR_TDATA1_TYPE_RESET _u(0x2) 1785 #define RVCSR_TDATA1_TYPE_BITS _u(0xf0000000) 1786 #define RVCSR_TDATA1_TYPE_MSB _u(31) 1787 #define RVCSR_TDATA1_TYPE_LSB _u(28) 1788 #define RVCSR_TDATA1_TYPE_ACCESS "RO" 1789 // ----------------------------------------------------------------------------- 1790 // Field : RVCSR_TDATA1_DMODE 1791 // Description : If 0, both Debug and M-mode can write the `tdata` registers at 1792 // the selected `tselect`. 1793 // 1794 // If 1, only Debug Mode can write the `tdata` registers at the 1795 // selected `tselect`. Writes from other modes are ignored. 1796 // 1797 // This bit is only writable from Debug Mode 1798 #define RVCSR_TDATA1_DMODE_RESET _u(0x0) 1799 #define RVCSR_TDATA1_DMODE_BITS _u(0x08000000) 1800 #define RVCSR_TDATA1_DMODE_MSB _u(27) 1801 #define RVCSR_TDATA1_DMODE_LSB _u(27) 1802 #define RVCSR_TDATA1_DMODE_ACCESS "RW" 1803 // ----------------------------------------------------------------------------- 1804 // Field : RVCSR_TDATA1_MASKMAX 1805 // Description : Value of 0 indicates only exact address matches are supported 1806 #define RVCSR_TDATA1_MASKMAX_RESET _u(0x00) 1807 #define RVCSR_TDATA1_MASKMAX_BITS _u(0x07e00000) 1808 #define RVCSR_TDATA1_MASKMAX_MSB _u(26) 1809 #define RVCSR_TDATA1_MASKMAX_LSB _u(21) 1810 #define RVCSR_TDATA1_MASKMAX_ACCESS "RO" 1811 // ----------------------------------------------------------------------------- 1812 // Field : RVCSR_TDATA1_HIT 1813 // Description : Trigger hit flag. Not implemented, hardwired to 0. 1814 #define RVCSR_TDATA1_HIT_RESET _u(0x0) 1815 #define RVCSR_TDATA1_HIT_BITS _u(0x00100000) 1816 #define RVCSR_TDATA1_HIT_MSB _u(20) 1817 #define RVCSR_TDATA1_HIT_LSB _u(20) 1818 #define RVCSR_TDATA1_HIT_ACCESS "RO" 1819 // ----------------------------------------------------------------------------- 1820 // Field : RVCSR_TDATA1_SELECT 1821 // Description : Hardwired value of 0 indicates that only address matches are 1822 // supported, not data matches 1823 #define RVCSR_TDATA1_SELECT_RESET _u(0x0) 1824 #define RVCSR_TDATA1_SELECT_BITS _u(0x00080000) 1825 #define RVCSR_TDATA1_SELECT_MSB _u(19) 1826 #define RVCSR_TDATA1_SELECT_LSB _u(19) 1827 #define RVCSR_TDATA1_SELECT_ACCESS "RO" 1828 // ----------------------------------------------------------------------------- 1829 // Field : RVCSR_TDATA1_TIMING 1830 // Description : Hardwired value of 0 indicates that trigger fires before the 1831 // triggering instruction executes, not afterward 1832 #define RVCSR_TDATA1_TIMING_RESET _u(0x0) 1833 #define RVCSR_TDATA1_TIMING_BITS _u(0x00040000) 1834 #define RVCSR_TDATA1_TIMING_MSB _u(18) 1835 #define RVCSR_TDATA1_TIMING_LSB _u(18) 1836 #define RVCSR_TDATA1_TIMING_ACCESS "RO" 1837 // ----------------------------------------------------------------------------- 1838 // Field : RVCSR_TDATA1_SIZELO 1839 // Description : Hardwired value of 0 indicates that access size matching is not 1840 // supported 1841 #define RVCSR_TDATA1_SIZELO_RESET _u(0x0) 1842 #define RVCSR_TDATA1_SIZELO_BITS _u(0x00030000) 1843 #define RVCSR_TDATA1_SIZELO_MSB _u(17) 1844 #define RVCSR_TDATA1_SIZELO_LSB _u(16) 1845 #define RVCSR_TDATA1_SIZELO_ACCESS "RO" 1846 // ----------------------------------------------------------------------------- 1847 // Field : RVCSR_TDATA1_ACTION 1848 // Description : Select action to be taken when the trigger fires. 1849 // 0x0 -> Raise a breakpoint exception, which can be handled by the M-mode exception handler 1850 // 0x1 -> Enter debug mode. This action is only selectable when `tdata1.dmode` is 1. 1851 #define RVCSR_TDATA1_ACTION_RESET _u(0x0) 1852 #define RVCSR_TDATA1_ACTION_BITS _u(0x0000f000) 1853 #define RVCSR_TDATA1_ACTION_MSB _u(15) 1854 #define RVCSR_TDATA1_ACTION_LSB _u(12) 1855 #define RVCSR_TDATA1_ACTION_ACCESS "RW" 1856 #define RVCSR_TDATA1_ACTION_VALUE_EBREAK _u(0x0) 1857 #define RVCSR_TDATA1_ACTION_VALUE_DEBUG _u(0x1) 1858 // ----------------------------------------------------------------------------- 1859 // Field : RVCSR_TDATA1_CHAIN 1860 // Description : Hardwired to 0 to indicate trigger chaining is not supported. 1861 #define RVCSR_TDATA1_CHAIN_RESET _u(0x0) 1862 #define RVCSR_TDATA1_CHAIN_BITS _u(0x00000800) 1863 #define RVCSR_TDATA1_CHAIN_MSB _u(11) 1864 #define RVCSR_TDATA1_CHAIN_LSB _u(11) 1865 #define RVCSR_TDATA1_CHAIN_ACCESS "RO" 1866 // ----------------------------------------------------------------------------- 1867 // Field : RVCSR_TDATA1_MATCH 1868 // Description : Hardwired to 0 to indicate match is always on the full address 1869 // specified by `tdata2` 1870 #define RVCSR_TDATA1_MATCH_RESET _u(0x0) 1871 #define RVCSR_TDATA1_MATCH_BITS _u(0x00000780) 1872 #define RVCSR_TDATA1_MATCH_MSB _u(10) 1873 #define RVCSR_TDATA1_MATCH_LSB _u(7) 1874 #define RVCSR_TDATA1_MATCH_ACCESS "RO" 1875 // ----------------------------------------------------------------------------- 1876 // Field : RVCSR_TDATA1_M 1877 // Description : When set, enable this trigger in M-mode 1878 #define RVCSR_TDATA1_M_RESET _u(0x0) 1879 #define RVCSR_TDATA1_M_BITS _u(0x00000040) 1880 #define RVCSR_TDATA1_M_MSB _u(6) 1881 #define RVCSR_TDATA1_M_LSB _u(6) 1882 #define RVCSR_TDATA1_M_ACCESS "RW" 1883 // ----------------------------------------------------------------------------- 1884 // Field : RVCSR_TDATA1_U 1885 // Description : When set, enable this trigger in U-mode 1886 #define RVCSR_TDATA1_U_RESET _u(0x0) 1887 #define RVCSR_TDATA1_U_BITS _u(0x00000008) 1888 #define RVCSR_TDATA1_U_MSB _u(3) 1889 #define RVCSR_TDATA1_U_LSB _u(3) 1890 #define RVCSR_TDATA1_U_ACCESS "RW" 1891 // ----------------------------------------------------------------------------- 1892 // Field : RVCSR_TDATA1_EXECUTE 1893 // Description : When set, the trigger fires on the address of an instruction 1894 // that is executed. 1895 #define RVCSR_TDATA1_EXECUTE_RESET _u(0x0) 1896 #define RVCSR_TDATA1_EXECUTE_BITS _u(0x00000004) 1897 #define RVCSR_TDATA1_EXECUTE_MSB _u(2) 1898 #define RVCSR_TDATA1_EXECUTE_LSB _u(2) 1899 #define RVCSR_TDATA1_EXECUTE_ACCESS "RW" 1900 // ----------------------------------------------------------------------------- 1901 // Field : RVCSR_TDATA1_STORE 1902 // Description : Hardwired to 0 to indicate store address/data triggers are not 1903 // supported 1904 #define RVCSR_TDATA1_STORE_RESET _u(0x0) 1905 #define RVCSR_TDATA1_STORE_BITS _u(0x00000002) 1906 #define RVCSR_TDATA1_STORE_MSB _u(1) 1907 #define RVCSR_TDATA1_STORE_LSB _u(1) 1908 #define RVCSR_TDATA1_STORE_ACCESS "RO" 1909 // ----------------------------------------------------------------------------- 1910 // Field : RVCSR_TDATA1_LOAD 1911 // Description : Hardwired to 0 to indicate load address/data triggers are not 1912 // supported 1913 #define RVCSR_TDATA1_LOAD_RESET _u(0x0) 1914 #define RVCSR_TDATA1_LOAD_BITS _u(0x00000001) 1915 #define RVCSR_TDATA1_LOAD_MSB _u(0) 1916 #define RVCSR_TDATA1_LOAD_LSB _u(0) 1917 #define RVCSR_TDATA1_LOAD_ACCESS "RO" 1918 // ============================================================================= 1919 // Register : RVCSR_TDATA2 1920 // Description : Trigger configuration data 2 1921 // 1922 // Contains the address for instruction address triggers (hardware 1923 // breakpoints) 1924 #define RVCSR_TDATA2_OFFSET _u(0x000007a2) 1925 #define RVCSR_TDATA2_BITS _u(0xffffffff) 1926 #define RVCSR_TDATA2_RESET _u(0x00000000) 1927 #define RVCSR_TDATA2_MSB _u(31) 1928 #define RVCSR_TDATA2_LSB _u(0) 1929 #define RVCSR_TDATA2_ACCESS "RW" 1930 // ============================================================================= 1931 // Register : RVCSR_DCSR 1932 // Description : Debug control and status register. Access outside of Debug Mode 1933 // will cause an illegal instruction exception. 1934 #define RVCSR_DCSR_OFFSET _u(0x000007b0) 1935 #define RVCSR_DCSR_BITS _u(0xf0009fc7) 1936 #define RVCSR_DCSR_RESET _u(0x40000603) 1937 // ----------------------------------------------------------------------------- 1938 // Field : RVCSR_DCSR_XDEBUGVER 1939 // Description : Hardwired to 4: external debug support as per RISC-V 0.13.2 1940 // debug specification. 1941 #define RVCSR_DCSR_XDEBUGVER_RESET _u(0x4) 1942 #define RVCSR_DCSR_XDEBUGVER_BITS _u(0xf0000000) 1943 #define RVCSR_DCSR_XDEBUGVER_MSB _u(31) 1944 #define RVCSR_DCSR_XDEBUGVER_LSB _u(28) 1945 #define RVCSR_DCSR_XDEBUGVER_ACCESS "RO" 1946 // ----------------------------------------------------------------------------- 1947 // Field : RVCSR_DCSR_EBREAKM 1948 // Description : When 1, `ebreak` instructions executed in M-mode will break to 1949 // Debug Mode instead of trapping 1950 #define RVCSR_DCSR_EBREAKM_RESET _u(0x0) 1951 #define RVCSR_DCSR_EBREAKM_BITS _u(0x00008000) 1952 #define RVCSR_DCSR_EBREAKM_MSB _u(15) 1953 #define RVCSR_DCSR_EBREAKM_LSB _u(15) 1954 #define RVCSR_DCSR_EBREAKM_ACCESS "RW" 1955 // ----------------------------------------------------------------------------- 1956 // Field : RVCSR_DCSR_EBREAKU 1957 // Description : When 1, `ebreak` instructions executed in U-mode will break to 1958 // Debug Mode instead of trapping. 1959 #define RVCSR_DCSR_EBREAKU_RESET _u(0x0) 1960 #define RVCSR_DCSR_EBREAKU_BITS _u(0x00001000) 1961 #define RVCSR_DCSR_EBREAKU_MSB _u(12) 1962 #define RVCSR_DCSR_EBREAKU_LSB _u(12) 1963 #define RVCSR_DCSR_EBREAKU_ACCESS "RW" 1964 // ----------------------------------------------------------------------------- 1965 // Field : RVCSR_DCSR_STEPIE 1966 // Description : Hardwired to 0: no interrupts are taken during hardware single- 1967 // stepping. 1968 #define RVCSR_DCSR_STEPIE_RESET _u(0x0) 1969 #define RVCSR_DCSR_STEPIE_BITS _u(0x00000800) 1970 #define RVCSR_DCSR_STEPIE_MSB _u(11) 1971 #define RVCSR_DCSR_STEPIE_LSB _u(11) 1972 #define RVCSR_DCSR_STEPIE_ACCESS "RO" 1973 // ----------------------------------------------------------------------------- 1974 // Field : RVCSR_DCSR_STOPCOUNT 1975 // Description : Hardwired to 1: `mcycle`/`mcycleh` and `minstret`/`minstreth` 1976 // do not increment in Debug Mode. 1977 #define RVCSR_DCSR_STOPCOUNT_RESET _u(0x1) 1978 #define RVCSR_DCSR_STOPCOUNT_BITS _u(0x00000400) 1979 #define RVCSR_DCSR_STOPCOUNT_MSB _u(10) 1980 #define RVCSR_DCSR_STOPCOUNT_LSB _u(10) 1981 #define RVCSR_DCSR_STOPCOUNT_ACCESS "RO" 1982 // ----------------------------------------------------------------------------- 1983 // Field : RVCSR_DCSR_STOPTIME 1984 // Description : Hardwired to 1: core-local timers don't increment in debug 1985 // mode. External timers (e.g. hart-shared) may be configured to 1986 // ignore this. 1987 #define RVCSR_DCSR_STOPTIME_RESET _u(0x1) 1988 #define RVCSR_DCSR_STOPTIME_BITS _u(0x00000200) 1989 #define RVCSR_DCSR_STOPTIME_MSB _u(9) 1990 #define RVCSR_DCSR_STOPTIME_LSB _u(9) 1991 #define RVCSR_DCSR_STOPTIME_ACCESS "RO" 1992 // ----------------------------------------------------------------------------- 1993 // Field : RVCSR_DCSR_CAUSE 1994 // Description : Set by hardware when entering debug mode. 1995 // 0x1 -> An ebreak instruction was executed when the relevant `dcsr.ebreakx` bit was set. 1996 // 0x2 -> The trigger module caused a breakpoint exception. 1997 // 0x3 -> Processor entered Debug Mode due to a halt request, or a reset-halt request present when the core reset was released. 1998 // 0x4 -> Processor entered Debug Mode after executing one instruction with single-stepping enabled. 1999 #define RVCSR_DCSR_CAUSE_RESET _u(0x0) 2000 #define RVCSR_DCSR_CAUSE_BITS _u(0x000001c0) 2001 #define RVCSR_DCSR_CAUSE_MSB _u(8) 2002 #define RVCSR_DCSR_CAUSE_LSB _u(6) 2003 #define RVCSR_DCSR_CAUSE_ACCESS "RO" 2004 #define RVCSR_DCSR_CAUSE_VALUE_EBREAK _u(0x1) 2005 #define RVCSR_DCSR_CAUSE_VALUE_TRIGGER _u(0x2) 2006 #define RVCSR_DCSR_CAUSE_VALUE_HALTREQ _u(0x3) 2007 #define RVCSR_DCSR_CAUSE_VALUE_STEP _u(0x4) 2008 // ----------------------------------------------------------------------------- 2009 // Field : RVCSR_DCSR_STEP 2010 // Description : When 1, re-enter Debug Mode after each instruction executed in 2011 // M-mode or U-mode. 2012 #define RVCSR_DCSR_STEP_RESET _u(0x0) 2013 #define RVCSR_DCSR_STEP_BITS _u(0x00000004) 2014 #define RVCSR_DCSR_STEP_MSB _u(2) 2015 #define RVCSR_DCSR_STEP_LSB _u(2) 2016 #define RVCSR_DCSR_STEP_ACCESS "RW" 2017 // ----------------------------------------------------------------------------- 2018 // Field : RVCSR_DCSR_PRV 2019 // Description : Read the privilege mode the core was in when entering Debug 2020 // Mode, and set the privilege mode the core will execute in when 2021 // returning from Debug Mode. 2022 #define RVCSR_DCSR_PRV_RESET _u(0x3) 2023 #define RVCSR_DCSR_PRV_BITS _u(0x00000003) 2024 #define RVCSR_DCSR_PRV_MSB _u(1) 2025 #define RVCSR_DCSR_PRV_LSB _u(0) 2026 #define RVCSR_DCSR_PRV_ACCESS "RW" 2027 // ============================================================================= 2028 // Register : RVCSR_DPC 2029 // Description : Debug program counter. When entering Debug Mode, `dpc` samples 2030 // the current program counter, e.g. the address of an `ebreak` 2031 // which caused Debug Mode entry. When leaving debug mode, the 2032 // processor jumps to `dpc`. The host may read/write this register 2033 // whilst in Debug Mode. 2034 #define RVCSR_DPC_OFFSET _u(0x000007b1) 2035 #define RVCSR_DPC_BITS _u(0xfffffffe) 2036 #define RVCSR_DPC_RESET _u(0x00000000) 2037 #define RVCSR_DPC_MSB _u(31) 2038 #define RVCSR_DPC_LSB _u(1) 2039 #define RVCSR_DPC_ACCESS "RW" 2040 // ============================================================================= 2041 // Register : RVCSR_MCYCLE 2042 // Description : Machine-mode cycle counter, low half 2043 // Counts up once per cycle, when `mcountinhibit.cy` is 0. 2044 // Disabled by default to save power. 2045 #define RVCSR_MCYCLE_OFFSET _u(0x00000b00) 2046 #define RVCSR_MCYCLE_BITS _u(0xffffffff) 2047 #define RVCSR_MCYCLE_RESET _u(0x00000000) 2048 #define RVCSR_MCYCLE_MSB _u(31) 2049 #define RVCSR_MCYCLE_LSB _u(0) 2050 #define RVCSR_MCYCLE_ACCESS "RW" 2051 // ============================================================================= 2052 // Register : RVCSR_MINSTRET 2053 // Description : Machine-mode instruction retire counter, low half 2054 // Counts up once per instruction, when `mcountinhibit.ir` is 0. 2055 // Disabled by default to save power. 2056 #define RVCSR_MINSTRET_OFFSET _u(0x00000b02) 2057 #define RVCSR_MINSTRET_BITS _u(0xffffffff) 2058 #define RVCSR_MINSTRET_RESET _u(0x00000000) 2059 #define RVCSR_MINSTRET_MSB _u(31) 2060 #define RVCSR_MINSTRET_LSB _u(0) 2061 #define RVCSR_MINSTRET_ACCESS "RW" 2062 // ============================================================================= 2063 // Register : RVCSR_MHPMCOUNTER3 2064 // Description : Extended performance counter, hardwired to 0. 2065 #define RVCSR_MHPMCOUNTER3_OFFSET _u(0x00000b03) 2066 #define RVCSR_MHPMCOUNTER3_BITS _u(0xffffffff) 2067 #define RVCSR_MHPMCOUNTER3_RESET _u(0x00000000) 2068 #define RVCSR_MHPMCOUNTER3_MSB _u(31) 2069 #define RVCSR_MHPMCOUNTER3_LSB _u(0) 2070 #define RVCSR_MHPMCOUNTER3_ACCESS "RO" 2071 // ============================================================================= 2072 // Register : RVCSR_MHPMCOUNTER4 2073 // Description : Extended performance counter, hardwired to 0. 2074 #define RVCSR_MHPMCOUNTER4_OFFSET _u(0x00000b04) 2075 #define RVCSR_MHPMCOUNTER4_BITS _u(0xffffffff) 2076 #define RVCSR_MHPMCOUNTER4_RESET _u(0x00000000) 2077 #define RVCSR_MHPMCOUNTER4_MSB _u(31) 2078 #define RVCSR_MHPMCOUNTER4_LSB _u(0) 2079 #define RVCSR_MHPMCOUNTER4_ACCESS "RO" 2080 // ============================================================================= 2081 // Register : RVCSR_MHPMCOUNTER5 2082 // Description : Extended performance counter, hardwired to 0. 2083 #define RVCSR_MHPMCOUNTER5_OFFSET _u(0x00000b05) 2084 #define RVCSR_MHPMCOUNTER5_BITS _u(0xffffffff) 2085 #define RVCSR_MHPMCOUNTER5_RESET _u(0x00000000) 2086 #define RVCSR_MHPMCOUNTER5_MSB _u(31) 2087 #define RVCSR_MHPMCOUNTER5_LSB _u(0) 2088 #define RVCSR_MHPMCOUNTER5_ACCESS "RO" 2089 // ============================================================================= 2090 // Register : RVCSR_MHPMCOUNTER6 2091 // Description : Extended performance counter, hardwired to 0. 2092 #define RVCSR_MHPMCOUNTER6_OFFSET _u(0x00000b06) 2093 #define RVCSR_MHPMCOUNTER6_BITS _u(0xffffffff) 2094 #define RVCSR_MHPMCOUNTER6_RESET _u(0x00000000) 2095 #define RVCSR_MHPMCOUNTER6_MSB _u(31) 2096 #define RVCSR_MHPMCOUNTER6_LSB _u(0) 2097 #define RVCSR_MHPMCOUNTER6_ACCESS "RO" 2098 // ============================================================================= 2099 // Register : RVCSR_MHPMCOUNTER7 2100 // Description : Extended performance counter, hardwired to 0. 2101 #define RVCSR_MHPMCOUNTER7_OFFSET _u(0x00000b07) 2102 #define RVCSR_MHPMCOUNTER7_BITS _u(0xffffffff) 2103 #define RVCSR_MHPMCOUNTER7_RESET _u(0x00000000) 2104 #define RVCSR_MHPMCOUNTER7_MSB _u(31) 2105 #define RVCSR_MHPMCOUNTER7_LSB _u(0) 2106 #define RVCSR_MHPMCOUNTER7_ACCESS "RO" 2107 // ============================================================================= 2108 // Register : RVCSR_MHPMCOUNTER8 2109 // Description : Extended performance counter, hardwired to 0. 2110 #define RVCSR_MHPMCOUNTER8_OFFSET _u(0x00000b08) 2111 #define RVCSR_MHPMCOUNTER8_BITS _u(0xffffffff) 2112 #define RVCSR_MHPMCOUNTER8_RESET _u(0x00000000) 2113 #define RVCSR_MHPMCOUNTER8_MSB _u(31) 2114 #define RVCSR_MHPMCOUNTER8_LSB _u(0) 2115 #define RVCSR_MHPMCOUNTER8_ACCESS "RO" 2116 // ============================================================================= 2117 // Register : RVCSR_MHPMCOUNTER9 2118 // Description : Extended performance counter, hardwired to 0. 2119 #define RVCSR_MHPMCOUNTER9_OFFSET _u(0x00000b09) 2120 #define RVCSR_MHPMCOUNTER9_BITS _u(0xffffffff) 2121 #define RVCSR_MHPMCOUNTER9_RESET _u(0x00000000) 2122 #define RVCSR_MHPMCOUNTER9_MSB _u(31) 2123 #define RVCSR_MHPMCOUNTER9_LSB _u(0) 2124 #define RVCSR_MHPMCOUNTER9_ACCESS "RO" 2125 // ============================================================================= 2126 // Register : RVCSR_MHPMCOUNTER10 2127 // Description : Extended performance counter, hardwired to 0. 2128 #define RVCSR_MHPMCOUNTER10_OFFSET _u(0x00000b0a) 2129 #define RVCSR_MHPMCOUNTER10_BITS _u(0xffffffff) 2130 #define RVCSR_MHPMCOUNTER10_RESET _u(0x00000000) 2131 #define RVCSR_MHPMCOUNTER10_MSB _u(31) 2132 #define RVCSR_MHPMCOUNTER10_LSB _u(0) 2133 #define RVCSR_MHPMCOUNTER10_ACCESS "RO" 2134 // ============================================================================= 2135 // Register : RVCSR_MHPMCOUNTER11 2136 // Description : Extended performance counter, hardwired to 0. 2137 #define RVCSR_MHPMCOUNTER11_OFFSET _u(0x00000b0b) 2138 #define RVCSR_MHPMCOUNTER11_BITS _u(0xffffffff) 2139 #define RVCSR_MHPMCOUNTER11_RESET _u(0x00000000) 2140 #define RVCSR_MHPMCOUNTER11_MSB _u(31) 2141 #define RVCSR_MHPMCOUNTER11_LSB _u(0) 2142 #define RVCSR_MHPMCOUNTER11_ACCESS "RO" 2143 // ============================================================================= 2144 // Register : RVCSR_MHPMCOUNTER12 2145 // Description : Extended performance counter, hardwired to 0. 2146 #define RVCSR_MHPMCOUNTER12_OFFSET _u(0x00000b0c) 2147 #define RVCSR_MHPMCOUNTER12_BITS _u(0xffffffff) 2148 #define RVCSR_MHPMCOUNTER12_RESET _u(0x00000000) 2149 #define RVCSR_MHPMCOUNTER12_MSB _u(31) 2150 #define RVCSR_MHPMCOUNTER12_LSB _u(0) 2151 #define RVCSR_MHPMCOUNTER12_ACCESS "RO" 2152 // ============================================================================= 2153 // Register : RVCSR_MHPMCOUNTER13 2154 // Description : Extended performance counter, hardwired to 0. 2155 #define RVCSR_MHPMCOUNTER13_OFFSET _u(0x00000b0d) 2156 #define RVCSR_MHPMCOUNTER13_BITS _u(0xffffffff) 2157 #define RVCSR_MHPMCOUNTER13_RESET _u(0x00000000) 2158 #define RVCSR_MHPMCOUNTER13_MSB _u(31) 2159 #define RVCSR_MHPMCOUNTER13_LSB _u(0) 2160 #define RVCSR_MHPMCOUNTER13_ACCESS "RO" 2161 // ============================================================================= 2162 // Register : RVCSR_MHPMCOUNTER14 2163 // Description : Extended performance counter, hardwired to 0. 2164 #define RVCSR_MHPMCOUNTER14_OFFSET _u(0x00000b0e) 2165 #define RVCSR_MHPMCOUNTER14_BITS _u(0xffffffff) 2166 #define RVCSR_MHPMCOUNTER14_RESET _u(0x00000000) 2167 #define RVCSR_MHPMCOUNTER14_MSB _u(31) 2168 #define RVCSR_MHPMCOUNTER14_LSB _u(0) 2169 #define RVCSR_MHPMCOUNTER14_ACCESS "RO" 2170 // ============================================================================= 2171 // Register : RVCSR_MHPMCOUNTER15 2172 // Description : Extended performance counter, hardwired to 0. 2173 #define RVCSR_MHPMCOUNTER15_OFFSET _u(0x00000b0f) 2174 #define RVCSR_MHPMCOUNTER15_BITS _u(0xffffffff) 2175 #define RVCSR_MHPMCOUNTER15_RESET _u(0x00000000) 2176 #define RVCSR_MHPMCOUNTER15_MSB _u(31) 2177 #define RVCSR_MHPMCOUNTER15_LSB _u(0) 2178 #define RVCSR_MHPMCOUNTER15_ACCESS "RO" 2179 // ============================================================================= 2180 // Register : RVCSR_MHPMCOUNTER16 2181 // Description : Extended performance counter, hardwired to 0. 2182 #define RVCSR_MHPMCOUNTER16_OFFSET _u(0x00000b10) 2183 #define RVCSR_MHPMCOUNTER16_BITS _u(0xffffffff) 2184 #define RVCSR_MHPMCOUNTER16_RESET _u(0x00000000) 2185 #define RVCSR_MHPMCOUNTER16_MSB _u(31) 2186 #define RVCSR_MHPMCOUNTER16_LSB _u(0) 2187 #define RVCSR_MHPMCOUNTER16_ACCESS "RO" 2188 // ============================================================================= 2189 // Register : RVCSR_MHPMCOUNTER17 2190 // Description : Extended performance counter, hardwired to 0. 2191 #define RVCSR_MHPMCOUNTER17_OFFSET _u(0x00000b11) 2192 #define RVCSR_MHPMCOUNTER17_BITS _u(0xffffffff) 2193 #define RVCSR_MHPMCOUNTER17_RESET _u(0x00000000) 2194 #define RVCSR_MHPMCOUNTER17_MSB _u(31) 2195 #define RVCSR_MHPMCOUNTER17_LSB _u(0) 2196 #define RVCSR_MHPMCOUNTER17_ACCESS "RO" 2197 // ============================================================================= 2198 // Register : RVCSR_MHPMCOUNTER18 2199 // Description : Extended performance counter, hardwired to 0. 2200 #define RVCSR_MHPMCOUNTER18_OFFSET _u(0x00000b12) 2201 #define RVCSR_MHPMCOUNTER18_BITS _u(0xffffffff) 2202 #define RVCSR_MHPMCOUNTER18_RESET _u(0x00000000) 2203 #define RVCSR_MHPMCOUNTER18_MSB _u(31) 2204 #define RVCSR_MHPMCOUNTER18_LSB _u(0) 2205 #define RVCSR_MHPMCOUNTER18_ACCESS "RO" 2206 // ============================================================================= 2207 // Register : RVCSR_MHPMCOUNTER19 2208 // Description : Extended performance counter, hardwired to 0. 2209 #define RVCSR_MHPMCOUNTER19_OFFSET _u(0x00000b13) 2210 #define RVCSR_MHPMCOUNTER19_BITS _u(0xffffffff) 2211 #define RVCSR_MHPMCOUNTER19_RESET _u(0x00000000) 2212 #define RVCSR_MHPMCOUNTER19_MSB _u(31) 2213 #define RVCSR_MHPMCOUNTER19_LSB _u(0) 2214 #define RVCSR_MHPMCOUNTER19_ACCESS "RO" 2215 // ============================================================================= 2216 // Register : RVCSR_MHPMCOUNTER20 2217 // Description : Extended performance counter, hardwired to 0. 2218 #define RVCSR_MHPMCOUNTER20_OFFSET _u(0x00000b14) 2219 #define RVCSR_MHPMCOUNTER20_BITS _u(0xffffffff) 2220 #define RVCSR_MHPMCOUNTER20_RESET _u(0x00000000) 2221 #define RVCSR_MHPMCOUNTER20_MSB _u(31) 2222 #define RVCSR_MHPMCOUNTER20_LSB _u(0) 2223 #define RVCSR_MHPMCOUNTER20_ACCESS "RO" 2224 // ============================================================================= 2225 // Register : RVCSR_MHPMCOUNTER21 2226 // Description : Extended performance counter, hardwired to 0. 2227 #define RVCSR_MHPMCOUNTER21_OFFSET _u(0x00000b15) 2228 #define RVCSR_MHPMCOUNTER21_BITS _u(0xffffffff) 2229 #define RVCSR_MHPMCOUNTER21_RESET _u(0x00000000) 2230 #define RVCSR_MHPMCOUNTER21_MSB _u(31) 2231 #define RVCSR_MHPMCOUNTER21_LSB _u(0) 2232 #define RVCSR_MHPMCOUNTER21_ACCESS "RO" 2233 // ============================================================================= 2234 // Register : RVCSR_MHPMCOUNTER22 2235 // Description : Extended performance counter, hardwired to 0. 2236 #define RVCSR_MHPMCOUNTER22_OFFSET _u(0x00000b16) 2237 #define RVCSR_MHPMCOUNTER22_BITS _u(0xffffffff) 2238 #define RVCSR_MHPMCOUNTER22_RESET _u(0x00000000) 2239 #define RVCSR_MHPMCOUNTER22_MSB _u(31) 2240 #define RVCSR_MHPMCOUNTER22_LSB _u(0) 2241 #define RVCSR_MHPMCOUNTER22_ACCESS "RO" 2242 // ============================================================================= 2243 // Register : RVCSR_MHPMCOUNTER23 2244 // Description : Extended performance counter, hardwired to 0. 2245 #define RVCSR_MHPMCOUNTER23_OFFSET _u(0x00000b17) 2246 #define RVCSR_MHPMCOUNTER23_BITS _u(0xffffffff) 2247 #define RVCSR_MHPMCOUNTER23_RESET _u(0x00000000) 2248 #define RVCSR_MHPMCOUNTER23_MSB _u(31) 2249 #define RVCSR_MHPMCOUNTER23_LSB _u(0) 2250 #define RVCSR_MHPMCOUNTER23_ACCESS "RO" 2251 // ============================================================================= 2252 // Register : RVCSR_MHPMCOUNTER24 2253 // Description : Extended performance counter, hardwired to 0. 2254 #define RVCSR_MHPMCOUNTER24_OFFSET _u(0x00000b18) 2255 #define RVCSR_MHPMCOUNTER24_BITS _u(0xffffffff) 2256 #define RVCSR_MHPMCOUNTER24_RESET _u(0x00000000) 2257 #define RVCSR_MHPMCOUNTER24_MSB _u(31) 2258 #define RVCSR_MHPMCOUNTER24_LSB _u(0) 2259 #define RVCSR_MHPMCOUNTER24_ACCESS "RO" 2260 // ============================================================================= 2261 // Register : RVCSR_MHPMCOUNTER25 2262 // Description : Extended performance counter, hardwired to 0. 2263 #define RVCSR_MHPMCOUNTER25_OFFSET _u(0x00000b19) 2264 #define RVCSR_MHPMCOUNTER25_BITS _u(0xffffffff) 2265 #define RVCSR_MHPMCOUNTER25_RESET _u(0x00000000) 2266 #define RVCSR_MHPMCOUNTER25_MSB _u(31) 2267 #define RVCSR_MHPMCOUNTER25_LSB _u(0) 2268 #define RVCSR_MHPMCOUNTER25_ACCESS "RO" 2269 // ============================================================================= 2270 // Register : RVCSR_MHPMCOUNTER26 2271 // Description : Extended performance counter, hardwired to 0. 2272 #define RVCSR_MHPMCOUNTER26_OFFSET _u(0x00000b1a) 2273 #define RVCSR_MHPMCOUNTER26_BITS _u(0xffffffff) 2274 #define RVCSR_MHPMCOUNTER26_RESET _u(0x00000000) 2275 #define RVCSR_MHPMCOUNTER26_MSB _u(31) 2276 #define RVCSR_MHPMCOUNTER26_LSB _u(0) 2277 #define RVCSR_MHPMCOUNTER26_ACCESS "RO" 2278 // ============================================================================= 2279 // Register : RVCSR_MHPMCOUNTER27 2280 // Description : Extended performance counter, hardwired to 0. 2281 #define RVCSR_MHPMCOUNTER27_OFFSET _u(0x00000b1b) 2282 #define RVCSR_MHPMCOUNTER27_BITS _u(0xffffffff) 2283 #define RVCSR_MHPMCOUNTER27_RESET _u(0x00000000) 2284 #define RVCSR_MHPMCOUNTER27_MSB _u(31) 2285 #define RVCSR_MHPMCOUNTER27_LSB _u(0) 2286 #define RVCSR_MHPMCOUNTER27_ACCESS "RO" 2287 // ============================================================================= 2288 // Register : RVCSR_MHPMCOUNTER28 2289 // Description : Extended performance counter, hardwired to 0. 2290 #define RVCSR_MHPMCOUNTER28_OFFSET _u(0x00000b1c) 2291 #define RVCSR_MHPMCOUNTER28_BITS _u(0xffffffff) 2292 #define RVCSR_MHPMCOUNTER28_RESET _u(0x00000000) 2293 #define RVCSR_MHPMCOUNTER28_MSB _u(31) 2294 #define RVCSR_MHPMCOUNTER28_LSB _u(0) 2295 #define RVCSR_MHPMCOUNTER28_ACCESS "RO" 2296 // ============================================================================= 2297 // Register : RVCSR_MHPMCOUNTER29 2298 // Description : Extended performance counter, hardwired to 0. 2299 #define RVCSR_MHPMCOUNTER29_OFFSET _u(0x00000b1d) 2300 #define RVCSR_MHPMCOUNTER29_BITS _u(0xffffffff) 2301 #define RVCSR_MHPMCOUNTER29_RESET _u(0x00000000) 2302 #define RVCSR_MHPMCOUNTER29_MSB _u(31) 2303 #define RVCSR_MHPMCOUNTER29_LSB _u(0) 2304 #define RVCSR_MHPMCOUNTER29_ACCESS "RO" 2305 // ============================================================================= 2306 // Register : RVCSR_MHPMCOUNTER30 2307 // Description : Extended performance counter, hardwired to 0. 2308 #define RVCSR_MHPMCOUNTER30_OFFSET _u(0x00000b1e) 2309 #define RVCSR_MHPMCOUNTER30_BITS _u(0xffffffff) 2310 #define RVCSR_MHPMCOUNTER30_RESET _u(0x00000000) 2311 #define RVCSR_MHPMCOUNTER30_MSB _u(31) 2312 #define RVCSR_MHPMCOUNTER30_LSB _u(0) 2313 #define RVCSR_MHPMCOUNTER30_ACCESS "RO" 2314 // ============================================================================= 2315 // Register : RVCSR_MHPMCOUNTER31 2316 // Description : Extended performance counter, hardwired to 0. 2317 #define RVCSR_MHPMCOUNTER31_OFFSET _u(0x00000b1f) 2318 #define RVCSR_MHPMCOUNTER31_BITS _u(0xffffffff) 2319 #define RVCSR_MHPMCOUNTER31_RESET _u(0x00000000) 2320 #define RVCSR_MHPMCOUNTER31_MSB _u(31) 2321 #define RVCSR_MHPMCOUNTER31_LSB _u(0) 2322 #define RVCSR_MHPMCOUNTER31_ACCESS "RO" 2323 // ============================================================================= 2324 // Register : RVCSR_MCYCLEH 2325 // Description : Machine-mode cycle counter, high half 2326 // Counts up once per 1 << 32 cycles, when `mcountinhibit.cy` is 2327 // 0. Disabled by default to save power. 2328 #define RVCSR_MCYCLEH_OFFSET _u(0x00000b80) 2329 #define RVCSR_MCYCLEH_BITS _u(0xffffffff) 2330 #define RVCSR_MCYCLEH_RESET _u(0x00000000) 2331 #define RVCSR_MCYCLEH_MSB _u(31) 2332 #define RVCSR_MCYCLEH_LSB _u(0) 2333 #define RVCSR_MCYCLEH_ACCESS "RW" 2334 // ============================================================================= 2335 // Register : RVCSR_MINSTRETH 2336 // Description : Machine-mode instruction retire counter, low half 2337 // Counts up once per 1 << 32 instructions, when 2338 // `mcountinhibit.ir` is 0. Disabled by default to save power. 2339 #define RVCSR_MINSTRETH_OFFSET _u(0x00000b82) 2340 #define RVCSR_MINSTRETH_BITS _u(0xffffffff) 2341 #define RVCSR_MINSTRETH_RESET _u(0x00000000) 2342 #define RVCSR_MINSTRETH_MSB _u(31) 2343 #define RVCSR_MINSTRETH_LSB _u(0) 2344 #define RVCSR_MINSTRETH_ACCESS "RW" 2345 // ============================================================================= 2346 // Register : RVCSR_MHPMCOUNTER3H 2347 // Description : Extended performance counter, hardwired to 0. 2348 #define RVCSR_MHPMCOUNTER3H_OFFSET _u(0x00000b83) 2349 #define RVCSR_MHPMCOUNTER3H_BITS _u(0xffffffff) 2350 #define RVCSR_MHPMCOUNTER3H_RESET _u(0x00000000) 2351 #define RVCSR_MHPMCOUNTER3H_MSB _u(31) 2352 #define RVCSR_MHPMCOUNTER3H_LSB _u(0) 2353 #define RVCSR_MHPMCOUNTER3H_ACCESS "RO" 2354 // ============================================================================= 2355 // Register : RVCSR_MHPMCOUNTER4H 2356 // Description : Extended performance counter, hardwired to 0. 2357 #define RVCSR_MHPMCOUNTER4H_OFFSET _u(0x00000b84) 2358 #define RVCSR_MHPMCOUNTER4H_BITS _u(0xffffffff) 2359 #define RVCSR_MHPMCOUNTER4H_RESET _u(0x00000000) 2360 #define RVCSR_MHPMCOUNTER4H_MSB _u(31) 2361 #define RVCSR_MHPMCOUNTER4H_LSB _u(0) 2362 #define RVCSR_MHPMCOUNTER4H_ACCESS "RO" 2363 // ============================================================================= 2364 // Register : RVCSR_MHPMCOUNTER5H 2365 // Description : Extended performance counter, hardwired to 0. 2366 #define RVCSR_MHPMCOUNTER5H_OFFSET _u(0x00000b85) 2367 #define RVCSR_MHPMCOUNTER5H_BITS _u(0xffffffff) 2368 #define RVCSR_MHPMCOUNTER5H_RESET _u(0x00000000) 2369 #define RVCSR_MHPMCOUNTER5H_MSB _u(31) 2370 #define RVCSR_MHPMCOUNTER5H_LSB _u(0) 2371 #define RVCSR_MHPMCOUNTER5H_ACCESS "RO" 2372 // ============================================================================= 2373 // Register : RVCSR_MHPMCOUNTER6H 2374 // Description : Extended performance counter, hardwired to 0. 2375 #define RVCSR_MHPMCOUNTER6H_OFFSET _u(0x00000b86) 2376 #define RVCSR_MHPMCOUNTER6H_BITS _u(0xffffffff) 2377 #define RVCSR_MHPMCOUNTER6H_RESET _u(0x00000000) 2378 #define RVCSR_MHPMCOUNTER6H_MSB _u(31) 2379 #define RVCSR_MHPMCOUNTER6H_LSB _u(0) 2380 #define RVCSR_MHPMCOUNTER6H_ACCESS "RO" 2381 // ============================================================================= 2382 // Register : RVCSR_MHPMCOUNTER7H 2383 // Description : Extended performance counter, hardwired to 0. 2384 #define RVCSR_MHPMCOUNTER7H_OFFSET _u(0x00000b87) 2385 #define RVCSR_MHPMCOUNTER7H_BITS _u(0xffffffff) 2386 #define RVCSR_MHPMCOUNTER7H_RESET _u(0x00000000) 2387 #define RVCSR_MHPMCOUNTER7H_MSB _u(31) 2388 #define RVCSR_MHPMCOUNTER7H_LSB _u(0) 2389 #define RVCSR_MHPMCOUNTER7H_ACCESS "RO" 2390 // ============================================================================= 2391 // Register : RVCSR_MHPMCOUNTER8H 2392 // Description : Extended performance counter, hardwired to 0. 2393 #define RVCSR_MHPMCOUNTER8H_OFFSET _u(0x00000b88) 2394 #define RVCSR_MHPMCOUNTER8H_BITS _u(0xffffffff) 2395 #define RVCSR_MHPMCOUNTER8H_RESET _u(0x00000000) 2396 #define RVCSR_MHPMCOUNTER8H_MSB _u(31) 2397 #define RVCSR_MHPMCOUNTER8H_LSB _u(0) 2398 #define RVCSR_MHPMCOUNTER8H_ACCESS "RO" 2399 // ============================================================================= 2400 // Register : RVCSR_MHPMCOUNTER9H 2401 // Description : Extended performance counter, hardwired to 0. 2402 #define RVCSR_MHPMCOUNTER9H_OFFSET _u(0x00000b89) 2403 #define RVCSR_MHPMCOUNTER9H_BITS _u(0xffffffff) 2404 #define RVCSR_MHPMCOUNTER9H_RESET _u(0x00000000) 2405 #define RVCSR_MHPMCOUNTER9H_MSB _u(31) 2406 #define RVCSR_MHPMCOUNTER9H_LSB _u(0) 2407 #define RVCSR_MHPMCOUNTER9H_ACCESS "RO" 2408 // ============================================================================= 2409 // Register : RVCSR_MHPMCOUNTER10H 2410 // Description : Extended performance counter, hardwired to 0. 2411 #define RVCSR_MHPMCOUNTER10H_OFFSET _u(0x00000b8a) 2412 #define RVCSR_MHPMCOUNTER10H_BITS _u(0xffffffff) 2413 #define RVCSR_MHPMCOUNTER10H_RESET _u(0x00000000) 2414 #define RVCSR_MHPMCOUNTER10H_MSB _u(31) 2415 #define RVCSR_MHPMCOUNTER10H_LSB _u(0) 2416 #define RVCSR_MHPMCOUNTER10H_ACCESS "RO" 2417 // ============================================================================= 2418 // Register : RVCSR_MHPMCOUNTER11H 2419 // Description : Extended performance counter, hardwired to 0. 2420 #define RVCSR_MHPMCOUNTER11H_OFFSET _u(0x00000b8b) 2421 #define RVCSR_MHPMCOUNTER11H_BITS _u(0xffffffff) 2422 #define RVCSR_MHPMCOUNTER11H_RESET _u(0x00000000) 2423 #define RVCSR_MHPMCOUNTER11H_MSB _u(31) 2424 #define RVCSR_MHPMCOUNTER11H_LSB _u(0) 2425 #define RVCSR_MHPMCOUNTER11H_ACCESS "RO" 2426 // ============================================================================= 2427 // Register : RVCSR_MHPMCOUNTER12H 2428 // Description : Extended performance counter, hardwired to 0. 2429 #define RVCSR_MHPMCOUNTER12H_OFFSET _u(0x00000b8c) 2430 #define RVCSR_MHPMCOUNTER12H_BITS _u(0xffffffff) 2431 #define RVCSR_MHPMCOUNTER12H_RESET _u(0x00000000) 2432 #define RVCSR_MHPMCOUNTER12H_MSB _u(31) 2433 #define RVCSR_MHPMCOUNTER12H_LSB _u(0) 2434 #define RVCSR_MHPMCOUNTER12H_ACCESS "RO" 2435 // ============================================================================= 2436 // Register : RVCSR_MHPMCOUNTER13H 2437 // Description : Extended performance counter, hardwired to 0. 2438 #define RVCSR_MHPMCOUNTER13H_OFFSET _u(0x00000b8d) 2439 #define RVCSR_MHPMCOUNTER13H_BITS _u(0xffffffff) 2440 #define RVCSR_MHPMCOUNTER13H_RESET _u(0x00000000) 2441 #define RVCSR_MHPMCOUNTER13H_MSB _u(31) 2442 #define RVCSR_MHPMCOUNTER13H_LSB _u(0) 2443 #define RVCSR_MHPMCOUNTER13H_ACCESS "RO" 2444 // ============================================================================= 2445 // Register : RVCSR_MHPMCOUNTER14H 2446 // Description : Extended performance counter, hardwired to 0. 2447 #define RVCSR_MHPMCOUNTER14H_OFFSET _u(0x00000b8e) 2448 #define RVCSR_MHPMCOUNTER14H_BITS _u(0xffffffff) 2449 #define RVCSR_MHPMCOUNTER14H_RESET _u(0x00000000) 2450 #define RVCSR_MHPMCOUNTER14H_MSB _u(31) 2451 #define RVCSR_MHPMCOUNTER14H_LSB _u(0) 2452 #define RVCSR_MHPMCOUNTER14H_ACCESS "RO" 2453 // ============================================================================= 2454 // Register : RVCSR_MHPMCOUNTER15H 2455 // Description : Extended performance counter, hardwired to 0. 2456 #define RVCSR_MHPMCOUNTER15H_OFFSET _u(0x00000b8f) 2457 #define RVCSR_MHPMCOUNTER15H_BITS _u(0xffffffff) 2458 #define RVCSR_MHPMCOUNTER15H_RESET _u(0x00000000) 2459 #define RVCSR_MHPMCOUNTER15H_MSB _u(31) 2460 #define RVCSR_MHPMCOUNTER15H_LSB _u(0) 2461 #define RVCSR_MHPMCOUNTER15H_ACCESS "RO" 2462 // ============================================================================= 2463 // Register : RVCSR_MHPMCOUNTER16H 2464 // Description : Extended performance counter, hardwired to 0. 2465 #define RVCSR_MHPMCOUNTER16H_OFFSET _u(0x00000b90) 2466 #define RVCSR_MHPMCOUNTER16H_BITS _u(0xffffffff) 2467 #define RVCSR_MHPMCOUNTER16H_RESET _u(0x00000000) 2468 #define RVCSR_MHPMCOUNTER16H_MSB _u(31) 2469 #define RVCSR_MHPMCOUNTER16H_LSB _u(0) 2470 #define RVCSR_MHPMCOUNTER16H_ACCESS "RO" 2471 // ============================================================================= 2472 // Register : RVCSR_MHPMCOUNTER17H 2473 // Description : Extended performance counter, hardwired to 0. 2474 #define RVCSR_MHPMCOUNTER17H_OFFSET _u(0x00000b91) 2475 #define RVCSR_MHPMCOUNTER17H_BITS _u(0xffffffff) 2476 #define RVCSR_MHPMCOUNTER17H_RESET _u(0x00000000) 2477 #define RVCSR_MHPMCOUNTER17H_MSB _u(31) 2478 #define RVCSR_MHPMCOUNTER17H_LSB _u(0) 2479 #define RVCSR_MHPMCOUNTER17H_ACCESS "RO" 2480 // ============================================================================= 2481 // Register : RVCSR_MHPMCOUNTER18H 2482 // Description : Extended performance counter, hardwired to 0. 2483 #define RVCSR_MHPMCOUNTER18H_OFFSET _u(0x00000b92) 2484 #define RVCSR_MHPMCOUNTER18H_BITS _u(0xffffffff) 2485 #define RVCSR_MHPMCOUNTER18H_RESET _u(0x00000000) 2486 #define RVCSR_MHPMCOUNTER18H_MSB _u(31) 2487 #define RVCSR_MHPMCOUNTER18H_LSB _u(0) 2488 #define RVCSR_MHPMCOUNTER18H_ACCESS "RO" 2489 // ============================================================================= 2490 // Register : RVCSR_MHPMCOUNTER19H 2491 // Description : Extended performance counter, hardwired to 0. 2492 #define RVCSR_MHPMCOUNTER19H_OFFSET _u(0x00000b93) 2493 #define RVCSR_MHPMCOUNTER19H_BITS _u(0xffffffff) 2494 #define RVCSR_MHPMCOUNTER19H_RESET _u(0x00000000) 2495 #define RVCSR_MHPMCOUNTER19H_MSB _u(31) 2496 #define RVCSR_MHPMCOUNTER19H_LSB _u(0) 2497 #define RVCSR_MHPMCOUNTER19H_ACCESS "RO" 2498 // ============================================================================= 2499 // Register : RVCSR_MHPMCOUNTER20H 2500 // Description : Extended performance counter, hardwired to 0. 2501 #define RVCSR_MHPMCOUNTER20H_OFFSET _u(0x00000b94) 2502 #define RVCSR_MHPMCOUNTER20H_BITS _u(0xffffffff) 2503 #define RVCSR_MHPMCOUNTER20H_RESET _u(0x00000000) 2504 #define RVCSR_MHPMCOUNTER20H_MSB _u(31) 2505 #define RVCSR_MHPMCOUNTER20H_LSB _u(0) 2506 #define RVCSR_MHPMCOUNTER20H_ACCESS "RO" 2507 // ============================================================================= 2508 // Register : RVCSR_MHPMCOUNTER21H 2509 // Description : Extended performance counter, hardwired to 0. 2510 #define RVCSR_MHPMCOUNTER21H_OFFSET _u(0x00000b95) 2511 #define RVCSR_MHPMCOUNTER21H_BITS _u(0xffffffff) 2512 #define RVCSR_MHPMCOUNTER21H_RESET _u(0x00000000) 2513 #define RVCSR_MHPMCOUNTER21H_MSB _u(31) 2514 #define RVCSR_MHPMCOUNTER21H_LSB _u(0) 2515 #define RVCSR_MHPMCOUNTER21H_ACCESS "RO" 2516 // ============================================================================= 2517 // Register : RVCSR_MHPMCOUNTER22H 2518 // Description : Extended performance counter, hardwired to 0. 2519 #define RVCSR_MHPMCOUNTER22H_OFFSET _u(0x00000b96) 2520 #define RVCSR_MHPMCOUNTER22H_BITS _u(0xffffffff) 2521 #define RVCSR_MHPMCOUNTER22H_RESET _u(0x00000000) 2522 #define RVCSR_MHPMCOUNTER22H_MSB _u(31) 2523 #define RVCSR_MHPMCOUNTER22H_LSB _u(0) 2524 #define RVCSR_MHPMCOUNTER22H_ACCESS "RO" 2525 // ============================================================================= 2526 // Register : RVCSR_MHPMCOUNTER23H 2527 // Description : Extended performance counter, hardwired to 0. 2528 #define RVCSR_MHPMCOUNTER23H_OFFSET _u(0x00000b97) 2529 #define RVCSR_MHPMCOUNTER23H_BITS _u(0xffffffff) 2530 #define RVCSR_MHPMCOUNTER23H_RESET _u(0x00000000) 2531 #define RVCSR_MHPMCOUNTER23H_MSB _u(31) 2532 #define RVCSR_MHPMCOUNTER23H_LSB _u(0) 2533 #define RVCSR_MHPMCOUNTER23H_ACCESS "RO" 2534 // ============================================================================= 2535 // Register : RVCSR_MHPMCOUNTER24H 2536 // Description : Extended performance counter, hardwired to 0. 2537 #define RVCSR_MHPMCOUNTER24H_OFFSET _u(0x00000b98) 2538 #define RVCSR_MHPMCOUNTER24H_BITS _u(0xffffffff) 2539 #define RVCSR_MHPMCOUNTER24H_RESET _u(0x00000000) 2540 #define RVCSR_MHPMCOUNTER24H_MSB _u(31) 2541 #define RVCSR_MHPMCOUNTER24H_LSB _u(0) 2542 #define RVCSR_MHPMCOUNTER24H_ACCESS "RO" 2543 // ============================================================================= 2544 // Register : RVCSR_MHPMCOUNTER25H 2545 // Description : Extended performance counter, hardwired to 0. 2546 #define RVCSR_MHPMCOUNTER25H_OFFSET _u(0x00000b99) 2547 #define RVCSR_MHPMCOUNTER25H_BITS _u(0xffffffff) 2548 #define RVCSR_MHPMCOUNTER25H_RESET _u(0x00000000) 2549 #define RVCSR_MHPMCOUNTER25H_MSB _u(31) 2550 #define RVCSR_MHPMCOUNTER25H_LSB _u(0) 2551 #define RVCSR_MHPMCOUNTER25H_ACCESS "RO" 2552 // ============================================================================= 2553 // Register : RVCSR_MHPMCOUNTER26H 2554 // Description : Extended performance counter, hardwired to 0. 2555 #define RVCSR_MHPMCOUNTER26H_OFFSET _u(0x00000b9a) 2556 #define RVCSR_MHPMCOUNTER26H_BITS _u(0xffffffff) 2557 #define RVCSR_MHPMCOUNTER26H_RESET _u(0x00000000) 2558 #define RVCSR_MHPMCOUNTER26H_MSB _u(31) 2559 #define RVCSR_MHPMCOUNTER26H_LSB _u(0) 2560 #define RVCSR_MHPMCOUNTER26H_ACCESS "RO" 2561 // ============================================================================= 2562 // Register : RVCSR_MHPMCOUNTER27H 2563 // Description : Extended performance counter, hardwired to 0. 2564 #define RVCSR_MHPMCOUNTER27H_OFFSET _u(0x00000b9b) 2565 #define RVCSR_MHPMCOUNTER27H_BITS _u(0xffffffff) 2566 #define RVCSR_MHPMCOUNTER27H_RESET _u(0x00000000) 2567 #define RVCSR_MHPMCOUNTER27H_MSB _u(31) 2568 #define RVCSR_MHPMCOUNTER27H_LSB _u(0) 2569 #define RVCSR_MHPMCOUNTER27H_ACCESS "RO" 2570 // ============================================================================= 2571 // Register : RVCSR_MHPMCOUNTER28H 2572 // Description : Extended performance counter, hardwired to 0. 2573 #define RVCSR_MHPMCOUNTER28H_OFFSET _u(0x00000b9c) 2574 #define RVCSR_MHPMCOUNTER28H_BITS _u(0xffffffff) 2575 #define RVCSR_MHPMCOUNTER28H_RESET _u(0x00000000) 2576 #define RVCSR_MHPMCOUNTER28H_MSB _u(31) 2577 #define RVCSR_MHPMCOUNTER28H_LSB _u(0) 2578 #define RVCSR_MHPMCOUNTER28H_ACCESS "RO" 2579 // ============================================================================= 2580 // Register : RVCSR_MHPMCOUNTER29H 2581 // Description : Extended performance counter, hardwired to 0. 2582 #define RVCSR_MHPMCOUNTER29H_OFFSET _u(0x00000b9d) 2583 #define RVCSR_MHPMCOUNTER29H_BITS _u(0xffffffff) 2584 #define RVCSR_MHPMCOUNTER29H_RESET _u(0x00000000) 2585 #define RVCSR_MHPMCOUNTER29H_MSB _u(31) 2586 #define RVCSR_MHPMCOUNTER29H_LSB _u(0) 2587 #define RVCSR_MHPMCOUNTER29H_ACCESS "RO" 2588 // ============================================================================= 2589 // Register : RVCSR_MHPMCOUNTER30H 2590 // Description : Extended performance counter, hardwired to 0. 2591 #define RVCSR_MHPMCOUNTER30H_OFFSET _u(0x00000b9e) 2592 #define RVCSR_MHPMCOUNTER30H_BITS _u(0xffffffff) 2593 #define RVCSR_MHPMCOUNTER30H_RESET _u(0x00000000) 2594 #define RVCSR_MHPMCOUNTER30H_MSB _u(31) 2595 #define RVCSR_MHPMCOUNTER30H_LSB _u(0) 2596 #define RVCSR_MHPMCOUNTER30H_ACCESS "RO" 2597 // ============================================================================= 2598 // Register : RVCSR_MHPMCOUNTER31H 2599 // Description : Extended performance counter, hardwired to 0. 2600 #define RVCSR_MHPMCOUNTER31H_OFFSET _u(0x00000b9f) 2601 #define RVCSR_MHPMCOUNTER31H_BITS _u(0xffffffff) 2602 #define RVCSR_MHPMCOUNTER31H_RESET _u(0x00000000) 2603 #define RVCSR_MHPMCOUNTER31H_MSB _u(31) 2604 #define RVCSR_MHPMCOUNTER31H_LSB _u(0) 2605 #define RVCSR_MHPMCOUNTER31H_ACCESS "RO" 2606 // ============================================================================= 2607 // Register : RVCSR_PMPCFGM0 2608 // Description : PMP M-mode configuration. One bit per PMP region. Setting a bit 2609 // makes the corresponding region apply to M-mode (like the 2610 // `pmpcfg.L` bit) but does not lock the region. 2611 // 2612 // PMP is useful for non-security-related purposes, such as stack 2613 // guarding and peripheral emulation. This extension allows M-mode 2614 // to freely use any currently unlocked regions for its own 2615 // purposes, without the inconvenience of having to lock them. 2616 // 2617 // Note that this does not grant any new capabilities to M-mode, 2618 // since in the base standard it is already possible to apply 2619 // unlocked regions to M-mode by locking them. In general, PMP 2620 // regions should be locked in ascending region number order so 2621 // they can't be subsequently overridden by currently unlocked 2622 // regions. 2623 // 2624 // Note also that this is not the same as the rule locking bypass 2625 // bit in the ePMP extension, which does not permit locked and 2626 // unlocked M-mode regions to coexist. 2627 // 2628 // This is a Hazard3 custom CSR. 2629 #define RVCSR_PMPCFGM0_OFFSET _u(0x00000bd0) 2630 #define RVCSR_PMPCFGM0_BITS _u(0x0000ffff) 2631 #define RVCSR_PMPCFGM0_RESET _u(0x00000000) 2632 #define RVCSR_PMPCFGM0_MSB _u(15) 2633 #define RVCSR_PMPCFGM0_LSB _u(0) 2634 #define RVCSR_PMPCFGM0_ACCESS "RW" 2635 // ============================================================================= 2636 // Register : RVCSR_MEIEA 2637 // Description : External interrupt enable array. 2638 // 2639 // The array contains a read-write bit for each external interrupt 2640 // request: a `1` bit indicates that interrupt is currently 2641 // enabled. At reset, all external interrupts are disabled. 2642 // 2643 // If enabled, an external interrupt can cause assertion of the 2644 // standard RISC-V machine external interrupt pending flag 2645 // (`mip.meip`), and therefore cause the processor to enter the 2646 // external interrupt vector. See `meipa`. 2647 // 2648 // There are up to 512 external interrupts. The upper half of this 2649 // register contains a 16-bit window into the full 512-bit vector. 2650 // The window is indexed by the 5 LSBs of the write data. 2651 #define RVCSR_MEIEA_OFFSET _u(0x00000be0) 2652 #define RVCSR_MEIEA_BITS _u(0xffff001f) 2653 #define RVCSR_MEIEA_RESET _u(0x00000000) 2654 // ----------------------------------------------------------------------------- 2655 // Field : RVCSR_MEIEA_WINDOW 2656 // Description : 16-bit read/write window into the external interrupt enable 2657 // array 2658 #define RVCSR_MEIEA_WINDOW_RESET _u(0x0000) 2659 #define RVCSR_MEIEA_WINDOW_BITS _u(0xffff0000) 2660 #define RVCSR_MEIEA_WINDOW_MSB _u(31) 2661 #define RVCSR_MEIEA_WINDOW_LSB _u(16) 2662 #define RVCSR_MEIEA_WINDOW_ACCESS "RW" 2663 // ----------------------------------------------------------------------------- 2664 // Field : RVCSR_MEIEA_INDEX 2665 // Description : Write-only self-clearing field (no value is stored) used to 2666 // control which window of the array appears in `window`. 2667 #define RVCSR_MEIEA_INDEX_RESET _u(0x00) 2668 #define RVCSR_MEIEA_INDEX_BITS _u(0x0000001f) 2669 #define RVCSR_MEIEA_INDEX_MSB _u(4) 2670 #define RVCSR_MEIEA_INDEX_LSB _u(0) 2671 #define RVCSR_MEIEA_INDEX_ACCESS "WO" 2672 // ============================================================================= 2673 // Register : RVCSR_MEIPA 2674 // Description : External interrupt pending array 2675 // 2676 // Contains a read-only bit for each external interrupt request. 2677 // Similarly to `meiea`, this register is a window into an array 2678 // of up to 512 external interrupt flags. The status appears in 2679 // the upper 16 bits of the value read from `meipa`, and the lower 2680 // 5 bits of the value _written_ by the same CSR instruction (or 0 2681 // if no write takes place) select a 16-bit window of the full 2682 // interrupt pending array. 2683 // 2684 // A `1` bit indicates that interrupt is currently asserted. IRQs 2685 // are assumed to be level-sensitive, and the relevant `meipa` bit 2686 // is cleared by servicing the requestor so that it deasserts its 2687 // interrupt request. 2688 // 2689 // When any interrupt of sufficient priority is both set in 2690 // `meipa` and enabled in `meiea`, the standard RISC-V external 2691 // interrupt pending bit `mip.meip` is asserted. In other words, 2692 // `meipa` is filtered by `meiea` to generate the standard 2693 // `mip.meip` flag. 2694 #define RVCSR_MEIPA_OFFSET _u(0x00000be1) 2695 #define RVCSR_MEIPA_BITS _u(0xffff001f) 2696 #define RVCSR_MEIPA_RESET _u(0x00000000) 2697 // ----------------------------------------------------------------------------- 2698 // Field : RVCSR_MEIPA_WINDOW 2699 // Description : 16-bit read-only window into the external interrupt pending 2700 // array 2701 #define RVCSR_MEIPA_WINDOW_RESET "-" 2702 #define RVCSR_MEIPA_WINDOW_BITS _u(0xffff0000) 2703 #define RVCSR_MEIPA_WINDOW_MSB _u(31) 2704 #define RVCSR_MEIPA_WINDOW_LSB _u(16) 2705 #define RVCSR_MEIPA_WINDOW_ACCESS "RO" 2706 // ----------------------------------------------------------------------------- 2707 // Field : RVCSR_MEIPA_INDEX 2708 // Description : Write-only, self-clearing field (no value is stored) used to 2709 // control which window of the array appears in `window`. 2710 #define RVCSR_MEIPA_INDEX_RESET _u(0x00) 2711 #define RVCSR_MEIPA_INDEX_BITS _u(0x0000001f) 2712 #define RVCSR_MEIPA_INDEX_MSB _u(4) 2713 #define RVCSR_MEIPA_INDEX_LSB _u(0) 2714 #define RVCSR_MEIPA_INDEX_ACCESS "WO" 2715 // ============================================================================= 2716 // Register : RVCSR_MEIFA 2717 // Description : External interrupt force array 2718 // 2719 // Contains a read-write bit for every interrupt request. Writing 2720 // a 1 to a bit in the interrupt force array causes the 2721 // corresponding bit to become pending in `meipa`. Software can 2722 // use this feature to manually trigger a particular interrupt. 2723 // 2724 // There are no restrictions on using `meifa` inside of an 2725 // interrupt. The more useful case here is to schedule some lower- 2726 // priority handler from within a high-priority interrupt, so that 2727 // it will execute before the core returns to the foreground code. 2728 // Implementers may wish to reserve some external IRQs with their 2729 // external inputs tied to 0 for this purpose. 2730 // 2731 // Bits can be cleared by software, and are cleared automatically 2732 // by hardware upon a read of `meinext` which returns the 2733 // corresponding IRQ number in `meinext.irq` with `mienext.noirq` 2734 // clear (no matter whether `meinext.update` is written). 2735 // 2736 // `meifa` implements the same array window indexing scheme as 2737 // `meiea` and `meipa`. 2738 #define RVCSR_MEIFA_OFFSET _u(0x00000be2) 2739 #define RVCSR_MEIFA_BITS _u(0xffff001f) 2740 #define RVCSR_MEIFA_RESET _u(0x00000000) 2741 // ----------------------------------------------------------------------------- 2742 // Field : RVCSR_MEIFA_WINDOW 2743 // Description : 16-bit read/write window into the external interrupt force 2744 // array 2745 #define RVCSR_MEIFA_WINDOW_RESET _u(0x0000) 2746 #define RVCSR_MEIFA_WINDOW_BITS _u(0xffff0000) 2747 #define RVCSR_MEIFA_WINDOW_MSB _u(31) 2748 #define RVCSR_MEIFA_WINDOW_LSB _u(16) 2749 #define RVCSR_MEIFA_WINDOW_ACCESS "RW" 2750 // ----------------------------------------------------------------------------- 2751 // Field : RVCSR_MEIFA_INDEX 2752 // Description : Write-only, self-clearing field (no value is stored) used to 2753 // control which window of the array appears in `window`. 2754 #define RVCSR_MEIFA_INDEX_RESET _u(0x00) 2755 #define RVCSR_MEIFA_INDEX_BITS _u(0x0000001f) 2756 #define RVCSR_MEIFA_INDEX_MSB _u(4) 2757 #define RVCSR_MEIFA_INDEX_LSB _u(0) 2758 #define RVCSR_MEIFA_INDEX_ACCESS "WO" 2759 // ============================================================================= 2760 // Register : RVCSR_MEIPRA 2761 // Description : External interrupt priority array 2762 // 2763 // Each interrupt has an (up to) 4-bit priority value associated 2764 // with it, and each access to this register reads and/or writes a 2765 // 16-bit window containing four such priority values. When less 2766 // than 16 priority levels are available, the LSBs of the priority 2767 // fields are hardwired to 0. 2768 // 2769 // When an interrupt's priority is lower than the current 2770 // preemption priority `meicontext.preempt`, it is treated as not 2771 // being pending for the purposes of `mip.meip`. The pending bit 2772 // in `meipa` will still assert, but the machine external 2773 // interrupt pending bit `mip.meip` will not, so the processor 2774 // will ignore this interrupt. See `meicontext`. 2775 #define RVCSR_MEIPRA_OFFSET _u(0x00000be3) 2776 #define RVCSR_MEIPRA_BITS _u(0xffff001f) 2777 #define RVCSR_MEIPRA_RESET _u(0x00000000) 2778 // ----------------------------------------------------------------------------- 2779 // Field : RVCSR_MEIPRA_WINDOW 2780 // Description : 16-bit read/write window into the external interrupt priority 2781 // array, containing four 4-bit priority values. 2782 #define RVCSR_MEIPRA_WINDOW_RESET _u(0x0000) 2783 #define RVCSR_MEIPRA_WINDOW_BITS _u(0xffff0000) 2784 #define RVCSR_MEIPRA_WINDOW_MSB _u(31) 2785 #define RVCSR_MEIPRA_WINDOW_LSB _u(16) 2786 #define RVCSR_MEIPRA_WINDOW_ACCESS "RW" 2787 // ----------------------------------------------------------------------------- 2788 // Field : RVCSR_MEIPRA_INDEX 2789 // Description : Write-only, self-clearing field (no value is stored) used to 2790 // control which window of the array appears in `window`. 2791 #define RVCSR_MEIPRA_INDEX_RESET _u(0x00) 2792 #define RVCSR_MEIPRA_INDEX_BITS _u(0x0000001f) 2793 #define RVCSR_MEIPRA_INDEX_MSB _u(4) 2794 #define RVCSR_MEIPRA_INDEX_LSB _u(0) 2795 #define RVCSR_MEIPRA_INDEX_ACCESS "WO" 2796 // ============================================================================= 2797 // Register : RVCSR_MEINEXT 2798 // Description : Get next external interrupt 2799 // 2800 // Contains the index of the highest-priority external interrupt 2801 // which is both asserted in `meipa` and enabled in `meiea`, left- 2802 // shifted by 2 so that it can be used to index an array of 32-bit 2803 // function pointers. If there is no such interrupt, the MSB is 2804 // set. 2805 // 2806 // When multiple interrupts of the same priority are both pending 2807 // and enabled, the lowest-numbered wins. Interrupts with priority 2808 // less than `meicontext.ppreempt` -- the _previous_ preemption 2809 // priority -- are treated as though they are not pending. This is 2810 // to ensure that a preempting interrupt frame does not service 2811 // interrupts which may be in progress in the frame that was 2812 // preempted. 2813 #define RVCSR_MEINEXT_OFFSET _u(0x00000be4) 2814 #define RVCSR_MEINEXT_BITS _u(0x800007fd) 2815 #define RVCSR_MEINEXT_RESET _u(0x00000000) 2816 // ----------------------------------------------------------------------------- 2817 // Field : RVCSR_MEINEXT_NOIRQ 2818 // Description : Set when there is no external interrupt which is enabled, 2819 // pending, and has priority greater than or equal to 2820 // `meicontext.ppreempt`. Can be efficiently tested with a `bltz` 2821 // or `bgez` instruction. 2822 #define RVCSR_MEINEXT_NOIRQ_RESET _u(0x0) 2823 #define RVCSR_MEINEXT_NOIRQ_BITS _u(0x80000000) 2824 #define RVCSR_MEINEXT_NOIRQ_MSB _u(31) 2825 #define RVCSR_MEINEXT_NOIRQ_LSB _u(31) 2826 #define RVCSR_MEINEXT_NOIRQ_ACCESS "RO" 2827 // ----------------------------------------------------------------------------- 2828 // Field : RVCSR_MEINEXT_IRQ 2829 // Description : Index of the highest-priority active external interrupt. Zero 2830 // when no external interrupts with sufficient priority are both 2831 // pending and enabled. 2832 #define RVCSR_MEINEXT_IRQ_RESET _u(0x000) 2833 #define RVCSR_MEINEXT_IRQ_BITS _u(0x000007fc) 2834 #define RVCSR_MEINEXT_IRQ_MSB _u(10) 2835 #define RVCSR_MEINEXT_IRQ_LSB _u(2) 2836 #define RVCSR_MEINEXT_IRQ_ACCESS "RO" 2837 // ----------------------------------------------------------------------------- 2838 // Field : RVCSR_MEINEXT_UPDATE 2839 // Description : Writing 1 (self-clearing) causes hardware to update 2840 // `meicontext` according to the IRQ number and preemption 2841 // priority of the interrupt indicated in `noirq`/`irq`. This 2842 // should be done in a single atomic operation, i.e. `csrrsi a0, 2843 // meinext, 0x1`. 2844 #define RVCSR_MEINEXT_UPDATE_RESET _u(0x0) 2845 #define RVCSR_MEINEXT_UPDATE_BITS _u(0x00000001) 2846 #define RVCSR_MEINEXT_UPDATE_MSB _u(0) 2847 #define RVCSR_MEINEXT_UPDATE_LSB _u(0) 2848 #define RVCSR_MEINEXT_UPDATE_ACCESS "SC" 2849 // ============================================================================= 2850 // Register : RVCSR_MEICONTEXT 2851 // Description : External interrupt context register 2852 // 2853 // Configures the priority level for interrupt preemption, and 2854 // helps software track which interrupt it is currently in. The 2855 // latter is useful when a common interrupt service routine 2856 // handles interrupt requests from multiple instances of the same 2857 // peripheral. 2858 // 2859 // A three-level stack of preemption priorities is maintained in 2860 // the `preempt`, `ppreempt` and `pppreempt` fields. The priority 2861 // stack is saved when hardware enters the external interrupt 2862 // vector, and restored by an `mret` instruction if 2863 // `meicontext.mreteirq` is set. 2864 // 2865 // The top entry of the priority stack, `preempt`, is used by 2866 // hardware to ensure that only higher-priority interrupts can 2867 // preempt the current interrupt. The next entry, `ppreempt`, is 2868 // used to avoid servicing interrupts which may already be in 2869 // progress in a frame that was preempted. The third entry, 2870 // `pppreempt`, has no hardware effect, but ensures that `preempt` 2871 // and `ppreempt` can be correctly saved/restored across arbitrary 2872 // levels of preemption. 2873 #define RVCSR_MEICONTEXT_OFFSET _u(0x00000be5) 2874 #define RVCSR_MEICONTEXT_BITS _u(0xff1f9fff) 2875 #define RVCSR_MEICONTEXT_RESET _u(0x00008000) 2876 // ----------------------------------------------------------------------------- 2877 // Field : RVCSR_MEICONTEXT_PPPREEMPT 2878 // Description : Previous `ppreempt`. Set to `ppreempt` on priority save, set to 2879 // zero on priority restore. Has no hardware effect, but ensures 2880 // that when `meicontext` is saved/restored correctly, `preempt` 2881 // and `ppreempt` stack correctly through arbitrarily many 2882 // preemption frames. 2883 #define RVCSR_MEICONTEXT_PPPREEMPT_RESET _u(0x0) 2884 #define RVCSR_MEICONTEXT_PPPREEMPT_BITS _u(0xf0000000) 2885 #define RVCSR_MEICONTEXT_PPPREEMPT_MSB _u(31) 2886 #define RVCSR_MEICONTEXT_PPPREEMPT_LSB _u(28) 2887 #define RVCSR_MEICONTEXT_PPPREEMPT_ACCESS "RW" 2888 // ----------------------------------------------------------------------------- 2889 // Field : RVCSR_MEICONTEXT_PPREEMPT 2890 // Description : Previous `preempt`. Set to `preempt` on priority save, restored 2891 // to to `pppreempt` on priority restore. 2892 // 2893 // IRQs of lower priority than `ppreempt` are not visible in 2894 // `meinext`, so that a preemptee is not re-taken in the 2895 // preempting frame. 2896 #define RVCSR_MEICONTEXT_PPREEMPT_RESET _u(0x0) 2897 #define RVCSR_MEICONTEXT_PPREEMPT_BITS _u(0x0f000000) 2898 #define RVCSR_MEICONTEXT_PPREEMPT_MSB _u(27) 2899 #define RVCSR_MEICONTEXT_PPREEMPT_LSB _u(24) 2900 #define RVCSR_MEICONTEXT_PPREEMPT_ACCESS "RW" 2901 // ----------------------------------------------------------------------------- 2902 // Field : RVCSR_MEICONTEXT_PREEMPT 2903 // Description : Minimum interrupt priority to preempt the current interrupt. 2904 // Interrupts with lower priority than `preempt` do not cause the 2905 // core to transfer to an interrupt handler. Updated by hardware 2906 // when when `meinext.update` is written, or when hardware enters 2907 // the external interrupt vector. 2908 // 2909 // If an interrupt is present in `meinext` when this field is 2910 // updated, then `preempt` is set to one level greater than that 2911 // interrupt's priority. Otherwise, `ppreempt` is set to one level 2912 // greater than the maximum interrupt priority, disabling 2913 // preemption. 2914 #define RVCSR_MEICONTEXT_PREEMPT_RESET _u(0x00) 2915 #define RVCSR_MEICONTEXT_PREEMPT_BITS _u(0x001f0000) 2916 #define RVCSR_MEICONTEXT_PREEMPT_MSB _u(20) 2917 #define RVCSR_MEICONTEXT_PREEMPT_LSB _u(16) 2918 #define RVCSR_MEICONTEXT_PREEMPT_ACCESS "RW" 2919 // ----------------------------------------------------------------------------- 2920 // Field : RVCSR_MEICONTEXT_NOIRQ 2921 // Description : Not in interrupt (read/write). Set to 1 at reset. Set to 2922 // `meinext.noirq` when `meinext.update` is written. No hardware 2923 // effect. 2924 #define RVCSR_MEICONTEXT_NOIRQ_RESET _u(0x1) 2925 #define RVCSR_MEICONTEXT_NOIRQ_BITS _u(0x00008000) 2926 #define RVCSR_MEICONTEXT_NOIRQ_MSB _u(15) 2927 #define RVCSR_MEICONTEXT_NOIRQ_LSB _u(15) 2928 #define RVCSR_MEICONTEXT_NOIRQ_ACCESS "RW" 2929 // ----------------------------------------------------------------------------- 2930 // Field : RVCSR_MEICONTEXT_IRQ 2931 // Description : Current IRQ number (read/write). Set to `meinext.irq` when 2932 // `meinext.update` is written. No hardware effect. 2933 #define RVCSR_MEICONTEXT_IRQ_RESET _u(0x000) 2934 #define RVCSR_MEICONTEXT_IRQ_BITS _u(0x00001ff0) 2935 #define RVCSR_MEICONTEXT_IRQ_MSB _u(12) 2936 #define RVCSR_MEICONTEXT_IRQ_LSB _u(4) 2937 #define RVCSR_MEICONTEXT_IRQ_ACCESS "RW" 2938 // ----------------------------------------------------------------------------- 2939 // Field : RVCSR_MEICONTEXT_MTIESAVE 2940 // Description : Reads as the current value of `mie.mtie`, if `clearts` is set 2941 // by the same CSR access instruction. Otherwise reads as 0. 2942 // Writes are ORed into `mie.mtie`. 2943 #define RVCSR_MEICONTEXT_MTIESAVE_RESET _u(0x0) 2944 #define RVCSR_MEICONTEXT_MTIESAVE_BITS _u(0x00000008) 2945 #define RVCSR_MEICONTEXT_MTIESAVE_MSB _u(3) 2946 #define RVCSR_MEICONTEXT_MTIESAVE_LSB _u(3) 2947 #define RVCSR_MEICONTEXT_MTIESAVE_ACCESS "RO" 2948 // ----------------------------------------------------------------------------- 2949 // Field : RVCSR_MEICONTEXT_MSIESAVE 2950 // Description : Reads as the current value of `mie.msie`, if `clearts` is set 2951 // by the same CSR access instruction. Otherwise reads as 0. 2952 // Writes are ORed into `mie.msie`. 2953 #define RVCSR_MEICONTEXT_MSIESAVE_RESET _u(0x0) 2954 #define RVCSR_MEICONTEXT_MSIESAVE_BITS _u(0x00000004) 2955 #define RVCSR_MEICONTEXT_MSIESAVE_MSB _u(2) 2956 #define RVCSR_MEICONTEXT_MSIESAVE_LSB _u(2) 2957 #define RVCSR_MEICONTEXT_MSIESAVE_ACCESS "RO" 2958 // ----------------------------------------------------------------------------- 2959 // Field : RVCSR_MEICONTEXT_CLEARTS 2960 // Description : Write-1 self-clearing field. Writing 1 will clear `mie.mtie` 2961 // and `mie.msie`, and present their prior values in the 2962 // `mtiesave` and `msiesave` of this register. This makes it safe 2963 // to re-enable IRQs (via `mstatus.mie`) without the possibility 2964 // of being preempted by the standard timer and soft interrupt 2965 // handlers, which may not be aware of Hazard3's interrupt 2966 // hardware. 2967 // 2968 // The clear due to `clearts` takes precedence over the set due to 2969 // `mtiesave`/`msiesave`, although it would be unusual for 2970 // software to write both on the same cycle. 2971 #define RVCSR_MEICONTEXT_CLEARTS_RESET _u(0x0) 2972 #define RVCSR_MEICONTEXT_CLEARTS_BITS _u(0x00000002) 2973 #define RVCSR_MEICONTEXT_CLEARTS_MSB _u(1) 2974 #define RVCSR_MEICONTEXT_CLEARTS_LSB _u(1) 2975 #define RVCSR_MEICONTEXT_CLEARTS_ACCESS "SC" 2976 // ----------------------------------------------------------------------------- 2977 // Field : RVCSR_MEICONTEXT_MRETEIRQ 2978 // Description : If 1, enable restore of the preemption priority stack on 2979 // `mret`. This bit is set on entering the external interrupt 2980 // vector, cleared by `mret`, and cleared upon taking any trap 2981 // other than an external interrupt. 2982 // 2983 // Provided `meicontext` is saved on entry to the external 2984 // interrupt vector (before enabling preemption), is restored 2985 // before exiting, and the standard software/timer IRQs are 2986 // prevented from preempting (e.g. by using `clearts`), this flag 2987 // allows the hardware to safely manage the preemption priority 2988 // stack even when an external interrupt handler may take 2989 // exceptions. 2990 #define RVCSR_MEICONTEXT_MRETEIRQ_RESET _u(0x0) 2991 #define RVCSR_MEICONTEXT_MRETEIRQ_BITS _u(0x00000001) 2992 #define RVCSR_MEICONTEXT_MRETEIRQ_MSB _u(0) 2993 #define RVCSR_MEICONTEXT_MRETEIRQ_LSB _u(0) 2994 #define RVCSR_MEICONTEXT_MRETEIRQ_ACCESS "RW" 2995 // ============================================================================= 2996 // Register : RVCSR_MSLEEP 2997 // Description : M-mode sleep control register 2998 #define RVCSR_MSLEEP_OFFSET _u(0x00000bf0) 2999 #define RVCSR_MSLEEP_BITS _u(0x00000007) 3000 #define RVCSR_MSLEEP_RESET _u(0x00000000) 3001 // ----------------------------------------------------------------------------- 3002 // Field : RVCSR_MSLEEP_SLEEPONBLOCK 3003 // Description : Enter the deep sleep state configured by 3004 // msleep.deepsleep/msleep.powerdown on a `h3.block` instruction, 3005 // as well as a standard `wfi`. If this bit is clear, a `h3.block` 3006 // is always implemented as a simple pipeline stall. 3007 #define RVCSR_MSLEEP_SLEEPONBLOCK_RESET _u(0x0) 3008 #define RVCSR_MSLEEP_SLEEPONBLOCK_BITS _u(0x00000004) 3009 #define RVCSR_MSLEEP_SLEEPONBLOCK_MSB _u(2) 3010 #define RVCSR_MSLEEP_SLEEPONBLOCK_LSB _u(2) 3011 #define RVCSR_MSLEEP_SLEEPONBLOCK_ACCESS "RW" 3012 // ----------------------------------------------------------------------------- 3013 // Field : RVCSR_MSLEEP_POWERDOWN 3014 // Description : Release the external power request when going to sleep. The 3015 // function of this is platform-defined -- it may do nothing, it 3016 // may do something simple like clock-gating the fabric, or it may 3017 // be tied to some complex system-level power controller. 3018 // 3019 // When waking, the processor reasserts its external power-up 3020 // request, and will not fetch any instructions until the request 3021 // is acknowledged. This may add considerable latency to the 3022 // wakeup. 3023 #define RVCSR_MSLEEP_POWERDOWN_RESET _u(0x0) 3024 #define RVCSR_MSLEEP_POWERDOWN_BITS _u(0x00000002) 3025 #define RVCSR_MSLEEP_POWERDOWN_MSB _u(1) 3026 #define RVCSR_MSLEEP_POWERDOWN_LSB _u(1) 3027 #define RVCSR_MSLEEP_POWERDOWN_ACCESS "RW" 3028 // ----------------------------------------------------------------------------- 3029 // Field : RVCSR_MSLEEP_DEEPSLEEP 3030 // Description : Deassert the processor clock enable when entering the sleep 3031 // state. If a clock gate is instantiated, this allows most of the 3032 // processor (everything except the power state machine and the 3033 // interrupt and halt input registers) to be clock gated whilst 3034 // asleep, which may reduce the sleep current. This adds one cycle 3035 // to the wakeup latency. 3036 #define RVCSR_MSLEEP_DEEPSLEEP_RESET _u(0x0) 3037 #define RVCSR_MSLEEP_DEEPSLEEP_BITS _u(0x00000001) 3038 #define RVCSR_MSLEEP_DEEPSLEEP_MSB _u(0) 3039 #define RVCSR_MSLEEP_DEEPSLEEP_LSB _u(0) 3040 #define RVCSR_MSLEEP_DEEPSLEEP_ACCESS "RW" 3041 // ============================================================================= 3042 // Register : RVCSR_DMDATA0 3043 // Description : The Debug Module's DATA0 register is mapped into Hazard3's CSR 3044 // space so that the Debug Module can exchange data with the core 3045 // by executing CSR access instructions (this is used to implement 3046 // the Abstract Access Register command). Only accessible in Debug 3047 // Mode. 3048 #define RVCSR_DMDATA0_OFFSET _u(0x00000bff) 3049 #define RVCSR_DMDATA0_BITS _u(0xffffffff) 3050 #define RVCSR_DMDATA0_RESET _u(0x00000000) 3051 #define RVCSR_DMDATA0_MSB _u(31) 3052 #define RVCSR_DMDATA0_LSB _u(0) 3053 #define RVCSR_DMDATA0_ACCESS "RW" 3054 // ============================================================================= 3055 // Register : RVCSR_CYCLE 3056 // Description : Read-only U-mode alias of mcycle, accessible when 3057 // `mcounteren.cy` is set 3058 #define RVCSR_CYCLE_OFFSET _u(0x00000c00) 3059 #define RVCSR_CYCLE_BITS _u(0xffffffff) 3060 #define RVCSR_CYCLE_RESET _u(0x00000000) 3061 #define RVCSR_CYCLE_MSB _u(31) 3062 #define RVCSR_CYCLE_LSB _u(0) 3063 #define RVCSR_CYCLE_ACCESS "RO" 3064 // ============================================================================= 3065 // Register : RVCSR_INSTRET 3066 // Description : Read-only U-mode alias of minstret, accessible when 3067 // `mcounteren.ir` is set 3068 #define RVCSR_INSTRET_OFFSET _u(0x00000c02) 3069 #define RVCSR_INSTRET_BITS _u(0xffffffff) 3070 #define RVCSR_INSTRET_RESET _u(0x00000000) 3071 #define RVCSR_INSTRET_MSB _u(31) 3072 #define RVCSR_INSTRET_LSB _u(0) 3073 #define RVCSR_INSTRET_ACCESS "RO" 3074 // ============================================================================= 3075 // Register : RVCSR_CYCLEH 3076 // Description : Read-only U-mode alias of mcycleh, accessible when 3077 // `mcounteren.cy` is set 3078 #define RVCSR_CYCLEH_OFFSET _u(0x00000c80) 3079 #define RVCSR_CYCLEH_BITS _u(0xffffffff) 3080 #define RVCSR_CYCLEH_RESET _u(0x00000000) 3081 #define RVCSR_CYCLEH_MSB _u(31) 3082 #define RVCSR_CYCLEH_LSB _u(0) 3083 #define RVCSR_CYCLEH_ACCESS "RO" 3084 // ============================================================================= 3085 // Register : RVCSR_INSTRETH 3086 // Description : Read-only U-mode alias of minstreth, accessible when 3087 // `mcounteren.ir` is set 3088 #define RVCSR_INSTRETH_OFFSET _u(0x00000c82) 3089 #define RVCSR_INSTRETH_BITS _u(0xffffffff) 3090 #define RVCSR_INSTRETH_RESET _u(0x00000000) 3091 #define RVCSR_INSTRETH_MSB _u(31) 3092 #define RVCSR_INSTRETH_LSB _u(0) 3093 #define RVCSR_INSTRETH_ACCESS "RO" 3094 // ============================================================================= 3095 // Register : RVCSR_MVENDORID 3096 // Description : Vendor ID 3097 #define RVCSR_MVENDORID_OFFSET _u(0x00000f11) 3098 #define RVCSR_MVENDORID_BITS _u(0xffffffff) 3099 #define RVCSR_MVENDORID_RESET _u(0x00000000) 3100 // ----------------------------------------------------------------------------- 3101 // Field : RVCSR_MVENDORID_BANK 3102 #define RVCSR_MVENDORID_BANK_RESET "-" 3103 #define RVCSR_MVENDORID_BANK_BITS _u(0xffffff80) 3104 #define RVCSR_MVENDORID_BANK_MSB _u(31) 3105 #define RVCSR_MVENDORID_BANK_LSB _u(7) 3106 #define RVCSR_MVENDORID_BANK_ACCESS "RO" 3107 // ----------------------------------------------------------------------------- 3108 // Field : RVCSR_MVENDORID_OFFSET 3109 #define RVCSR_MVENDORID_OFFSET_RESET "-" 3110 #define RVCSR_MVENDORID_OFFSET_BITS _u(0x0000007f) 3111 #define RVCSR_MVENDORID_OFFSET_MSB _u(6) 3112 #define RVCSR_MVENDORID_OFFSET_LSB _u(0) 3113 #define RVCSR_MVENDORID_OFFSET_ACCESS "RO" 3114 // ============================================================================= 3115 // Register : RVCSR_MARCHID 3116 // Description : Architecture ID (Hazard3) 3117 #define RVCSR_MARCHID_OFFSET _u(0x00000f12) 3118 #define RVCSR_MARCHID_BITS _u(0xffffffff) 3119 #define RVCSR_MARCHID_RESET _u(0x0000001b) 3120 #define RVCSR_MARCHID_MSB _u(31) 3121 #define RVCSR_MARCHID_LSB _u(0) 3122 #define RVCSR_MARCHID_ACCESS "RO" 3123 // ============================================================================= 3124 // Register : RVCSR_MIMPID 3125 // Description : Implementation ID 3126 #define RVCSR_MIMPID_OFFSET _u(0x00000f13) 3127 #define RVCSR_MIMPID_BITS _u(0xffffffff) 3128 #define RVCSR_MIMPID_RESET "-" 3129 #define RVCSR_MIMPID_MSB _u(31) 3130 #define RVCSR_MIMPID_LSB _u(0) 3131 #define RVCSR_MIMPID_ACCESS "RO" 3132 // ============================================================================= 3133 // Register : RVCSR_MHARTID 3134 // Description : Hardware thread ID 3135 // On RP2350, core 0 has a hart ID of 0, and core 1 has a hart ID 3136 // of 1. 3137 #define RVCSR_MHARTID_OFFSET _u(0x00000f14) 3138 #define RVCSR_MHARTID_BITS _u(0xffffffff) 3139 #define RVCSR_MHARTID_RESET "-" 3140 #define RVCSR_MHARTID_MSB _u(31) 3141 #define RVCSR_MHARTID_LSB _u(0) 3142 #define RVCSR_MHARTID_ACCESS "RO" 3143 // ============================================================================= 3144 // Register : RVCSR_MCONFIGPTR 3145 // Description : Pointer to configuration data structure (hardwired to 0) 3146 #define RVCSR_MCONFIGPTR_OFFSET _u(0x00000f15) 3147 #define RVCSR_MCONFIGPTR_BITS _u(0xffffffff) 3148 #define RVCSR_MCONFIGPTR_RESET _u(0x00000000) 3149 #define RVCSR_MCONFIGPTR_MSB _u(31) 3150 #define RVCSR_MCONFIGPTR_LSB _u(0) 3151 #define RVCSR_MCONFIGPTR_ACCESS "RO" 3152 // ============================================================================= 3153 #endif // _HARDWARE_REGS_RVCSR_H 3154 3155