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Searched refs:RVCSR_MEIFA_OFFSET (Results 1 – 4 of 4) sorted by relevance

/hal_rpi_pico-latest/src/rp2_common/hardware_irq/include/hardware/
Dirq.h383 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16)); in irq_clear()
/hal_rpi_pico-latest/src/rp2_common/hardware_irq/
Dirq.c82 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
83 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
122 hazard3_irqarray_set(RVCSR_MEIFA_OFFSET, num / 16, 1u << (num % 16)); in irq_set_pending()
/hal_rpi_pico-latest/src/rp2_common/pico_crt0/
Dcrt0_riscv.S547 csrw RVCSR_MEIFA_OFFSET, a0
/hal_rpi_pico-latest/src/rp2350/hardware_regs/include/hardware/regs/
Drvcsr.h2738 #define RVCSR_MEIFA_OFFSET _u(0x00000be2) macro