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Searched refs:RVCSR_MEIEA_OFFSET (Results 1 – 2 of 2) sorted by relevance

/hal_rpi_pico-latest/src/rp2_common/hardware_irq/
Dirq.c72 return 0 != (hazard3_irqarray_read(RVCSR_MEIEA_OFFSET, num / 16) & (1u << (num % 16))); in pico_irq_is_enabled()
84 hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
85 hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
87 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); in irq_set_mask_n_enabled_internal()
88 hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); in irq_set_mask_n_enabled_internal()
/hal_rpi_pico-latest/src/rp2350/hardware_regs/include/hardware/regs/
Drvcsr.h2651 #define RVCSR_MEIEA_OFFSET _u(0x00000be0) macro