1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : RTC 10 // Version : 1 11 // Bus type : apb 12 // Description : Register block to control RTC 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_RTC_H 15 #define _HARDWARE_REGS_RTC_H 16 // ============================================================================= 17 // Register : RTC_CLKDIV_M1 18 // Description : Divider minus 1 for the 1 second counter. Safe to change the 19 // value when RTC is not enabled. 20 #define RTC_CLKDIV_M1_OFFSET _u(0x00000000) 21 #define RTC_CLKDIV_M1_BITS _u(0x0000ffff) 22 #define RTC_CLKDIV_M1_RESET _u(0x00000000) 23 #define RTC_CLKDIV_M1_MSB _u(15) 24 #define RTC_CLKDIV_M1_LSB _u(0) 25 #define RTC_CLKDIV_M1_ACCESS "RW" 26 // ============================================================================= 27 // Register : RTC_SETUP_0 28 // Description : RTC setup register 0 29 #define RTC_SETUP_0_OFFSET _u(0x00000004) 30 #define RTC_SETUP_0_BITS _u(0x00ffff1f) 31 #define RTC_SETUP_0_RESET _u(0x00000000) 32 // ----------------------------------------------------------------------------- 33 // Field : RTC_SETUP_0_YEAR 34 // Description : Year 35 #define RTC_SETUP_0_YEAR_RESET _u(0x000) 36 #define RTC_SETUP_0_YEAR_BITS _u(0x00fff000) 37 #define RTC_SETUP_0_YEAR_MSB _u(23) 38 #define RTC_SETUP_0_YEAR_LSB _u(12) 39 #define RTC_SETUP_0_YEAR_ACCESS "RW" 40 // ----------------------------------------------------------------------------- 41 // Field : RTC_SETUP_0_MONTH 42 // Description : Month (1..12) 43 #define RTC_SETUP_0_MONTH_RESET _u(0x0) 44 #define RTC_SETUP_0_MONTH_BITS _u(0x00000f00) 45 #define RTC_SETUP_0_MONTH_MSB _u(11) 46 #define RTC_SETUP_0_MONTH_LSB _u(8) 47 #define RTC_SETUP_0_MONTH_ACCESS "RW" 48 // ----------------------------------------------------------------------------- 49 // Field : RTC_SETUP_0_DAY 50 // Description : Day of the month (1..31) 51 #define RTC_SETUP_0_DAY_RESET _u(0x00) 52 #define RTC_SETUP_0_DAY_BITS _u(0x0000001f) 53 #define RTC_SETUP_0_DAY_MSB _u(4) 54 #define RTC_SETUP_0_DAY_LSB _u(0) 55 #define RTC_SETUP_0_DAY_ACCESS "RW" 56 // ============================================================================= 57 // Register : RTC_SETUP_1 58 // Description : RTC setup register 1 59 #define RTC_SETUP_1_OFFSET _u(0x00000008) 60 #define RTC_SETUP_1_BITS _u(0x071f3f3f) 61 #define RTC_SETUP_1_RESET _u(0x00000000) 62 // ----------------------------------------------------------------------------- 63 // Field : RTC_SETUP_1_DOTW 64 // Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 65 #define RTC_SETUP_1_DOTW_RESET _u(0x0) 66 #define RTC_SETUP_1_DOTW_BITS _u(0x07000000) 67 #define RTC_SETUP_1_DOTW_MSB _u(26) 68 #define RTC_SETUP_1_DOTW_LSB _u(24) 69 #define RTC_SETUP_1_DOTW_ACCESS "RW" 70 // ----------------------------------------------------------------------------- 71 // Field : RTC_SETUP_1_HOUR 72 // Description : Hours 73 #define RTC_SETUP_1_HOUR_RESET _u(0x00) 74 #define RTC_SETUP_1_HOUR_BITS _u(0x001f0000) 75 #define RTC_SETUP_1_HOUR_MSB _u(20) 76 #define RTC_SETUP_1_HOUR_LSB _u(16) 77 #define RTC_SETUP_1_HOUR_ACCESS "RW" 78 // ----------------------------------------------------------------------------- 79 // Field : RTC_SETUP_1_MIN 80 // Description : Minutes 81 #define RTC_SETUP_1_MIN_RESET _u(0x00) 82 #define RTC_SETUP_1_MIN_BITS _u(0x00003f00) 83 #define RTC_SETUP_1_MIN_MSB _u(13) 84 #define RTC_SETUP_1_MIN_LSB _u(8) 85 #define RTC_SETUP_1_MIN_ACCESS "RW" 86 // ----------------------------------------------------------------------------- 87 // Field : RTC_SETUP_1_SEC 88 // Description : Seconds 89 #define RTC_SETUP_1_SEC_RESET _u(0x00) 90 #define RTC_SETUP_1_SEC_BITS _u(0x0000003f) 91 #define RTC_SETUP_1_SEC_MSB _u(5) 92 #define RTC_SETUP_1_SEC_LSB _u(0) 93 #define RTC_SETUP_1_SEC_ACCESS "RW" 94 // ============================================================================= 95 // Register : RTC_CTRL 96 // Description : RTC Control and status 97 #define RTC_CTRL_OFFSET _u(0x0000000c) 98 #define RTC_CTRL_BITS _u(0x00000113) 99 #define RTC_CTRL_RESET _u(0x00000000) 100 // ----------------------------------------------------------------------------- 101 // Field : RTC_CTRL_FORCE_NOTLEAPYEAR 102 // Description : If set, leapyear is forced off. 103 // Useful for years divisible by 100 but not by 400 104 #define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0) 105 #define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100) 106 #define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8) 107 #define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8) 108 #define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW" 109 // ----------------------------------------------------------------------------- 110 // Field : RTC_CTRL_LOAD 111 // Description : Load RTC 112 #define RTC_CTRL_LOAD_RESET _u(0x0) 113 #define RTC_CTRL_LOAD_BITS _u(0x00000010) 114 #define RTC_CTRL_LOAD_MSB _u(4) 115 #define RTC_CTRL_LOAD_LSB _u(4) 116 #define RTC_CTRL_LOAD_ACCESS "SC" 117 // ----------------------------------------------------------------------------- 118 // Field : RTC_CTRL_RTC_ACTIVE 119 // Description : RTC enabled (running) 120 #define RTC_CTRL_RTC_ACTIVE_RESET "-" 121 #define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002) 122 #define RTC_CTRL_RTC_ACTIVE_MSB _u(1) 123 #define RTC_CTRL_RTC_ACTIVE_LSB _u(1) 124 #define RTC_CTRL_RTC_ACTIVE_ACCESS "RO" 125 // ----------------------------------------------------------------------------- 126 // Field : RTC_CTRL_RTC_ENABLE 127 // Description : Enable RTC 128 #define RTC_CTRL_RTC_ENABLE_RESET _u(0x0) 129 #define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001) 130 #define RTC_CTRL_RTC_ENABLE_MSB _u(0) 131 #define RTC_CTRL_RTC_ENABLE_LSB _u(0) 132 #define RTC_CTRL_RTC_ENABLE_ACCESS "RW" 133 // ============================================================================= 134 // Register : RTC_IRQ_SETUP_0 135 // Description : Interrupt setup register 0 136 #define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010) 137 #define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f) 138 #define RTC_IRQ_SETUP_0_RESET _u(0x00000000) 139 // ----------------------------------------------------------------------------- 140 // Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE 141 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-" 142 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000) 143 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29) 144 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29) 145 #define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO" 146 // ----------------------------------------------------------------------------- 147 // Field : RTC_IRQ_SETUP_0_MATCH_ENA 148 // Description : Global match enable. Don't change any other value while this 149 // one is enabled 150 #define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0) 151 #define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000) 152 #define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28) 153 #define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28) 154 #define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW" 155 // ----------------------------------------------------------------------------- 156 // Field : RTC_IRQ_SETUP_0_YEAR_ENA 157 // Description : Enable year matching 158 #define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0) 159 #define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000) 160 #define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26) 161 #define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26) 162 #define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW" 163 // ----------------------------------------------------------------------------- 164 // Field : RTC_IRQ_SETUP_0_MONTH_ENA 165 // Description : Enable month matching 166 #define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0) 167 #define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000) 168 #define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25) 169 #define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25) 170 #define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW" 171 // ----------------------------------------------------------------------------- 172 // Field : RTC_IRQ_SETUP_0_DAY_ENA 173 // Description : Enable day matching 174 #define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0) 175 #define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000) 176 #define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24) 177 #define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24) 178 #define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW" 179 // ----------------------------------------------------------------------------- 180 // Field : RTC_IRQ_SETUP_0_YEAR 181 // Description : Year 182 #define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000) 183 #define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000) 184 #define RTC_IRQ_SETUP_0_YEAR_MSB _u(23) 185 #define RTC_IRQ_SETUP_0_YEAR_LSB _u(12) 186 #define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW" 187 // ----------------------------------------------------------------------------- 188 // Field : RTC_IRQ_SETUP_0_MONTH 189 // Description : Month (1..12) 190 #define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0) 191 #define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00) 192 #define RTC_IRQ_SETUP_0_MONTH_MSB _u(11) 193 #define RTC_IRQ_SETUP_0_MONTH_LSB _u(8) 194 #define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW" 195 // ----------------------------------------------------------------------------- 196 // Field : RTC_IRQ_SETUP_0_DAY 197 // Description : Day of the month (1..31) 198 #define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00) 199 #define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f) 200 #define RTC_IRQ_SETUP_0_DAY_MSB _u(4) 201 #define RTC_IRQ_SETUP_0_DAY_LSB _u(0) 202 #define RTC_IRQ_SETUP_0_DAY_ACCESS "RW" 203 // ============================================================================= 204 // Register : RTC_IRQ_SETUP_1 205 // Description : Interrupt setup register 1 206 #define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014) 207 #define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f) 208 #define RTC_IRQ_SETUP_1_RESET _u(0x00000000) 209 // ----------------------------------------------------------------------------- 210 // Field : RTC_IRQ_SETUP_1_DOTW_ENA 211 // Description : Enable day of the week matching 212 #define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0) 213 #define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000) 214 #define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31) 215 #define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31) 216 #define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW" 217 // ----------------------------------------------------------------------------- 218 // Field : RTC_IRQ_SETUP_1_HOUR_ENA 219 // Description : Enable hour matching 220 #define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0) 221 #define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000) 222 #define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30) 223 #define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30) 224 #define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW" 225 // ----------------------------------------------------------------------------- 226 // Field : RTC_IRQ_SETUP_1_MIN_ENA 227 // Description : Enable minute matching 228 #define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0) 229 #define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000) 230 #define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29) 231 #define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29) 232 #define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW" 233 // ----------------------------------------------------------------------------- 234 // Field : RTC_IRQ_SETUP_1_SEC_ENA 235 // Description : Enable second matching 236 #define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0) 237 #define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000) 238 #define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28) 239 #define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28) 240 #define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW" 241 // ----------------------------------------------------------------------------- 242 // Field : RTC_IRQ_SETUP_1_DOTW 243 // Description : Day of the week 244 #define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0) 245 #define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000) 246 #define RTC_IRQ_SETUP_1_DOTW_MSB _u(26) 247 #define RTC_IRQ_SETUP_1_DOTW_LSB _u(24) 248 #define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW" 249 // ----------------------------------------------------------------------------- 250 // Field : RTC_IRQ_SETUP_1_HOUR 251 // Description : Hours 252 #define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00) 253 #define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000) 254 #define RTC_IRQ_SETUP_1_HOUR_MSB _u(20) 255 #define RTC_IRQ_SETUP_1_HOUR_LSB _u(16) 256 #define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW" 257 // ----------------------------------------------------------------------------- 258 // Field : RTC_IRQ_SETUP_1_MIN 259 // Description : Minutes 260 #define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00) 261 #define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00) 262 #define RTC_IRQ_SETUP_1_MIN_MSB _u(13) 263 #define RTC_IRQ_SETUP_1_MIN_LSB _u(8) 264 #define RTC_IRQ_SETUP_1_MIN_ACCESS "RW" 265 // ----------------------------------------------------------------------------- 266 // Field : RTC_IRQ_SETUP_1_SEC 267 // Description : Seconds 268 #define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00) 269 #define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f) 270 #define RTC_IRQ_SETUP_1_SEC_MSB _u(5) 271 #define RTC_IRQ_SETUP_1_SEC_LSB _u(0) 272 #define RTC_IRQ_SETUP_1_SEC_ACCESS "RW" 273 // ============================================================================= 274 // Register : RTC_RTC_1 275 // Description : RTC register 1. 276 #define RTC_RTC_1_OFFSET _u(0x00000018) 277 #define RTC_RTC_1_BITS _u(0x00ffff1f) 278 #define RTC_RTC_1_RESET _u(0x00000000) 279 // ----------------------------------------------------------------------------- 280 // Field : RTC_RTC_1_YEAR 281 // Description : Year 282 #define RTC_RTC_1_YEAR_RESET "-" 283 #define RTC_RTC_1_YEAR_BITS _u(0x00fff000) 284 #define RTC_RTC_1_YEAR_MSB _u(23) 285 #define RTC_RTC_1_YEAR_LSB _u(12) 286 #define RTC_RTC_1_YEAR_ACCESS "RO" 287 // ----------------------------------------------------------------------------- 288 // Field : RTC_RTC_1_MONTH 289 // Description : Month (1..12) 290 #define RTC_RTC_1_MONTH_RESET "-" 291 #define RTC_RTC_1_MONTH_BITS _u(0x00000f00) 292 #define RTC_RTC_1_MONTH_MSB _u(11) 293 #define RTC_RTC_1_MONTH_LSB _u(8) 294 #define RTC_RTC_1_MONTH_ACCESS "RO" 295 // ----------------------------------------------------------------------------- 296 // Field : RTC_RTC_1_DAY 297 // Description : Day of the month (1..31) 298 #define RTC_RTC_1_DAY_RESET "-" 299 #define RTC_RTC_1_DAY_BITS _u(0x0000001f) 300 #define RTC_RTC_1_DAY_MSB _u(4) 301 #define RTC_RTC_1_DAY_LSB _u(0) 302 #define RTC_RTC_1_DAY_ACCESS "RO" 303 // ============================================================================= 304 // Register : RTC_RTC_0 305 // Description : RTC register 0 306 // Read this before RTC 1! 307 #define RTC_RTC_0_OFFSET _u(0x0000001c) 308 #define RTC_RTC_0_BITS _u(0x071f3f3f) 309 #define RTC_RTC_0_RESET _u(0x00000000) 310 // ----------------------------------------------------------------------------- 311 // Field : RTC_RTC_0_DOTW 312 // Description : Day of the week 313 #define RTC_RTC_0_DOTW_RESET "-" 314 #define RTC_RTC_0_DOTW_BITS _u(0x07000000) 315 #define RTC_RTC_0_DOTW_MSB _u(26) 316 #define RTC_RTC_0_DOTW_LSB _u(24) 317 #define RTC_RTC_0_DOTW_ACCESS "RF" 318 // ----------------------------------------------------------------------------- 319 // Field : RTC_RTC_0_HOUR 320 // Description : Hours 321 #define RTC_RTC_0_HOUR_RESET "-" 322 #define RTC_RTC_0_HOUR_BITS _u(0x001f0000) 323 #define RTC_RTC_0_HOUR_MSB _u(20) 324 #define RTC_RTC_0_HOUR_LSB _u(16) 325 #define RTC_RTC_0_HOUR_ACCESS "RF" 326 // ----------------------------------------------------------------------------- 327 // Field : RTC_RTC_0_MIN 328 // Description : Minutes 329 #define RTC_RTC_0_MIN_RESET "-" 330 #define RTC_RTC_0_MIN_BITS _u(0x00003f00) 331 #define RTC_RTC_0_MIN_MSB _u(13) 332 #define RTC_RTC_0_MIN_LSB _u(8) 333 #define RTC_RTC_0_MIN_ACCESS "RF" 334 // ----------------------------------------------------------------------------- 335 // Field : RTC_RTC_0_SEC 336 // Description : Seconds 337 #define RTC_RTC_0_SEC_RESET "-" 338 #define RTC_RTC_0_SEC_BITS _u(0x0000003f) 339 #define RTC_RTC_0_SEC_MSB _u(5) 340 #define RTC_RTC_0_SEC_LSB _u(0) 341 #define RTC_RTC_0_SEC_ACCESS "RF" 342 // ============================================================================= 343 // Register : RTC_INTR 344 // Description : Raw Interrupts 345 #define RTC_INTR_OFFSET _u(0x00000020) 346 #define RTC_INTR_BITS _u(0x00000001) 347 #define RTC_INTR_RESET _u(0x00000000) 348 // ----------------------------------------------------------------------------- 349 // Field : RTC_INTR_RTC 350 #define RTC_INTR_RTC_RESET _u(0x0) 351 #define RTC_INTR_RTC_BITS _u(0x00000001) 352 #define RTC_INTR_RTC_MSB _u(0) 353 #define RTC_INTR_RTC_LSB _u(0) 354 #define RTC_INTR_RTC_ACCESS "RO" 355 // ============================================================================= 356 // Register : RTC_INTE 357 // Description : Interrupt Enable 358 #define RTC_INTE_OFFSET _u(0x00000024) 359 #define RTC_INTE_BITS _u(0x00000001) 360 #define RTC_INTE_RESET _u(0x00000000) 361 // ----------------------------------------------------------------------------- 362 // Field : RTC_INTE_RTC 363 #define RTC_INTE_RTC_RESET _u(0x0) 364 #define RTC_INTE_RTC_BITS _u(0x00000001) 365 #define RTC_INTE_RTC_MSB _u(0) 366 #define RTC_INTE_RTC_LSB _u(0) 367 #define RTC_INTE_RTC_ACCESS "RW" 368 // ============================================================================= 369 // Register : RTC_INTF 370 // Description : Interrupt Force 371 #define RTC_INTF_OFFSET _u(0x00000028) 372 #define RTC_INTF_BITS _u(0x00000001) 373 #define RTC_INTF_RESET _u(0x00000000) 374 // ----------------------------------------------------------------------------- 375 // Field : RTC_INTF_RTC 376 #define RTC_INTF_RTC_RESET _u(0x0) 377 #define RTC_INTF_RTC_BITS _u(0x00000001) 378 #define RTC_INTF_RTC_MSB _u(0) 379 #define RTC_INTF_RTC_LSB _u(0) 380 #define RTC_INTF_RTC_ACCESS "RW" 381 // ============================================================================= 382 // Register : RTC_INTS 383 // Description : Interrupt status after masking & forcing 384 #define RTC_INTS_OFFSET _u(0x0000002c) 385 #define RTC_INTS_BITS _u(0x00000001) 386 #define RTC_INTS_RESET _u(0x00000000) 387 // ----------------------------------------------------------------------------- 388 // Field : RTC_INTS_RTC 389 #define RTC_INTS_RTC_RESET _u(0x0) 390 #define RTC_INTS_RTC_BITS _u(0x00000001) 391 #define RTC_INTS_RTC_MSB _u(0) 392 #define RTC_INTS_RTC_LSB _u(0) 393 #define RTC_INTS_RTC_ACCESS "RO" 394 // ============================================================================= 395 #endif // _HARDWARE_REGS_RTC_H 396 397
