1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : RP_AP 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_RP_AP_H 14 #define _HARDWARE_REGS_RP_AP_H 15 // ============================================================================= 16 // Register : RP_AP_CTRL 17 // Description : This register is primarily used for DFT but can also be used to 18 // overcome some power up problems. However, it should not be used 19 // to force power up of domains. Use DBG_POW_OVRD for that. 20 #define RP_AP_CTRL_OFFSET _u(0x00000000) 21 #define RP_AP_CTRL_BITS _u(0xc000007f) 22 #define RP_AP_CTRL_RESET _u(0x00000000) 23 // ----------------------------------------------------------------------------- 24 // Field : RP_AP_CTRL_RESCUE_RESTART 25 // Description : Allows debug of boot problems by restarting the chip with 26 // minimal boot code execution. Write to 1 to put the chip in 27 // reset then write to 0 to restart the chip with the rescue flag 28 // set. The rescue flag is in the POWMAN_CHIP_RESET register and 29 // is read by boot code. The rescue flag is cleared by writing 0 30 // to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by 31 // any means other than RESCUE_RESTART. 32 #define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0) 33 #define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000) 34 #define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31) 35 #define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31) 36 #define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW" 37 // ----------------------------------------------------------------------------- 38 // Field : RP_AP_CTRL_SPARE 39 // Description : Unused 40 #define RP_AP_CTRL_SPARE_RESET _u(0x0) 41 #define RP_AP_CTRL_SPARE_BITS _u(0x40000000) 42 #define RP_AP_CTRL_SPARE_MSB _u(30) 43 #define RP_AP_CTRL_SPARE_LSB _u(30) 44 #define RP_AP_CTRL_SPARE_ACCESS "RW" 45 // ----------------------------------------------------------------------------- 46 // Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK 47 // Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is 48 // inoperative or malfunctioning and also allows the initial power 49 // sequencing rate to be adjusted. Write to 1 to force the LPOSC 50 // output to be driven from a GPIO (gpio20 on 80-pin package, 51 // gpio34 on the 60-pin package). If the LPOSC is inoperative or 52 // malfunctioning it may also be necessary to set the 53 // LPOSC_STABLE_FRCE bit in this register. The user must provide a 54 // clock on the GPIO. For normal operation use a clock running at 55 // around 32kHz. Adjusting the frequency will speed up or slow 56 // down the initial power-up sequence. 57 #define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0) 58 #define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040) 59 #define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6) 60 #define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6) 61 #define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW" 62 // ----------------------------------------------------------------------------- 63 // Field : RP_AP_CTRL_LPOSC_STABLE_FRCE 64 // Description : Allows the chip to start-up even though the Low Power 65 // Oscillator (LPOSC) is failing to set its stable flag. Initial 66 // power sequencing is clocked by LPOSC at around 32kHz but does 67 // not start until the LPOSC declares itself to be stable. If the 68 // LPOSC is otherwise working correctly the chip will boot when 69 // this bit is set. If the LPOSC is not working then 70 // DBG_FRCE_GPIO_LPCK must be set and an external clock provided. 71 #define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0) 72 #define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020) 73 #define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5) 74 #define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5) 75 #define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW" 76 // ----------------------------------------------------------------------------- 77 // Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF 78 // Description : Holds the isolation gates between power domains in the open 79 // state. This is intended to hold the gates open for DFT and 80 // power manager debug. It is not intended to force the isolation 81 // gates open. Use the overrides in DBG_POW_OVRD to force the 82 // isolation gates open or closed. 83 #define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0) 84 #define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010) 85 #define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4) 86 #define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4) 87 #define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW" 88 // ----------------------------------------------------------------------------- 89 // Field : RP_AP_CTRL_POWMAN_DFT_PWRON 90 // Description : Holds the power switches on for all domains. This is intended 91 // to keep the power on for DFT and debug, rather than for 92 // switching the power on. The power switches are not sequenced 93 // and the sudden demand for current could cause the always-on 94 // power domain to brown out. This register is in the always-on 95 // domain therefore chaos could ensue. It is recommended to use 96 // the DBG_POW_OVRD controls instead. 97 #define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0) 98 #define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008) 99 #define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3) 100 #define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3) 101 #define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW" 102 // ----------------------------------------------------------------------------- 103 // Field : RP_AP_CTRL_POWMAN_DBGMODE 104 // Description : This prevents the power manager from powering down and 105 // resetting the switched-core power domain. It is intended for 106 // DFT and for debugging the power manager after the chip has 107 // booted. It cannot be used to force initial power on because it 108 // simultaneously deasserts the reset. 109 #define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0) 110 #define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004) 111 #define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2) 112 #define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2) 113 #define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW" 114 // ----------------------------------------------------------------------------- 115 // Field : RP_AP_CTRL_JTAG_FUNCSEL 116 // Description : Multiplexes the JTAG ports onto GPIO0-3 117 #define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0) 118 #define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002) 119 #define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1) 120 #define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1) 121 #define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW" 122 // ----------------------------------------------------------------------------- 123 // Field : RP_AP_CTRL_JTAG_TRSTN 124 // Description : Resets the JTAG module. Active low. 125 #define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0) 126 #define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001) 127 #define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0) 128 #define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0) 129 #define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW" 130 // ============================================================================= 131 // Register : RP_AP_DBGKEY 132 // Description : Serial key load interface (write-only) 133 #define RP_AP_DBGKEY_OFFSET _u(0x00000004) 134 #define RP_AP_DBGKEY_BITS _u(0x00000007) 135 #define RP_AP_DBGKEY_RESET _u(0x00000000) 136 // ----------------------------------------------------------------------------- 137 // Field : RP_AP_DBGKEY_RESET 138 // Description : Reset (before sending a new key) 139 #define RP_AP_DBGKEY_RESET_RESET _u(0x0) 140 #define RP_AP_DBGKEY_RESET_BITS _u(0x00000004) 141 #define RP_AP_DBGKEY_RESET_MSB _u(2) 142 #define RP_AP_DBGKEY_RESET_LSB _u(2) 143 #define RP_AP_DBGKEY_RESET_ACCESS "RW" 144 // ----------------------------------------------------------------------------- 145 // Field : RP_AP_DBGKEY_PUSH 146 #define RP_AP_DBGKEY_PUSH_RESET _u(0x0) 147 #define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002) 148 #define RP_AP_DBGKEY_PUSH_MSB _u(1) 149 #define RP_AP_DBGKEY_PUSH_LSB _u(1) 150 #define RP_AP_DBGKEY_PUSH_ACCESS "RW" 151 // ----------------------------------------------------------------------------- 152 // Field : RP_AP_DBGKEY_DATA 153 #define RP_AP_DBGKEY_DATA_RESET _u(0x0) 154 #define RP_AP_DBGKEY_DATA_BITS _u(0x00000001) 155 #define RP_AP_DBGKEY_DATA_MSB _u(0) 156 #define RP_AP_DBGKEY_DATA_LSB _u(0) 157 #define RP_AP_DBGKEY_DATA_ACCESS "RW" 158 // ============================================================================= 159 // Register : RP_AP_DBG_POW_STATE_SWCORE 160 // Description : This register indicates the state of the power sequencer for 161 // the switched-core domain. 162 // The sequencer timing is managed by the POWMAN_SEQ_* registers. 163 // See the header file for those registers for more information on 164 // the timing. 165 // Power up of the domain commences by clearing bit 0 (IS_PD) then 166 // bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the 167 // sequence is complete. 168 // Power down of the domain commences by clearing bit 8 (IS_PU) 169 // then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then 170 // set to indicate the sequence is complete. 171 // Bits 9-11 describe the states of the power manager clocks which 172 // change as clock generators in the switched-core become 173 // available following switched-core power up. 174 // This bus can be sent to GPIO for debug. See 175 // DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register. 176 #define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008) 177 #define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff) 178 #define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000) 179 // ----------------------------------------------------------------------------- 180 // Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK 181 // Description : Indicates the source of the power manager clock. On switched- 182 // core power up the clock switches from the LPOSC to clk_ref and 183 // this flag will be set. clk_ref will be running from the ROSC 184 // initially but will switch to XOSC when it comes available. On 185 // switched-core power down the clock switches to LPOSC and this 186 // flag will be cleared. 187 #define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0) 188 #define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800) 189 #define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11) 190 #define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11) 191 #define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO" 192 // ----------------------------------------------------------------------------- 193 // Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK 194 // Description : Indicates the switched-core power sequencer is waiting for the 195 // power manager clock to update. On switched-core power up the 196 // clock switches from the LPOSC to clk_ref. clk_ref will be 197 // running from the ROSC initially but will switch to XOSC when it 198 // comes available. On switched-core power down the clock switches 199 // to LPOSC. 200 // If the switched-core power up sequence stalls with this flag 201 // active then it means clk_ref is not running which indicates a 202 // problem with the ROSC. If that happens then set 203 // DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid 204 // using the ROSC. 205 // If the switched-core power down sequence stalls with this flag 206 // active then it means LPOSC is not running. The solution is to 207 // not stop LPOSC when the switched-core power domain is powered. 208 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0) 209 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400) 210 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10) 211 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10) 212 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO" 213 // ----------------------------------------------------------------------------- 214 // Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK 215 // Description : Indicates that the switched-core power sequencer is waiting for 216 // the AON-Timer to update. On switched-core power-up there is 217 // nothing to be done. The AON-Timer continues to run from the 218 // LPOSC so this flag will not be set. Software decides whether to 219 // switch the AON-Timer clock to XOSC (via clk_ref). On switched- 220 // core power-down the sequencer will switch the AON-Timer back to 221 // LPOSC if software switched it to XOSC. During the switchover 222 // the WAITING_TIMCK flag will be set. If the switched-core power 223 // down sequence stalls with this flag active then the only 224 // recourse is to reset the chip and change software to not select 225 // XOSC as the AON-Timer source. 226 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0) 227 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200) 228 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9) 229 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9) 230 #define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO" 231 // ----------------------------------------------------------------------------- 232 // Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU 233 // Description : Indicates the power somain is fully powered up. 234 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0) 235 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100) 236 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8) 237 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8) 238 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO" 239 // ----------------------------------------------------------------------------- 240 // Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ 241 // Description : Indicates the state of the reset to the power domain. 242 #define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0) 243 #define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080) 244 #define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7) 245 #define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7) 246 #define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO" 247 // ----------------------------------------------------------------------------- 248 // Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK 249 // Description : Indicates the state of the enable to the power domain. 250 #define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0) 251 #define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040) 252 #define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6) 253 #define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6) 254 #define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO" 255 // ----------------------------------------------------------------------------- 256 // Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ 257 // Description : Indicates the state of the isolation control to the power 258 // domain. 259 #define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0) 260 #define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020) 261 #define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5) 262 #define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5) 263 #define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO" 264 // ----------------------------------------------------------------------------- 265 // Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK 266 // Description : Indicates the state of the large power switches for the power 267 // domain. 268 #define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0) 269 #define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010) 270 #define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4) 271 #define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4) 272 #define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO" 273 // ----------------------------------------------------------------------------- 274 // Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2 275 // Description : The small switches are split into 3 chains. In the power up 276 // sequence they are switched on separately to allow management of 277 // the VDD rise time. In the power down sequence they switch off 278 // simultaneously with the large power switches. 279 // This bit indicates the state of the last element in small power 280 // switch chain 2. 281 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0) 282 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008) 283 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3) 284 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3) 285 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO" 286 // ----------------------------------------------------------------------------- 287 // Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1 288 // Description : This bit indicates the state of the last element in small power 289 // switch chain 1. 290 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0) 291 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004) 292 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2) 293 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2) 294 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO" 295 // ----------------------------------------------------------------------------- 296 // Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0 297 // Description : This bit indicates the state of the last element in small power 298 // switch chain 0. 299 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0) 300 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002) 301 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1) 302 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1) 303 #define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO" 304 // ----------------------------------------------------------------------------- 305 // Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD 306 // Description : Indicates the power somain is fully powered down. 307 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0) 308 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001) 309 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0) 310 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0) 311 #define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO" 312 // ============================================================================= 313 // Register : RP_AP_DBG_POW_STATE_XIP 314 // Description : This register indicates the state of the power sequencer for 315 // the XIP domain. 316 // The sequencer timing is managed by the POWMAN_SEQ_* registers. 317 // See the header file for those registers for more information on 318 // the timing. 319 // Power up of the domain commences by clearing bit 0 (IS_PD) then 320 // bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the 321 // sequence is complete. 322 // Power down of the domain commences by clearing bit 8 (IS_PU) 323 // then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then 324 // set to indicate the sequence is complete. 325 #define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c) 326 #define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff) 327 #define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000) 328 // ----------------------------------------------------------------------------- 329 // Field : RP_AP_DBG_POW_STATE_XIP_IS_PU 330 // Description : Indicates the power somain is fully powered up. 331 #define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0) 332 #define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100) 333 #define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8) 334 #define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8) 335 #define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO" 336 // ----------------------------------------------------------------------------- 337 // Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ 338 // Description : Indicates the state of the reset to the power domain. 339 #define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0) 340 #define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080) 341 #define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7) 342 #define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7) 343 #define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO" 344 // ----------------------------------------------------------------------------- 345 // Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK 346 // Description : Indicates the state of the enable to the power domain. 347 #define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0) 348 #define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040) 349 #define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6) 350 #define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6) 351 #define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO" 352 // ----------------------------------------------------------------------------- 353 // Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ 354 // Description : Indicates the state of the isolation control to the power 355 // domain. 356 #define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0) 357 #define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020) 358 #define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5) 359 #define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5) 360 #define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO" 361 // ----------------------------------------------------------------------------- 362 // Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK 363 // Description : Indicates the state of the large power switches for the power 364 // domain. 365 #define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0) 366 #define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010) 367 #define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4) 368 #define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4) 369 #define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO" 370 // ----------------------------------------------------------------------------- 371 // Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2 372 // Description : The small switches are split into 3 chains. In the power up 373 // sequence they are switched on separately to allow management of 374 // the VDD rise time. In the power down sequence they switch off 375 // simultaneously with the large power switches. 376 // This bit indicates the state of the last element in small power 377 // switch chain 2. 378 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0) 379 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008) 380 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3) 381 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3) 382 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO" 383 // ----------------------------------------------------------------------------- 384 // Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1 385 // Description : This bit indicates the state of the last element in small power 386 // switch chain 1. 387 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0) 388 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004) 389 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2) 390 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2) 391 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO" 392 // ----------------------------------------------------------------------------- 393 // Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0 394 // Description : This bit indicates the state of the last element in small power 395 // switch chain 0. 396 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0) 397 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002) 398 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1) 399 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1) 400 #define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO" 401 // ----------------------------------------------------------------------------- 402 // Field : RP_AP_DBG_POW_STATE_XIP_IS_PD 403 // Description : Indicates the power somain is fully powered down. 404 #define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0) 405 #define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001) 406 #define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0) 407 #define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0) 408 #define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO" 409 // ============================================================================= 410 // Register : RP_AP_DBG_POW_STATE_SRAM0 411 // Description : This register indicates the state of the power sequencer for 412 // the SRAM0 domain. 413 // The sequencer timing is managed by the POWMAN_SEQ_* registers. 414 // See the header file for those registers for more information on 415 // the timing. 416 // Power up of the domain commences by clearing bit 0 (IS_PD) then 417 // bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the 418 // sequence is complete. 419 // Power down of the domain commences by clearing bit 8 (IS_PU) 420 // then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then 421 // set to indicate the sequence is complete. 422 #define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010) 423 #define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff) 424 #define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000) 425 // ----------------------------------------------------------------------------- 426 // Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU 427 // Description : Indicates the power somain is fully powered up. 428 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0) 429 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100) 430 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8) 431 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8) 432 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO" 433 // ----------------------------------------------------------------------------- 434 // Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ 435 // Description : Indicates the state of the reset to the power domain. 436 #define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0) 437 #define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080) 438 #define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7) 439 #define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7) 440 #define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO" 441 // ----------------------------------------------------------------------------- 442 // Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK 443 // Description : Indicates the state of the enable to the power domain. 444 #define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0) 445 #define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040) 446 #define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6) 447 #define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6) 448 #define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO" 449 // ----------------------------------------------------------------------------- 450 // Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ 451 // Description : Indicates the state of the isolation control to the power 452 // domain. 453 #define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0) 454 #define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020) 455 #define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5) 456 #define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5) 457 #define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO" 458 // ----------------------------------------------------------------------------- 459 // Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK 460 // Description : Indicates the state of the large power switches for the power 461 // domain. 462 #define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0) 463 #define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010) 464 #define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4) 465 #define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4) 466 #define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO" 467 // ----------------------------------------------------------------------------- 468 // Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2 469 // Description : The small switches are split into 3 chains. In the power up 470 // sequence they are switched on separately to allow management of 471 // the VDD rise time. In the power down sequence they switch off 472 // simultaneously with the large power switches. 473 // This bit indicates the state of the last element in small power 474 // switch chain 2. 475 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0) 476 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008) 477 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3) 478 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3) 479 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO" 480 // ----------------------------------------------------------------------------- 481 // Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1 482 // Description : This bit indicates the state of the last element in small power 483 // switch chain 1. 484 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0) 485 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004) 486 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2) 487 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2) 488 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO" 489 // ----------------------------------------------------------------------------- 490 // Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0 491 // Description : This bit indicates the state of the last element in small power 492 // switch chain 0. 493 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0) 494 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002) 495 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1) 496 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1) 497 #define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO" 498 // ----------------------------------------------------------------------------- 499 // Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD 500 // Description : Indicates the power somain is fully powered down. 501 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0) 502 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001) 503 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0) 504 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0) 505 #define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO" 506 // ============================================================================= 507 // Register : RP_AP_DBG_POW_STATE_SRAM1 508 // Description : This register indicates the state of the power sequencer for 509 // the SRAM1 domain. 510 // The sequencer timing is managed by the POWMAN_SEQ_* registers. 511 // See the header file for those registers for more information on 512 // the timing. 513 // Power up of the domain commences by clearing bit 0 (IS_PD) then 514 // bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the 515 // sequence is complete. 516 // Power down of the domain commences by clearing bit 8 (IS_PU) 517 // then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then 518 // set to indicate the sequence is complete. 519 #define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014) 520 #define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff) 521 #define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000) 522 // ----------------------------------------------------------------------------- 523 // Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU 524 // Description : Indicates the power somain is fully powered up. 525 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0) 526 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100) 527 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8) 528 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8) 529 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO" 530 // ----------------------------------------------------------------------------- 531 // Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ 532 // Description : Indicates the state of the reset to the power domain. 533 #define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0) 534 #define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080) 535 #define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7) 536 #define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7) 537 #define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO" 538 // ----------------------------------------------------------------------------- 539 // Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK 540 // Description : Indicates the state of the enable to the power domain. 541 #define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0) 542 #define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040) 543 #define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6) 544 #define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6) 545 #define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO" 546 // ----------------------------------------------------------------------------- 547 // Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ 548 // Description : Indicates the state of the isolation control to the power 549 // domain. 550 #define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0) 551 #define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020) 552 #define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5) 553 #define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5) 554 #define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO" 555 // ----------------------------------------------------------------------------- 556 // Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK 557 // Description : Indicates the state of the large power switches for the power 558 // domain. 559 #define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0) 560 #define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010) 561 #define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4) 562 #define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4) 563 #define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO" 564 // ----------------------------------------------------------------------------- 565 // Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2 566 // Description : The small switches are split into 3 chains. In the power up 567 // sequence they are switched on separately to allow management of 568 // the VDD rise time. In the power down sequence they switch off 569 // simultaneously with the large power switches. 570 // This bit indicates the state of the last element in small power 571 // switch chain 2. 572 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0) 573 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008) 574 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3) 575 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3) 576 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO" 577 // ----------------------------------------------------------------------------- 578 // Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1 579 // Description : This bit indicates the state of the last element in small power 580 // switch chain 1. 581 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0) 582 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004) 583 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2) 584 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2) 585 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO" 586 // ----------------------------------------------------------------------------- 587 // Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0 588 // Description : This bit indicates the state of the last element in small power 589 // switch chain 0. 590 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0) 591 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002) 592 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1) 593 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1) 594 #define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO" 595 // ----------------------------------------------------------------------------- 596 // Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD 597 // Description : Indicates the power somain is fully powered down. 598 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0) 599 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001) 600 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0) 601 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0) 602 #define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO" 603 // ============================================================================= 604 // Register : RP_AP_DBG_POW_OVRD 605 // Description : This register allows external control of the power sequencer 606 // outputs for all the switched power domains. If any of the power 607 // sequencers stall at any stage then force power up operation of 608 // all domains by running this sequence: 609 // - set DBG_POW_OVRD = 0x3b to force small power switches on, 610 // large power switches off, resets on and isolation on 611 // - allow time for the domain power supplies to reach full rail 612 // - set DBG_POW_OVRD = 0x3b to force large power switches on 613 // - set DBG_POW_OVRD = 0x37 to remove isolation 614 // - set DBG_POW_OVRD = 0x17 to remove resets 615 #define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018) 616 #define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f) 617 #define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000) 618 // ----------------------------------------------------------------------------- 619 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC 620 // Description : By default the system begins boot as soon as a clock is 621 // available from the ROSC, then it switches to the XOSC when it 622 // is available. This is done because the XOSC takes several ms to 623 // start up. If there is a problem with the ROSC then the default 624 // behaviour can be changed to not use the ROSC and wait for XOSC. 625 // However, this requires a mask change to modify the reset value 626 // of the Power Manager START_FROM_XOSC register. To allow 627 // experimentation the default can be temporarily changed by 628 // setting this register bit to 1. After setting this bit the core 629 // must be reset by a Coresight dprst or a rescue reset (see 630 // RESCUE_RESTART in the RP_AP_CTRL register above). A power-on 631 // reset, brown-out reset or RUN pin reset will reset this control 632 // and revert to the default behaviour. 633 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0) 634 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040) 635 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6) 636 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6) 637 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW" 638 // ----------------------------------------------------------------------------- 639 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET 640 // Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets 641 // for all domains. 1 = reset. 0 = not reset. 642 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0) 643 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020) 644 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5) 645 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5) 646 #define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW" 647 // ----------------------------------------------------------------------------- 648 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET 649 // Description : Enables DBG_POW_RESET to control the resets for the power 650 // manager and the switched-core. Essentially that is everythjing 651 // except the Coresight 2-wire interface and the RP_AP registers. 652 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0) 653 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010) 654 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4) 655 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4) 656 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW" 657 // ----------------------------------------------------------------------------- 658 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO 659 // Description : When DBG_POW_OVRD_ISO=1 this register bit controls the 660 // isolation gates for all domains. 1 = isolated. 0 = not 661 // isolated. 662 #define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0) 663 #define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008) 664 #define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3) 665 #define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3) 666 #define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW" 667 // ----------------------------------------------------------------------------- 668 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO 669 // Description : Enables DBG_POW_ISO to control the isolation gates between 670 // domains. 671 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0) 672 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004) 673 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2) 674 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2) 675 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW" 676 // ----------------------------------------------------------------------------- 677 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ 678 // Description : Turn on the large power switches for all domains. This should 679 // not be done until sufficient time has been allowed for the 680 // small switches to bring the supplies up. Switching the large 681 // switches on too soon risks browning out the always-on domain 682 // and corrupting these very registers. 683 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0) 684 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002) 685 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1) 686 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1) 687 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW" 688 // ----------------------------------------------------------------------------- 689 // Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ 690 // Description : Turn on the small power switches for all domains. This switches 691 // on chain 0 for each domain and switches off chains 2 & 3 and 692 // the large power switch chain. This will bring the power up for 693 // all domains without browning out the always-on power domain. 694 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0) 695 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001) 696 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0) 697 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0) 698 #define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW" 699 // ============================================================================= 700 // Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO 701 // Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios. 702 // Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34 703 // Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35 704 // Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36 705 // . 706 // . 707 // Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45 708 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c) 709 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff) 710 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000) 711 // ----------------------------------------------------------------------------- 712 // Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE 713 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000) 714 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff) 715 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11) 716 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0) 717 #define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW" 718 // ============================================================================= 719 // Register : RP_AP_IDR 720 // Description : Standard Coresight ID Register 721 #define RP_AP_IDR_OFFSET _u(0x00000dfc) 722 #define RP_AP_IDR_BITS _u(0xffffffff) 723 #define RP_AP_IDR_RESET "-" 724 #define RP_AP_IDR_MSB _u(31) 725 #define RP_AP_IDR_LSB _u(0) 726 #define RP_AP_IDR_ACCESS "RO" 727 // ============================================================================= 728 #endif // _HARDWARE_REGS_RP_AP_H 729 730
