1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : RISCV_DM 10 // Version : 1 11 // Bus type : apb 12 // Description : RISC-V Debug module registers (Hazard3 subset only). Read- 13 // only information fields (such as dmstatus.version) are 14 // listed here with the values they have on the RP2350 15 // instantiation of Hazard3. 16 // ============================================================================= 17 #ifndef _HARDWARE_REGS_RISCV_DM_H 18 #define _HARDWARE_REGS_RISCV_DM_H 19 // ============================================================================= 20 // Register : RISCV_DM_DATA0 21 // Description : data0 through data11 are basic read/write registers that may be 22 // read or changed by abstract commands. abstractcs.datacount 23 // indicates how many of them are implemented, starting at data0, 24 // counting up. 25 // 26 // Accessing these registers while an abstract command is 27 // executing causes abstractcs.cmderr to be set to 1 (busy) if it 28 // is 0. 29 // 30 // Attempts to write them while abstractcs.busy is set does not 31 // change their value. 32 // 33 // The values in these registers may not be preserved after an 34 // abstract command is executed. The only guarantees on their 35 // contents are the ones offered by the command in question. If 36 // the command fails, no assumptions can be made about the 37 // contents of these registers. 38 // 39 // (Note: Hazard3 implements data0 only.) 40 #define RISCV_DM_DATA0_OFFSET _u(0x00000010) 41 #define RISCV_DM_DATA0_BITS _u(0xffffffff) 42 #define RISCV_DM_DATA0_RESET _u(0x00000000) 43 #define RISCV_DM_DATA0_MSB _u(31) 44 #define RISCV_DM_DATA0_LSB _u(0) 45 #define RISCV_DM_DATA0_ACCESS "RW" 46 // ============================================================================= 47 // Register : RISCV_DM_DMCONTROL 48 // Description : This register controls the overall Debug Module as well as the 49 // currently selected harts, as defined in hasel. 50 #define RISCV_DM_DMCONTROL_OFFSET _u(0x00000040) 51 #define RISCV_DM_DMCONTROL_BITS _u(0xf7ffffcf) 52 #define RISCV_DM_DMCONTROL_RESET _u(0x00000000) 53 // ----------------------------------------------------------------------------- 54 // Field : RISCV_DM_DMCONTROL_HALTREQ 55 // Description : Writing 0 clears the halt request bit for all currently 56 // selected harts. This may cancel outstanding halt requests for 57 // those harts. 58 // 59 // Writing 1 sets the halt request bit for all currently selected 60 // harts. Running harts will halt whenever their halt request bit 61 // is set. 62 // 63 // Writes apply to the new value of hartsel and hasel. 64 #define RISCV_DM_DMCONTROL_HALTREQ_RESET _u(0x0) 65 #define RISCV_DM_DMCONTROL_HALTREQ_BITS _u(0x80000000) 66 #define RISCV_DM_DMCONTROL_HALTREQ_MSB _u(31) 67 #define RISCV_DM_DMCONTROL_HALTREQ_LSB _u(31) 68 #define RISCV_DM_DMCONTROL_HALTREQ_ACCESS "WO" 69 // ----------------------------------------------------------------------------- 70 // Field : RISCV_DM_DMCONTROL_RESUMEREQ 71 // Description : Writing 1 causes the currently selected harts to resume once, 72 // if they are halted when the write occurs. It also clears the 73 // resume ack bit for those harts. 74 // 75 // resumereq is ignored if haltreq is set. 76 // 77 // Writes apply to the new value of hartsel and hasel. 78 #define RISCV_DM_DMCONTROL_RESUMEREQ_RESET _u(0x0) 79 #define RISCV_DM_DMCONTROL_RESUMEREQ_BITS _u(0x40000000) 80 #define RISCV_DM_DMCONTROL_RESUMEREQ_MSB _u(30) 81 #define RISCV_DM_DMCONTROL_RESUMEREQ_LSB _u(30) 82 #define RISCV_DM_DMCONTROL_RESUMEREQ_ACCESS "SC" 83 // ----------------------------------------------------------------------------- 84 // Field : RISCV_DM_DMCONTROL_HARTRESET 85 // Description : This optional field writes the reset bit for all the currently 86 // selected harts. To perform a reset the debugger writes 1, and 87 // then writes 0 to deassert the reset signal. 88 // 89 // While this bit is 1, the debugger must not change which harts 90 // are selected. 91 // 92 // Writes apply to the new value of hartsel and hasel. 93 // 94 // (The exact behaviour of this field is implementation-defined: 95 // on RP2350 it (triggers a local reset of the selected core(s) 96 // only.) 97 #define RISCV_DM_DMCONTROL_HARTRESET_RESET _u(0x0) 98 #define RISCV_DM_DMCONTROL_HARTRESET_BITS _u(0x20000000) 99 #define RISCV_DM_DMCONTROL_HARTRESET_MSB _u(29) 100 #define RISCV_DM_DMCONTROL_HARTRESET_LSB _u(29) 101 #define RISCV_DM_DMCONTROL_HARTRESET_ACCESS "RW" 102 // ----------------------------------------------------------------------------- 103 // Field : RISCV_DM_DMCONTROL_ACKHAVERESET 104 // Description : 0: No effect. 105 // 106 // 1: Clears havereset for any selected harts. 107 // 108 // Writes apply to the new value of hartsel and hasel. 109 #define RISCV_DM_DMCONTROL_ACKHAVERESET_RESET _u(0x0) 110 #define RISCV_DM_DMCONTROL_ACKHAVERESET_BITS _u(0x10000000) 111 #define RISCV_DM_DMCONTROL_ACKHAVERESET_MSB _u(28) 112 #define RISCV_DM_DMCONTROL_ACKHAVERESET_LSB _u(28) 113 #define RISCV_DM_DMCONTROL_ACKHAVERESET_ACCESS "SC" 114 // ----------------------------------------------------------------------------- 115 // Field : RISCV_DM_DMCONTROL_HASEL 116 // Description : Selects the definition of currently selected harts. 117 // 118 // 0: There is a single currently selected hart, that is selected 119 // by hartsel. 120 // 121 // 1: There may be multiple currently selected harts – the hart 122 // selected by hartsel, plus those selected by the hart array mask 123 // register. 124 // 125 // Hazard3 does support the hart array mask. 126 #define RISCV_DM_DMCONTROL_HASEL_RESET _u(0x0) 127 #define RISCV_DM_DMCONTROL_HASEL_BITS _u(0x04000000) 128 #define RISCV_DM_DMCONTROL_HASEL_MSB _u(26) 129 #define RISCV_DM_DMCONTROL_HASEL_LSB _u(26) 130 #define RISCV_DM_DMCONTROL_HASEL_ACCESS "RW" 131 // ----------------------------------------------------------------------------- 132 // Field : RISCV_DM_DMCONTROL_HARTSELLO 133 // Description : The low 10 bits of hartsel: the DM-specific index of the hart 134 // to select. This hart is always part of the currently selected 135 // harts. 136 // 137 // On RP2350, since there are only two cores (with one hart each), 138 // only the least-significant bit is writable. The others are tied 139 // to 0. 140 #define RISCV_DM_DMCONTROL_HARTSELLO_RESET _u(0x000) 141 #define RISCV_DM_DMCONTROL_HARTSELLO_BITS _u(0x03ff0000) 142 #define RISCV_DM_DMCONTROL_HARTSELLO_MSB _u(25) 143 #define RISCV_DM_DMCONTROL_HARTSELLO_LSB _u(16) 144 #define RISCV_DM_DMCONTROL_HARTSELLO_ACCESS "RW" 145 // ----------------------------------------------------------------------------- 146 // Field : RISCV_DM_DMCONTROL_HARTSELHI 147 // Description : The high 10 bits of hartsel: the DM-specific index of the hart 148 // to select. This hart is always part of the currently selected 149 // harts. 150 // 151 // On Hazard3 this field is always tied to all-zeroes. 152 #define RISCV_DM_DMCONTROL_HARTSELHI_RESET _u(0x000) 153 #define RISCV_DM_DMCONTROL_HARTSELHI_BITS _u(0x0000ffc0) 154 #define RISCV_DM_DMCONTROL_HARTSELHI_MSB _u(15) 155 #define RISCV_DM_DMCONTROL_HARTSELHI_LSB _u(6) 156 #define RISCV_DM_DMCONTROL_HARTSELHI_ACCESS "RW" 157 // ----------------------------------------------------------------------------- 158 // Field : RISCV_DM_DMCONTROL_SETRESETHALTREQ 159 // Description : This optional field writes the halt-on-reset request bit for 160 // all currently selected harts, unless clrresethaltreq is 161 // simultaneously set to 1. 162 // 163 // When set to 1, each selected hart will halt upon the next 164 // deassertion of its reset. The halt-on-reset request bit is not 165 // automatically cleared. The debugger must write to 166 // clrresethaltreq to clear it. 167 // 168 // Writes apply to the new value of hartsel and hasel. 169 #define RISCV_DM_DMCONTROL_SETRESETHALTREQ_RESET _u(0x0) 170 #define RISCV_DM_DMCONTROL_SETRESETHALTREQ_BITS _u(0x00000008) 171 #define RISCV_DM_DMCONTROL_SETRESETHALTREQ_MSB _u(3) 172 #define RISCV_DM_DMCONTROL_SETRESETHALTREQ_LSB _u(3) 173 #define RISCV_DM_DMCONTROL_SETRESETHALTREQ_ACCESS "SC" 174 // ----------------------------------------------------------------------------- 175 // Field : RISCV_DM_DMCONTROL_CLRRESETHALTREQ 176 // Description : This optional field clears the halt-on-reset request bit for 177 // all currently selected harts. 178 // 179 // Writes apply to the new value of hartsel and hasel. 180 #define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_RESET _u(0x0) 181 #define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_BITS _u(0x00000004) 182 #define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_MSB _u(2) 183 #define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_LSB _u(2) 184 #define RISCV_DM_DMCONTROL_CLRRESETHALTREQ_ACCESS "SC" 185 // ----------------------------------------------------------------------------- 186 // Field : RISCV_DM_DMCONTROL_NDMRESET 187 // Description : This bit controls the reset signal from the DM to the rest of 188 // the system. The signal should reset every part of the system, 189 // including every hart, except for the DM and any logic required 190 // to access the DM. To perform a system reset the debugger writes 191 // 1, and then writes 0 to deassert the reset. 192 // 193 // On RP2350 this performs a cold reset, the equivalent of a 194 // watchdog reset with all WDSEL bits set. This includes both 195 // cores and all peripherals. 196 #define RISCV_DM_DMCONTROL_NDMRESET_RESET _u(0x0) 197 #define RISCV_DM_DMCONTROL_NDMRESET_BITS _u(0x00000002) 198 #define RISCV_DM_DMCONTROL_NDMRESET_MSB _u(1) 199 #define RISCV_DM_DMCONTROL_NDMRESET_LSB _u(1) 200 #define RISCV_DM_DMCONTROL_NDMRESET_ACCESS "RW" 201 // ----------------------------------------------------------------------------- 202 // Field : RISCV_DM_DMCONTROL_DMACTIVE 203 // Description : This bit serves as a reset signal for the Debug Module itself. 204 // 205 // 0: The module’s state, including authentication mechanism, 206 // takes its reset values (the dmactive bit is the only bit which 207 // can be written to something other than its reset value). 208 // 209 // 1: The module functions normally. 210 // 211 // No other mechanism should exist that may result in resetting 212 // the Debug Module after power up, with the possible (but not 213 // recommended) exception of a global reset signal that resets the 214 // entire platform. 215 // 216 // (On RP2350, the Debug Module is reset by a power-on reset, a 217 // brownout reset, the RUN pin, and a rescue reset.) 218 // 219 // A debugger may pulse this bit low to get the Debug Module into 220 // a known state. 221 #define RISCV_DM_DMCONTROL_DMACTIVE_RESET _u(0x0) 222 #define RISCV_DM_DMCONTROL_DMACTIVE_BITS _u(0x00000001) 223 #define RISCV_DM_DMCONTROL_DMACTIVE_MSB _u(0) 224 #define RISCV_DM_DMCONTROL_DMACTIVE_LSB _u(0) 225 #define RISCV_DM_DMCONTROL_DMACTIVE_ACCESS "RW" 226 // ============================================================================= 227 // Register : RISCV_DM_DMSTATUS 228 // Description : This register reports status for the overall Debug Module as 229 // well as the currently selected harts, as defined in hasel. Its 230 // address will not change in the future, because it contains 231 // version. 232 // 233 // This entire register is read-only. 234 #define RISCV_DM_DMSTATUS_OFFSET _u(0x00000044) 235 #define RISCV_DM_DMSTATUS_BITS _u(0x004fffff) 236 #define RISCV_DM_DMSTATUS_RESET _u(0x004000a2) 237 // ----------------------------------------------------------------------------- 238 // Field : RISCV_DM_DMSTATUS_IMPEBREAK 239 // Description : If 1, then there is an implicit ebreak instruction at the non- 240 // existent word immediately after the Program Buffer. This saves 241 // the debugger from having to write the ebreak itself, and allows 242 // the Program Buffer to be one word smaller. 243 #define RISCV_DM_DMSTATUS_IMPEBREAK_RESET _u(0x1) 244 #define RISCV_DM_DMSTATUS_IMPEBREAK_BITS _u(0x00400000) 245 #define RISCV_DM_DMSTATUS_IMPEBREAK_MSB _u(22) 246 #define RISCV_DM_DMSTATUS_IMPEBREAK_LSB _u(22) 247 #define RISCV_DM_DMSTATUS_IMPEBREAK_ACCESS "RO" 248 // ----------------------------------------------------------------------------- 249 // Field : RISCV_DM_DMSTATUS_ALLHAVERESET 250 // Description : This field is 1 when all currently selected harts have been 251 // reset and reset has not been acknowledged for any of them. 252 #define RISCV_DM_DMSTATUS_ALLHAVERESET_RESET _u(0x0) 253 #define RISCV_DM_DMSTATUS_ALLHAVERESET_BITS _u(0x00080000) 254 #define RISCV_DM_DMSTATUS_ALLHAVERESET_MSB _u(19) 255 #define RISCV_DM_DMSTATUS_ALLHAVERESET_LSB _u(19) 256 #define RISCV_DM_DMSTATUS_ALLHAVERESET_ACCESS "RO" 257 // ----------------------------------------------------------------------------- 258 // Field : RISCV_DM_DMSTATUS_ANYHAVERESET 259 // Description : This field is 1 when at least one currently selected hart has 260 // been reset and reset has not been acknowledged for that hart. 261 #define RISCV_DM_DMSTATUS_ANYHAVERESET_RESET _u(0x0) 262 #define RISCV_DM_DMSTATUS_ANYHAVERESET_BITS _u(0x00040000) 263 #define RISCV_DM_DMSTATUS_ANYHAVERESET_MSB _u(18) 264 #define RISCV_DM_DMSTATUS_ANYHAVERESET_LSB _u(18) 265 #define RISCV_DM_DMSTATUS_ANYHAVERESET_ACCESS "RO" 266 // ----------------------------------------------------------------------------- 267 // Field : RISCV_DM_DMSTATUS_ALLRESUMEACK 268 // Description : This field is 1 when all currently selected harts have 269 // acknowledged their last resume request. 270 #define RISCV_DM_DMSTATUS_ALLRESUMEACK_RESET _u(0x0) 271 #define RISCV_DM_DMSTATUS_ALLRESUMEACK_BITS _u(0x00020000) 272 #define RISCV_DM_DMSTATUS_ALLRESUMEACK_MSB _u(17) 273 #define RISCV_DM_DMSTATUS_ALLRESUMEACK_LSB _u(17) 274 #define RISCV_DM_DMSTATUS_ALLRESUMEACK_ACCESS "RO" 275 // ----------------------------------------------------------------------------- 276 // Field : RISCV_DM_DMSTATUS_ANYRESUMEACK 277 // Description : This field is 1 when any currently selected hart has 278 // acknowledged its last resume request. 279 #define RISCV_DM_DMSTATUS_ANYRESUMEACK_RESET _u(0x0) 280 #define RISCV_DM_DMSTATUS_ANYRESUMEACK_BITS _u(0x00010000) 281 #define RISCV_DM_DMSTATUS_ANYRESUMEACK_MSB _u(16) 282 #define RISCV_DM_DMSTATUS_ANYRESUMEACK_LSB _u(16) 283 #define RISCV_DM_DMSTATUS_ANYRESUMEACK_ACCESS "RO" 284 // ----------------------------------------------------------------------------- 285 // Field : RISCV_DM_DMSTATUS_ALLNONEXISTENT 286 // Description : This field is 1 when all currently selected harts do not exist 287 // on this platform. 288 #define RISCV_DM_DMSTATUS_ALLNONEXISTENT_RESET "-" 289 #define RISCV_DM_DMSTATUS_ALLNONEXISTENT_BITS _u(0x00008000) 290 #define RISCV_DM_DMSTATUS_ALLNONEXISTENT_MSB _u(15) 291 #define RISCV_DM_DMSTATUS_ALLNONEXISTENT_LSB _u(15) 292 #define RISCV_DM_DMSTATUS_ALLNONEXISTENT_ACCESS "RO" 293 // ----------------------------------------------------------------------------- 294 // Field : RISCV_DM_DMSTATUS_ANYNONEXISTENT 295 // Description : This field is 1 when any currently selected hart does not exist 296 // in this platform. 297 #define RISCV_DM_DMSTATUS_ANYNONEXISTENT_RESET "-" 298 #define RISCV_DM_DMSTATUS_ANYNONEXISTENT_BITS _u(0x00004000) 299 #define RISCV_DM_DMSTATUS_ANYNONEXISTENT_MSB _u(14) 300 #define RISCV_DM_DMSTATUS_ANYNONEXISTENT_LSB _u(14) 301 #define RISCV_DM_DMSTATUS_ANYNONEXISTENT_ACCESS "RO" 302 // ----------------------------------------------------------------------------- 303 // Field : RISCV_DM_DMSTATUS_ALLUNAVAIL 304 // Description : This field is 1 when all currently selected harts are 305 // unavailable. 306 #define RISCV_DM_DMSTATUS_ALLUNAVAIL_RESET "-" 307 #define RISCV_DM_DMSTATUS_ALLUNAVAIL_BITS _u(0x00002000) 308 #define RISCV_DM_DMSTATUS_ALLUNAVAIL_MSB _u(13) 309 #define RISCV_DM_DMSTATUS_ALLUNAVAIL_LSB _u(13) 310 #define RISCV_DM_DMSTATUS_ALLUNAVAIL_ACCESS "RO" 311 // ----------------------------------------------------------------------------- 312 // Field : RISCV_DM_DMSTATUS_ANYUNAVAIL 313 // Description : This field is 1 when any currently selected hart is 314 // unavailable. 315 #define RISCV_DM_DMSTATUS_ANYUNAVAIL_RESET "-" 316 #define RISCV_DM_DMSTATUS_ANYUNAVAIL_BITS _u(0x00001000) 317 #define RISCV_DM_DMSTATUS_ANYUNAVAIL_MSB _u(12) 318 #define RISCV_DM_DMSTATUS_ANYUNAVAIL_LSB _u(12) 319 #define RISCV_DM_DMSTATUS_ANYUNAVAIL_ACCESS "RO" 320 // ----------------------------------------------------------------------------- 321 // Field : RISCV_DM_DMSTATUS_ALLRUNNING 322 // Description : This field is 1 when all currently selected harts are running. 323 #define RISCV_DM_DMSTATUS_ALLRUNNING_RESET _u(0x0) 324 #define RISCV_DM_DMSTATUS_ALLRUNNING_BITS _u(0x00000800) 325 #define RISCV_DM_DMSTATUS_ALLRUNNING_MSB _u(11) 326 #define RISCV_DM_DMSTATUS_ALLRUNNING_LSB _u(11) 327 #define RISCV_DM_DMSTATUS_ALLRUNNING_ACCESS "RO" 328 // ----------------------------------------------------------------------------- 329 // Field : RISCV_DM_DMSTATUS_ANYRUNNING 330 // Description : This field is 1 when any currently selected hart is running. 331 #define RISCV_DM_DMSTATUS_ANYRUNNING_RESET _u(0x0) 332 #define RISCV_DM_DMSTATUS_ANYRUNNING_BITS _u(0x00000400) 333 #define RISCV_DM_DMSTATUS_ANYRUNNING_MSB _u(10) 334 #define RISCV_DM_DMSTATUS_ANYRUNNING_LSB _u(10) 335 #define RISCV_DM_DMSTATUS_ANYRUNNING_ACCESS "RO" 336 // ----------------------------------------------------------------------------- 337 // Field : RISCV_DM_DMSTATUS_ALLHALTED 338 // Description : This field is 1 when all currently selected harts are halted. 339 #define RISCV_DM_DMSTATUS_ALLHALTED_RESET _u(0x0) 340 #define RISCV_DM_DMSTATUS_ALLHALTED_BITS _u(0x00000200) 341 #define RISCV_DM_DMSTATUS_ALLHALTED_MSB _u(9) 342 #define RISCV_DM_DMSTATUS_ALLHALTED_LSB _u(9) 343 #define RISCV_DM_DMSTATUS_ALLHALTED_ACCESS "RO" 344 // ----------------------------------------------------------------------------- 345 // Field : RISCV_DM_DMSTATUS_ANYHALTED 346 // Description : This field is 1 when any currently selected hart is halted. 347 #define RISCV_DM_DMSTATUS_ANYHALTED_RESET _u(0x0) 348 #define RISCV_DM_DMSTATUS_ANYHALTED_BITS _u(0x00000100) 349 #define RISCV_DM_DMSTATUS_ANYHALTED_MSB _u(8) 350 #define RISCV_DM_DMSTATUS_ANYHALTED_LSB _u(8) 351 #define RISCV_DM_DMSTATUS_ANYHALTED_ACCESS "RO" 352 // ----------------------------------------------------------------------------- 353 // Field : RISCV_DM_DMSTATUS_AUTHENTICATED 354 // Description : 0: Authentication is required before using the DM. 355 // 356 // 1: The authentication check has passed. 357 // 358 // On components that don’t implement authentication, this bit 359 // must be preset as 1. (Note: the version of Hazard3 on RP2350 360 // does not implement authentication.) 361 #define RISCV_DM_DMSTATUS_AUTHENTICATED_RESET _u(0x1) 362 #define RISCV_DM_DMSTATUS_AUTHENTICATED_BITS _u(0x00000080) 363 #define RISCV_DM_DMSTATUS_AUTHENTICATED_MSB _u(7) 364 #define RISCV_DM_DMSTATUS_AUTHENTICATED_LSB _u(7) 365 #define RISCV_DM_DMSTATUS_AUTHENTICATED_ACCESS "RO" 366 // ----------------------------------------------------------------------------- 367 // Field : RISCV_DM_DMSTATUS_AUTHBUSY 368 // Description : 0: The authentication module is ready to process the next 369 // read/write to authdata. 370 // 371 // 1: The authentication module is busy. Accessing authdata 372 // results in unspecified behavior. authbusy only becomes set in 373 // immediate response to an access to authdata. 374 #define RISCV_DM_DMSTATUS_AUTHBUSY_RESET _u(0x0) 375 #define RISCV_DM_DMSTATUS_AUTHBUSY_BITS _u(0x00000040) 376 #define RISCV_DM_DMSTATUS_AUTHBUSY_MSB _u(6) 377 #define RISCV_DM_DMSTATUS_AUTHBUSY_LSB _u(6) 378 #define RISCV_DM_DMSTATUS_AUTHBUSY_ACCESS "RO" 379 // ----------------------------------------------------------------------------- 380 // Field : RISCV_DM_DMSTATUS_HASRESETHALTREQ 381 // Description : 1 if this Debug Module supports halt-on-reset functionality 382 // controllable by the setresethaltreq and clrresethaltreq bits. 0 383 // otherwise. 384 #define RISCV_DM_DMSTATUS_HASRESETHALTREQ_RESET _u(0x1) 385 #define RISCV_DM_DMSTATUS_HASRESETHALTREQ_BITS _u(0x00000020) 386 #define RISCV_DM_DMSTATUS_HASRESETHALTREQ_MSB _u(5) 387 #define RISCV_DM_DMSTATUS_HASRESETHALTREQ_LSB _u(5) 388 #define RISCV_DM_DMSTATUS_HASRESETHALTREQ_ACCESS "RO" 389 // ----------------------------------------------------------------------------- 390 // Field : RISCV_DM_DMSTATUS_CONFSTPTRVALID 391 // Description : 0: confstrptr0–confstrptr3 hold information which is not 392 // relevant to the configuration string. 393 // 394 // 1: confstrptr0–confstrptr3 hold the address of the 395 // configuration string. 396 #define RISCV_DM_DMSTATUS_CONFSTPTRVALID_RESET _u(0x0) 397 #define RISCV_DM_DMSTATUS_CONFSTPTRVALID_BITS _u(0x00000010) 398 #define RISCV_DM_DMSTATUS_CONFSTPTRVALID_MSB _u(4) 399 #define RISCV_DM_DMSTATUS_CONFSTPTRVALID_LSB _u(4) 400 #define RISCV_DM_DMSTATUS_CONFSTPTRVALID_ACCESS "RO" 401 // ----------------------------------------------------------------------------- 402 // Field : RISCV_DM_DMSTATUS_VERSION 403 // Description : 0: There is no Debug Module present. 1: There is a Debug Module 404 // and it conforms to version 0.11 of the RISC-V debug 405 // specification. 406 // 407 // 2: There is a Debug Module and it conforms to version 0.13 of 408 // the RISC-V debug specification. 409 // 410 // 15: There is a Debug Module but it does not con- form to any 411 // available version of the RISC-V debug spec. 412 #define RISCV_DM_DMSTATUS_VERSION_RESET _u(0x2) 413 #define RISCV_DM_DMSTATUS_VERSION_BITS _u(0x0000000f) 414 #define RISCV_DM_DMSTATUS_VERSION_MSB _u(3) 415 #define RISCV_DM_DMSTATUS_VERSION_LSB _u(0) 416 #define RISCV_DM_DMSTATUS_VERSION_ACCESS "RO" 417 // ============================================================================= 418 // Register : RISCV_DM_HARTINFO 419 // Description : This register gives information about the hart currently 420 // selected by hartsel. 421 // 422 // This entire register is read-only. 423 #define RISCV_DM_HARTINFO_OFFSET _u(0x00000048) 424 #define RISCV_DM_HARTINFO_BITS _u(0x00f1ffff) 425 #define RISCV_DM_HARTINFO_RESET _u(0x00001bff) 426 // ----------------------------------------------------------------------------- 427 // Field : RISCV_DM_HARTINFO_NSCRATCH 428 // Description : Number of dscratch registers available for the debugger to use 429 // during program buffer execution, starting from dscratch0. The 430 // debugger can make no assumptions about the contents of these 431 // registers between commands. 432 #define RISCV_DM_HARTINFO_NSCRATCH_RESET _u(0x0) 433 #define RISCV_DM_HARTINFO_NSCRATCH_BITS _u(0x00f00000) 434 #define RISCV_DM_HARTINFO_NSCRATCH_MSB _u(23) 435 #define RISCV_DM_HARTINFO_NSCRATCH_LSB _u(20) 436 #define RISCV_DM_HARTINFO_NSCRATCH_ACCESS "RO" 437 // ----------------------------------------------------------------------------- 438 // Field : RISCV_DM_HARTINFO_DATAACCESS 439 // Description : 0: The data registers are shadowed in the hart by CSRs. Each 440 // CSR is DXLEN bits in size, and corresponds to a single 441 // argument. 442 // 443 // 1: The data registers are shadowed in the hart’s memory map. 444 // Each register takes up 4 bytes in the memory map. 445 #define RISCV_DM_HARTINFO_DATAACCESS_RESET _u(0x0) 446 #define RISCV_DM_HARTINFO_DATAACCESS_BITS _u(0x00010000) 447 #define RISCV_DM_HARTINFO_DATAACCESS_MSB _u(16) 448 #define RISCV_DM_HARTINFO_DATAACCESS_LSB _u(16) 449 #define RISCV_DM_HARTINFO_DATAACCESS_ACCESS "RO" 450 // ----------------------------------------------------------------------------- 451 // Field : RISCV_DM_HARTINFO_DATASIZE 452 // Description : If dataaccess is 0: Number of CSRs dedicated to shadowing the 453 // data registers. 454 // 455 // If dataaccess is 1: Number of 32-bit words in the memory map 456 // dedicated to shadowing the data registers. 457 #define RISCV_DM_HARTINFO_DATASIZE_RESET _u(0x1) 458 #define RISCV_DM_HARTINFO_DATASIZE_BITS _u(0x0000f000) 459 #define RISCV_DM_HARTINFO_DATASIZE_MSB _u(15) 460 #define RISCV_DM_HARTINFO_DATASIZE_LSB _u(12) 461 #define RISCV_DM_HARTINFO_DATASIZE_ACCESS "RW" 462 // ----------------------------------------------------------------------------- 463 // Field : RISCV_DM_HARTINFO_DATAADDR 464 // Description : If dataaccess is 0: The number of the first CSR dedicated to 465 // shadowing the data registers. 466 // 467 // If dataaccess is 1: Signed address of RAM where the data 468 // registers are shadowed, to be used to access relative to zero 469 // 470 // On Hazard3 this indicates the single data register mapped as 471 // dmdata0. There is actually only a single shared register, 472 // internal to the Debug Module, and mirrored in each core's CSR 473 // space. 474 #define RISCV_DM_HARTINFO_DATAADDR_RESET _u(0xbff) 475 #define RISCV_DM_HARTINFO_DATAADDR_BITS _u(0x00000fff) 476 #define RISCV_DM_HARTINFO_DATAADDR_MSB _u(11) 477 #define RISCV_DM_HARTINFO_DATAADDR_LSB _u(0) 478 #define RISCV_DM_HARTINFO_DATAADDR_ACCESS "RW" 479 // ============================================================================= 480 // Register : RISCV_DM_HALTSUM1 481 // Description : Each bit in this read-only register indicates whether any of a 482 // group of harts is halted or not. Unavailable/nonexistent harts 483 // are not considered to be halted. 484 // 485 // Each bit in haltsum1 is an OR reduction of 32 bits' worth of 486 // haltsum0. On RP2350, only the LSB is implemented. 487 #define RISCV_DM_HALTSUM1_OFFSET _u(0x0000004c) 488 #define RISCV_DM_HALTSUM1_BITS _u(0x00000001) 489 #define RISCV_DM_HALTSUM1_RESET _u(0x00000000) 490 #define RISCV_DM_HALTSUM1_MSB _u(0) 491 #define RISCV_DM_HALTSUM1_LSB _u(0) 492 #define RISCV_DM_HALTSUM1_ACCESS "RO" 493 // ============================================================================= 494 // Register : RISCV_DM_HAWINDOWSEL 495 // Description : This register selects which of the 32-bit portion of the hart 496 // array mask register is accessible in hawindow. 497 #define RISCV_DM_HAWINDOWSEL_OFFSET _u(0x00000050) 498 #define RISCV_DM_HAWINDOWSEL_BITS _u(0x00007fff) 499 #define RISCV_DM_HAWINDOWSEL_RESET _u(0x00000000) 500 // ----------------------------------------------------------------------------- 501 // Field : RISCV_DM_HAWINDOWSEL_HAWINDOWSEL 502 // Description : On Hazard3 this register is entirely hardwired to 0. 503 #define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_RESET _u(0x0000) 504 #define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_BITS _u(0x00007fff) 505 #define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_MSB _u(14) 506 #define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_LSB _u(0) 507 #define RISCV_DM_HAWINDOWSEL_HAWINDOWSEL_ACCESS "RW" 508 // ============================================================================= 509 // Register : RISCV_DM_HAWINDOW 510 // Description : This register provides R/W access to a 32-bit portion of the 511 // hart array mask register. The position of the window is 512 // determined by hawindowsel. I.e. bit 0 refers to hart 513 // hawindowsel ∗ 32, while bit 31 refers to hart hawindowsel ∗ 32 514 // + 31. 515 // 516 // On RP2350 only the two least-significant bits of this register 517 // are implemented, since there are only two cores. This is still 518 // useful to run/halt/reset both cores exactly simultaneously. 519 #define RISCV_DM_HAWINDOW_OFFSET _u(0x00000054) 520 #define RISCV_DM_HAWINDOW_BITS _u(0x00000003) 521 #define RISCV_DM_HAWINDOW_RESET _u(0x00000000) 522 // ----------------------------------------------------------------------------- 523 // Field : RISCV_DM_HAWINDOW_MASKDATA 524 #define RISCV_DM_HAWINDOW_MASKDATA_RESET _u(0x0) 525 #define RISCV_DM_HAWINDOW_MASKDATA_BITS _u(0x00000003) 526 #define RISCV_DM_HAWINDOW_MASKDATA_MSB _u(1) 527 #define RISCV_DM_HAWINDOW_MASKDATA_LSB _u(0) 528 #define RISCV_DM_HAWINDOW_MASKDATA_ACCESS "RW" 529 // ============================================================================= 530 // Register : RISCV_DM_ABSTRACTS 531 // Description : Abstract Control and Status. Writing this register while an 532 // abstract command is executing causes cmderr to be set to 1 533 // (busy) if it is 0. 534 #define RISCV_DM_ABSTRACTS_OFFSET _u(0x00000058) 535 #define RISCV_DM_ABSTRACTS_BITS _u(0x1f00170f) 536 #define RISCV_DM_ABSTRACTS_RESET _u(0x02000001) 537 // ----------------------------------------------------------------------------- 538 // Field : RISCV_DM_ABSTRACTS_PROGBUFSIZE 539 // Description : Size of the Program Buffer, in 32-bit words. 540 #define RISCV_DM_ABSTRACTS_PROGBUFSIZE_RESET _u(0x02) 541 #define RISCV_DM_ABSTRACTS_PROGBUFSIZE_BITS _u(0x1f000000) 542 #define RISCV_DM_ABSTRACTS_PROGBUFSIZE_MSB _u(28) 543 #define RISCV_DM_ABSTRACTS_PROGBUFSIZE_LSB _u(24) 544 #define RISCV_DM_ABSTRACTS_PROGBUFSIZE_ACCESS "RW" 545 // ----------------------------------------------------------------------------- 546 // Field : RISCV_DM_ABSTRACTS_BUSY 547 // Description : 1: An abstract command is currently being executed. 548 // 549 // This bit is set as soon as command is written, and is not 550 // cleared until that command has completed. 551 #define RISCV_DM_ABSTRACTS_BUSY_RESET _u(0x0) 552 #define RISCV_DM_ABSTRACTS_BUSY_BITS _u(0x00001000) 553 #define RISCV_DM_ABSTRACTS_BUSY_MSB _u(12) 554 #define RISCV_DM_ABSTRACTS_BUSY_LSB _u(12) 555 #define RISCV_DM_ABSTRACTS_BUSY_ACCESS "RW" 556 // ----------------------------------------------------------------------------- 557 // Field : RISCV_DM_ABSTRACTS_CMDERR 558 // Description : Gets set if an abstract command fails. The bits in this field 559 // remain set until they are cleared by writing 1 to them. No 560 // abstract command is started until the value is reset to 0. 561 // 562 // This field only contains a valid value if busy is 0. 563 // 564 // 0 (none): No error. 565 // 566 // 1 (busy): An abstract command was executing while command, 567 // abstractcs, or abstractauto was written, or when one of the 568 // data or progbuf registers was read or written. This status is 569 // only written if cmderr contains 0. 570 // 571 // 2 (not supported): The requested command is not supported, 572 // regardless of whether the hart is running or not. 573 // 574 // 3 (exception): An exception occurred while executing the 575 // command (e.g. while executing the Program Buffer). 576 // 577 // 4 (halt/resume): The abstract command couldn’t execute because 578 // the hart wasn’t in the required state (running/halted), or 579 // unavailable. 580 // 581 // 5 (bus): The abstract command failed due to a bus error (e.g. 582 // alignment, access size, or timeout). 583 // 584 // 7 (other): The command failed for another reason. 585 // 586 // Note: Hazard3 does not set values 5 or 7. Load/store 587 // instructions in the program buffer raise an exception when they 588 // encounter a bus fault, setting cmderr=3. 589 #define RISCV_DM_ABSTRACTS_CMDERR_RESET _u(0x0) 590 #define RISCV_DM_ABSTRACTS_CMDERR_BITS _u(0x00000700) 591 #define RISCV_DM_ABSTRACTS_CMDERR_MSB _u(10) 592 #define RISCV_DM_ABSTRACTS_CMDERR_LSB _u(8) 593 #define RISCV_DM_ABSTRACTS_CMDERR_ACCESS "WC" 594 // ----------------------------------------------------------------------------- 595 // Field : RISCV_DM_ABSTRACTS_DATACOUNT 596 // Description : Number of data registers that are implemented as part of the 597 // abstract command interface. 598 #define RISCV_DM_ABSTRACTS_DATACOUNT_RESET _u(0x1) 599 #define RISCV_DM_ABSTRACTS_DATACOUNT_BITS _u(0x0000000f) 600 #define RISCV_DM_ABSTRACTS_DATACOUNT_MSB _u(3) 601 #define RISCV_DM_ABSTRACTS_DATACOUNT_LSB _u(0) 602 #define RISCV_DM_ABSTRACTS_DATACOUNT_ACCESS "RO" 603 // ============================================================================= 604 // Register : RISCV_DM_COMMAND 605 // Description : Writes to this register cause the corresponding abstract 606 // command to be executed. 607 // 608 // Writing this register while an abstract command is executing 609 // causes cmderr to be set to 1 (busy) if it is 0. 610 // 611 // If cmderr is non-zero, writes to this register are ignored. 612 #define RISCV_DM_COMMAND_OFFSET _u(0x0000005c) 613 #define RISCV_DM_COMMAND_BITS _u(0xff7fffff) 614 #define RISCV_DM_COMMAND_RESET _u(0x00000000) 615 // ----------------------------------------------------------------------------- 616 // Field : RISCV_DM_COMMAND_CMDTYPE 617 // Description : On Hazard3 this field must be 0 (Access Register) 618 #define RISCV_DM_COMMAND_CMDTYPE_RESET _u(0x00) 619 #define RISCV_DM_COMMAND_CMDTYPE_BITS _u(0xff000000) 620 #define RISCV_DM_COMMAND_CMDTYPE_MSB _u(31) 621 #define RISCV_DM_COMMAND_CMDTYPE_LSB _u(24) 622 #define RISCV_DM_COMMAND_CMDTYPE_ACCESS "WO" 623 // ----------------------------------------------------------------------------- 624 // Field : RISCV_DM_COMMAND_AARSIZE 625 // Description : On Hazard3 this field must be 2 (32-bit register access) 626 #define RISCV_DM_COMMAND_AARSIZE_RESET _u(0x0) 627 #define RISCV_DM_COMMAND_AARSIZE_BITS _u(0x00700000) 628 #define RISCV_DM_COMMAND_AARSIZE_MSB _u(22) 629 #define RISCV_DM_COMMAND_AARSIZE_LSB _u(20) 630 #define RISCV_DM_COMMAND_AARSIZE_ACCESS "WO" 631 // ----------------------------------------------------------------------------- 632 // Field : RISCV_DM_COMMAND_AARPOSTINCREMENT 633 // Description : On Hazard3 this field must be 0 (no post-increment of regno) 634 #define RISCV_DM_COMMAND_AARPOSTINCREMENT_RESET _u(0x0) 635 #define RISCV_DM_COMMAND_AARPOSTINCREMENT_BITS _u(0x00080000) 636 #define RISCV_DM_COMMAND_AARPOSTINCREMENT_MSB _u(19) 637 #define RISCV_DM_COMMAND_AARPOSTINCREMENT_LSB _u(19) 638 #define RISCV_DM_COMMAND_AARPOSTINCREMENT_ACCESS "WO" 639 // ----------------------------------------------------------------------------- 640 // Field : RISCV_DM_COMMAND_POSTEXEC 641 // Description : 0: No effect. 642 // 643 // 1: Execute the program in the Program Buffer exactly once after 644 // performing the transfer, if any. 645 #define RISCV_DM_COMMAND_POSTEXEC_RESET _u(0x0) 646 #define RISCV_DM_COMMAND_POSTEXEC_BITS _u(0x00040000) 647 #define RISCV_DM_COMMAND_POSTEXEC_MSB _u(18) 648 #define RISCV_DM_COMMAND_POSTEXEC_LSB _u(18) 649 #define RISCV_DM_COMMAND_POSTEXEC_ACCESS "WO" 650 // ----------------------------------------------------------------------------- 651 // Field : RISCV_DM_COMMAND_TRANSFER 652 // Description : 0: Don’t do the operation specified by write. 653 // 654 // 1: Do the operation specified by write. 655 // 656 // This bit can be used to just execute the Program Buffer without 657 // having to worry about placing valid values into aarsize or 658 // regno. 659 #define RISCV_DM_COMMAND_TRANSFER_RESET _u(0x0) 660 #define RISCV_DM_COMMAND_TRANSFER_BITS _u(0x00020000) 661 #define RISCV_DM_COMMAND_TRANSFER_MSB _u(17) 662 #define RISCV_DM_COMMAND_TRANSFER_LSB _u(17) 663 #define RISCV_DM_COMMAND_TRANSFER_ACCESS "WO" 664 // ----------------------------------------------------------------------------- 665 // Field : RISCV_DM_COMMAND_WRITE 666 // Description : When transfer is set: 667 // 668 // 0: Copy data from the specified register into data0. 669 // 670 // 1: Copy data from data0 into the specified register. 671 #define RISCV_DM_COMMAND_WRITE_RESET _u(0x0) 672 #define RISCV_DM_COMMAND_WRITE_BITS _u(0x00010000) 673 #define RISCV_DM_COMMAND_WRITE_MSB _u(16) 674 #define RISCV_DM_COMMAND_WRITE_LSB _u(16) 675 #define RISCV_DM_COMMAND_WRITE_ACCESS "WO" 676 // ----------------------------------------------------------------------------- 677 // Field : RISCV_DM_COMMAND_REGNO 678 // Description : Number of the register to access. 679 // 680 // On Hazard3 this must be in the range 0x1000 through 0x101f 681 // inclusive, referring to GPRs x0 through x31. 682 #define RISCV_DM_COMMAND_REGNO_RESET _u(0x0000) 683 #define RISCV_DM_COMMAND_REGNO_BITS _u(0x0000ffff) 684 #define RISCV_DM_COMMAND_REGNO_MSB _u(15) 685 #define RISCV_DM_COMMAND_REGNO_LSB _u(0) 686 #define RISCV_DM_COMMAND_REGNO_ACCESS "WO" 687 // ============================================================================= 688 // Register : RISCV_DM_ABSTRACTAUTO 689 // Description : Abstract Command Autoexec. Writing this register while an 690 // abstract command is executing causes cmderr to be set to 1 691 // (busy) if it is 0. 692 #define RISCV_DM_ABSTRACTAUTO_OFFSET _u(0x00000060) 693 #define RISCV_DM_ABSTRACTAUTO_BITS _u(0xffff8fff) 694 #define RISCV_DM_ABSTRACTAUTO_RESET _u(0x00000000) 695 // ----------------------------------------------------------------------------- 696 // Field : RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF 697 // Description : When a bit in this field is 1, read or write accesses to the 698 // corresponding progbuf word cause the command in command to be 699 // executed again. 700 // 701 // Hazard3 implements only the two least-significant bits of this 702 // field (for the two-entry progbuf) 703 #define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_RESET _u(0x00000) 704 #define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_BITS _u(0xffff8000) 705 #define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_MSB _u(31) 706 #define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_LSB _u(15) 707 #define RISCV_DM_ABSTRACTAUTO_AUTOEXECPROGBUF_ACCESS "RW" 708 // ----------------------------------------------------------------------------- 709 // Field : RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA 710 // Description : When a bit in this field is 1, read or write accesses to the 711 // corresponding data word cause the command in command to be 712 // executed again. 713 // 714 // Hazard3 implements only the least-significant bit of this 715 // field. 716 #define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_RESET _u(0x000) 717 #define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_BITS _u(0x00000fff) 718 #define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_MSB _u(11) 719 #define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_LSB _u(0) 720 #define RISCV_DM_ABSTRACTAUTO_AUTOEXEDDATA_ACCESS "RW" 721 // ============================================================================= 722 // Register : RISCV_DM_NEXTDM 723 // Description : If there is more than one DM accessible on this DMI, this 724 // register contains the base address of thenext one in the chain, 725 // or 0 if this is the last one in the chain. 726 #define RISCV_DM_NEXTDM_OFFSET _u(0x00000074) 727 #define RISCV_DM_NEXTDM_BITS _u(0xffffffff) 728 #define RISCV_DM_NEXTDM_RESET _u(0x00000000) 729 #define RISCV_DM_NEXTDM_MSB _u(31) 730 #define RISCV_DM_NEXTDM_LSB _u(0) 731 #define RISCV_DM_NEXTDM_ACCESS "RO" 732 // ============================================================================= 733 // Register : RISCV_DM_PROGBUF0 734 // Description : progbuf0 through progbuf15 provide read/write access to the 735 // program buffer. abstractcs.progbufsize indicates how many of 736 // them are implemented starting at progbuf0, counting up. 737 // 738 // (Hazard3 implements a 2-word program buffer.) 739 #define RISCV_DM_PROGBUF0_OFFSET _u(0x00000080) 740 #define RISCV_DM_PROGBUF0_BITS _u(0xffffffff) 741 #define RISCV_DM_PROGBUF0_RESET _u(0x00000000) 742 #define RISCV_DM_PROGBUF0_MSB _u(31) 743 #define RISCV_DM_PROGBUF0_LSB _u(0) 744 #define RISCV_DM_PROGBUF0_ACCESS "RW" 745 // ============================================================================= 746 // Register : RISCV_DM_PROGBUF1 747 // Description : progbuf0 through progbuf15 provide read/write access to the 748 // program buffer. abstractcs.progbufsize indicates how many of 749 // them are implemented starting at progbuf0, counting up. 750 // 751 // (Hazard3 implements a 2-word program buffer.) 752 #define RISCV_DM_PROGBUF1_OFFSET _u(0x00000084) 753 #define RISCV_DM_PROGBUF1_BITS _u(0xffffffff) 754 #define RISCV_DM_PROGBUF1_RESET _u(0x00000000) 755 #define RISCV_DM_PROGBUF1_MSB _u(31) 756 #define RISCV_DM_PROGBUF1_LSB _u(0) 757 #define RISCV_DM_PROGBUF1_ACCESS "RW" 758 // ============================================================================= 759 // Register : RISCV_DM_SBCS 760 // Description : System Bus Access Control and Status 761 #define RISCV_DM_SBCS_OFFSET _u(0x000000e0) 762 #define RISCV_DM_SBCS_BITS _u(0xe07fffff) 763 #define RISCV_DM_SBCS_RESET _u(0x20000407) 764 // ----------------------------------------------------------------------------- 765 // Field : RISCV_DM_SBCS_SBVERSION 766 // Description : 1: The System Bus interface conforms to version 0.13.2 of the 767 // RISC-V debug spec. 768 #define RISCV_DM_SBCS_SBVERSION_RESET _u(0x1) 769 #define RISCV_DM_SBCS_SBVERSION_BITS _u(0xe0000000) 770 #define RISCV_DM_SBCS_SBVERSION_MSB _u(31) 771 #define RISCV_DM_SBCS_SBVERSION_LSB _u(29) 772 #define RISCV_DM_SBCS_SBVERSION_ACCESS "RO" 773 // ----------------------------------------------------------------------------- 774 // Field : RISCV_DM_SBCS_SBBUSYERROR 775 // Description : Set when the debugger attempts to read data while a read is in 776 // progress, or when the debugger initiates a new access while one 777 // is already in progress (while sbbusy is set). It remains set 778 // until it’s explicitly cleared by the debugger. 779 // 780 // While this field is set, no more system bus accesses can be 781 // initiated by the Debug Module. 782 #define RISCV_DM_SBCS_SBBUSYERROR_RESET _u(0x0) 783 #define RISCV_DM_SBCS_SBBUSYERROR_BITS _u(0x00400000) 784 #define RISCV_DM_SBCS_SBBUSYERROR_MSB _u(22) 785 #define RISCV_DM_SBCS_SBBUSYERROR_LSB _u(22) 786 #define RISCV_DM_SBCS_SBBUSYERROR_ACCESS "WC" 787 // ----------------------------------------------------------------------------- 788 // Field : RISCV_DM_SBCS_SBBUSY 789 // Description : When 1, indicates the system bus master is busy. (Whether the 790 // system bus itself is busy is related, but not the same thing.) 791 // This bit goes high immediately when a read or write is 792 // requested for any reason, and does not go low until the access 793 // is fully completed. 794 // 795 // Writes to sbcs while sbbusy is high result in undefined 796 // behavior. A debugger must not write to sbcs until it reads 797 // sbbusy as 0. 798 #define RISCV_DM_SBCS_SBBUSY_RESET _u(0x0) 799 #define RISCV_DM_SBCS_SBBUSY_BITS _u(0x00200000) 800 #define RISCV_DM_SBCS_SBBUSY_MSB _u(21) 801 #define RISCV_DM_SBCS_SBBUSY_LSB _u(21) 802 #define RISCV_DM_SBCS_SBBUSY_ACCESS "RO" 803 // ----------------------------------------------------------------------------- 804 // Field : RISCV_DM_SBCS_SBREADONADDR 805 // Description : When 1, every write to sbaddress0 automatically triggers a 806 // system bus read at the new address. 807 #define RISCV_DM_SBCS_SBREADONADDR_RESET _u(0x0) 808 #define RISCV_DM_SBCS_SBREADONADDR_BITS _u(0x00100000) 809 #define RISCV_DM_SBCS_SBREADONADDR_MSB _u(20) 810 #define RISCV_DM_SBCS_SBREADONADDR_LSB _u(20) 811 #define RISCV_DM_SBCS_SBREADONADDR_ACCESS "RW" 812 // ----------------------------------------------------------------------------- 813 // Field : RISCV_DM_SBCS_SBACCESS 814 // Description : Select the access size to use for system bus accesses. 815 // 816 // 0: 8-bit 817 // 818 // 1: 16-bit 819 // 820 // 2: 32-bit 821 // 822 // 3: 64-bit 823 // 824 // 4: 128-bit 825 // 826 // If sbaccess has an unsupported value when the DM starts a bus 827 // access, the access is not per formed and sberror is set to 4. 828 // (On Hazard3 the supported values are 8-bit, 16-bit and 32-bit.) 829 #define RISCV_DM_SBCS_SBACCESS_RESET _u(0x0) 830 #define RISCV_DM_SBCS_SBACCESS_BITS _u(0x000e0000) 831 #define RISCV_DM_SBCS_SBACCESS_MSB _u(19) 832 #define RISCV_DM_SBCS_SBACCESS_LSB _u(17) 833 #define RISCV_DM_SBCS_SBACCESS_ACCESS "RW" 834 // ----------------------------------------------------------------------------- 835 // Field : RISCV_DM_SBCS_SBAUTOINCREMENT 836 // Description : When 1, sbaddress is incremented by the access size (in bytes) 837 // selected in sbaccess after every system bus access. 838 #define RISCV_DM_SBCS_SBAUTOINCREMENT_RESET _u(0x0) 839 #define RISCV_DM_SBCS_SBAUTOINCREMENT_BITS _u(0x00010000) 840 #define RISCV_DM_SBCS_SBAUTOINCREMENT_MSB _u(16) 841 #define RISCV_DM_SBCS_SBAUTOINCREMENT_LSB _u(16) 842 #define RISCV_DM_SBCS_SBAUTOINCREMENT_ACCESS "RW" 843 // ----------------------------------------------------------------------------- 844 // Field : RISCV_DM_SBCS_SBREADONDATA 845 // Description : When 1, every read from sbdata0 automatically triggers a system 846 // bus read at the (possibly auto- incremented) address. 847 #define RISCV_DM_SBCS_SBREADONDATA_RESET _u(0x0) 848 #define RISCV_DM_SBCS_SBREADONDATA_BITS _u(0x00008000) 849 #define RISCV_DM_SBCS_SBREADONDATA_MSB _u(15) 850 #define RISCV_DM_SBCS_SBREADONDATA_LSB _u(15) 851 #define RISCV_DM_SBCS_SBREADONDATA_ACCESS "RW" 852 // ----------------------------------------------------------------------------- 853 // Field : RISCV_DM_SBCS_SBERROR 854 // Description : When the Debug Module’s system bus master encounters an error, 855 // this field gets set. The bits in this field remain set until 856 // they are cleared by writing 1 to them. While this field is non- 857 // zero, no more system bus accesses can be initiated by the Debug 858 // Module. 859 // 860 // An implementation may report “Other” (7) for any error 861 // condition. (Hazard3 does not use this value for any errors.) 862 // 863 // 0: There was no bus error. 864 // 865 // 1: There was a timeout. 866 // 867 // 2: A bad address was accessed. 868 // 869 // 3: There was an alignment error. 870 // 871 // 4: An access of unsupported size was requested. 872 // 873 // 7: Other. 874 // 875 // Hazard3 raises an alignment error for any non-naturally-aligned 876 // bus transfer which would otherwise be a valid transfer. 877 #define RISCV_DM_SBCS_SBERROR_RESET _u(0x0) 878 #define RISCV_DM_SBCS_SBERROR_BITS _u(0x00007000) 879 #define RISCV_DM_SBCS_SBERROR_MSB _u(14) 880 #define RISCV_DM_SBCS_SBERROR_LSB _u(12) 881 #define RISCV_DM_SBCS_SBERROR_ACCESS "WC" 882 // ----------------------------------------------------------------------------- 883 // Field : RISCV_DM_SBCS_SBASIZE 884 // Description : Width of system bus addresses in bits. (0 indicates there is no 885 // bus access support.) 886 #define RISCV_DM_SBCS_SBASIZE_RESET _u(0x20) 887 #define RISCV_DM_SBCS_SBASIZE_BITS _u(0x00000fe0) 888 #define RISCV_DM_SBCS_SBASIZE_MSB _u(11) 889 #define RISCV_DM_SBCS_SBASIZE_LSB _u(5) 890 #define RISCV_DM_SBCS_SBASIZE_ACCESS "RO" 891 // ----------------------------------------------------------------------------- 892 // Field : RISCV_DM_SBCS_SBACCESS128 893 // Description : 1 when 128-bit system bus accesses are supported. 894 #define RISCV_DM_SBCS_SBACCESS128_RESET _u(0x0) 895 #define RISCV_DM_SBCS_SBACCESS128_BITS _u(0x00000010) 896 #define RISCV_DM_SBCS_SBACCESS128_MSB _u(4) 897 #define RISCV_DM_SBCS_SBACCESS128_LSB _u(4) 898 #define RISCV_DM_SBCS_SBACCESS128_ACCESS "RO" 899 // ----------------------------------------------------------------------------- 900 // Field : RISCV_DM_SBCS_SBACCESS64 901 // Description : 1 when 64-bit system bus accesses are supported. 902 #define RISCV_DM_SBCS_SBACCESS64_RESET _u(0x0) 903 #define RISCV_DM_SBCS_SBACCESS64_BITS _u(0x00000008) 904 #define RISCV_DM_SBCS_SBACCESS64_MSB _u(3) 905 #define RISCV_DM_SBCS_SBACCESS64_LSB _u(3) 906 #define RISCV_DM_SBCS_SBACCESS64_ACCESS "RO" 907 // ----------------------------------------------------------------------------- 908 // Field : RISCV_DM_SBCS_SBACCESS32 909 // Description : 1 when 32-bit system bus accesses are supported. 910 #define RISCV_DM_SBCS_SBACCESS32_RESET _u(0x1) 911 #define RISCV_DM_SBCS_SBACCESS32_BITS _u(0x00000004) 912 #define RISCV_DM_SBCS_SBACCESS32_MSB _u(2) 913 #define RISCV_DM_SBCS_SBACCESS32_LSB _u(2) 914 #define RISCV_DM_SBCS_SBACCESS32_ACCESS "RO" 915 // ----------------------------------------------------------------------------- 916 // Field : RISCV_DM_SBCS_SBACCESS16 917 // Description : 1 when 16-bit system bus accesses are supported. 918 #define RISCV_DM_SBCS_SBACCESS16_RESET _u(0x1) 919 #define RISCV_DM_SBCS_SBACCESS16_BITS _u(0x00000002) 920 #define RISCV_DM_SBCS_SBACCESS16_MSB _u(1) 921 #define RISCV_DM_SBCS_SBACCESS16_LSB _u(1) 922 #define RISCV_DM_SBCS_SBACCESS16_ACCESS "RO" 923 // ----------------------------------------------------------------------------- 924 // Field : RISCV_DM_SBCS_SBACCESS8 925 // Description : 1 when 8-bit system bus accesses are supported. 926 #define RISCV_DM_SBCS_SBACCESS8_RESET _u(0x1) 927 #define RISCV_DM_SBCS_SBACCESS8_BITS _u(0x00000001) 928 #define RISCV_DM_SBCS_SBACCESS8_MSB _u(0) 929 #define RISCV_DM_SBCS_SBACCESS8_LSB _u(0) 930 #define RISCV_DM_SBCS_SBACCESS8_ACCESS "RO" 931 // ============================================================================= 932 // Register : RISCV_DM_SBADDRESS0 933 // Description : System Bus Address 31:0 934 // 935 // When the system bus master is busy, writes to this register 936 // will set sbbusyerror and don’t do anything else. 937 // 938 // If sberror is 0, sbbusyerror is 0, and sbreadonaddr is set then 939 // writes to this register start the following: 940 // 941 // 1. Set sbbusy. 942 // 943 // 2. Perform a bus read from the new value of sbaddress. 944 // 945 // 3. If the read succeeded and sbautoincrement is set, increment 946 // sbaddress. 947 // 948 // 4. Clear sbbusy. 949 #define RISCV_DM_SBADDRESS0_OFFSET _u(0x000000e4) 950 #define RISCV_DM_SBADDRESS0_BITS _u(0xffffffff) 951 #define RISCV_DM_SBADDRESS0_RESET _u(0x00000000) 952 // ----------------------------------------------------------------------------- 953 // Field : RISCV_DM_SBADDRESS0_ADDRESS 954 // Description : Accesses bits 31:0 of the physical address in sbaddress. 955 #define RISCV_DM_SBADDRESS0_ADDRESS_RESET _u(0x00000000) 956 #define RISCV_DM_SBADDRESS0_ADDRESS_BITS _u(0xffffffff) 957 #define RISCV_DM_SBADDRESS0_ADDRESS_MSB _u(31) 958 #define RISCV_DM_SBADDRESS0_ADDRESS_LSB _u(0) 959 #define RISCV_DM_SBADDRESS0_ADDRESS_ACCESS "RW" 960 // ============================================================================= 961 // Register : RISCV_DM_SBDATA0 962 // Description : System Bus Data 31:0 963 // 964 // Any successful system bus read updates sbdata. If the width of 965 // the read access is less than the width of sbdata, the contents 966 // of the remaining high bits may take on any value. 967 // 968 // If sberror or sbbusyerror both aren’t 0 then accesses do 969 // nothing. 970 // 971 // If the bus master is busy then accesses set sbbusyerror, and 972 // don’t do anything else. Writes to this register start the 973 // following: 974 // 975 // 1. Set sbbusy. 976 // 977 // 2. Perform a bus write of the new value of sbdata to sbaddress. 978 // 979 // 3. If the write succeeded and sbautoincrement is set, increment 980 // sbaddress. 981 // 982 // 4. Clear sbbusy. 983 // 984 // Reads from this register start the following: 985 // 986 // 1. “Return” the data. 987 // 988 // 2. Set sbbusy. 989 // 990 // 3. If sbreadondata is set, perform a system bus read from the 991 // address contained in sbaddress, placing the result in sbdata. 992 // 993 // 4. If the read was successful, and sbautoincrement is set, 994 // increment sbaddress. 995 // 996 // 5. Clear sbbusy. 997 #define RISCV_DM_SBDATA0_OFFSET _u(0x000000f0) 998 #define RISCV_DM_SBDATA0_BITS _u(0xffffffff) 999 #define RISCV_DM_SBDATA0_RESET _u(0x00000000) 1000 // ----------------------------------------------------------------------------- 1001 // Field : RISCV_DM_SBDATA0_DATA 1002 #define RISCV_DM_SBDATA0_DATA_RESET _u(0x00000000) 1003 #define RISCV_DM_SBDATA0_DATA_BITS _u(0xffffffff) 1004 #define RISCV_DM_SBDATA0_DATA_MSB _u(31) 1005 #define RISCV_DM_SBDATA0_DATA_LSB _u(0) 1006 #define RISCV_DM_SBDATA0_DATA_ACCESS "RW" 1007 // ============================================================================= 1008 // Register : RISCV_DM_HALTSUM0 1009 // Description : Each bit in this read-only register indicates whether one 1010 // specific hart is halted or not. Unavailable/nonexistent harts 1011 // are not considered to be halted. 1012 // 1013 // On RP2350, only the two LSBs of this register are implemented, 1014 // one for each core/hart. 1015 // 1016 // This entire register is read-only. 1017 #define RISCV_DM_HALTSUM0_OFFSET _u(0x00000100) 1018 #define RISCV_DM_HALTSUM0_BITS _u(0xffffffff) 1019 #define RISCV_DM_HALTSUM0_RESET _u(0x00000000) 1020 #define RISCV_DM_HALTSUM0_MSB _u(31) 1021 #define RISCV_DM_HALTSUM0_LSB _u(0) 1022 #define RISCV_DM_HALTSUM0_ACCESS "RO" 1023 // ============================================================================= 1024 #endif // _HARDWARE_REGS_RISCV_DM_H 1025 1026