1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef _HARDWARE_STRUCTS_RESETS_H 9 #define _HARDWARE_STRUCTS_RESETS_H 10 11 /** 12 * \file rp2350/resets.h 13 */ 14 15 #include "hardware/address_mapped.h" 16 #include "hardware/regs/resets.h" 17 18 // Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_resets 19 // 20 // The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature) 21 // _REG_(x) will link to the corresponding register in hardware/regs/resets.h. 22 // 23 // Bit-field descriptions are of the form: 24 // BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION 25 26 /** \brief Resettable component numbers on RP2350 (used as typedef \ref reset_num_t) 27 * \ingroup hardware_resets 28 */ 29 typedef enum reset_num_rp2350 { 30 RESET_ADC = 0, ///< Select ADC to be reset 31 RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset 32 RESET_DMA = 2, ///< Select DMA to be reset 33 RESET_HSTX = 3, ///< Select HSTX to be reset 34 RESET_I2C0 = 4, ///< Select I2C0 to be reset 35 RESET_I2C1 = 5, ///< Select I2C1 to be reset 36 RESET_IO_BANK0 = 6, ///< Select IO_BANK0 to be reset 37 RESET_IO_QSPI = 7, ///< Select IO_QSPI to be reset 38 RESET_JTAG = 8, ///< Select JTAG to be reset 39 RESET_PADS_BANK0 = 9, ///< Select PADS_BANK0 to be reset 40 RESET_PADS_QSPI = 10, ///< Select PADS_QSPI to be reset 41 RESET_PIO0 = 11, ///< Select PIO0 to be reset 42 RESET_PIO1 = 12, ///< Select PIO1 to be reset 43 RESET_PIO2 = 13, ///< Select PIO2 to be reset 44 RESET_PLL_SYS = 14, ///< Select PLL_SYS to be reset 45 RESET_PLL_USB = 15, ///< Select PLL_USB to be reset 46 RESET_PWM = 16, ///< Select PWM to be reset 47 RESET_SHA256 = 17, ///< Select SHA256 to be reset 48 RESET_SPI0 = 18, ///< Select SPI0 to be reset 49 RESET_SPI1 = 19, ///< Select SPI1 to be reset 50 RESET_SYSCFG = 20, ///< Select SYSCFG to be reset 51 RESET_SYSINFO = 21, ///< Select SYSINFO to be reset 52 RESET_TBMAN = 22, ///< Select TBMAN to be reset 53 RESET_TIMER0 = 23, ///< Select TIMER0 to be reset 54 RESET_TIMER1 = 24, ///< Select TIMER1 to be reset 55 RESET_TRNG = 25, ///< Select TRNG to be reset 56 RESET_UART0 = 26, ///< Select UART0 to be reset 57 RESET_UART1 = 27, ///< Select UART1 to be reset 58 RESET_USBCTRL = 28, ///< Select USBCTRL to be reset 59 RESET_COUNT 60 } reset_num_t; 61 62 /// \tag::resets_hw[] 63 typedef struct { 64 _REG_(RESETS_RESET_OFFSET) // RESETS_RESET 65 // 0x10000000 [28] USBCTRL (1) 66 // 0x08000000 [27] UART1 (1) 67 // 0x04000000 [26] UART0 (1) 68 // 0x02000000 [25] TRNG (1) 69 // 0x01000000 [24] TIMER1 (1) 70 // 0x00800000 [23] TIMER0 (1) 71 // 0x00400000 [22] TBMAN (1) 72 // 0x00200000 [21] SYSINFO (1) 73 // 0x00100000 [20] SYSCFG (1) 74 // 0x00080000 [19] SPI1 (1) 75 // 0x00040000 [18] SPI0 (1) 76 // 0x00020000 [17] SHA256 (1) 77 // 0x00010000 [16] PWM (1) 78 // 0x00008000 [15] PLL_USB (1) 79 // 0x00004000 [14] PLL_SYS (1) 80 // 0x00002000 [13] PIO2 (1) 81 // 0x00001000 [12] PIO1 (1) 82 // 0x00000800 [11] PIO0 (1) 83 // 0x00000400 [10] PADS_QSPI (1) 84 // 0x00000200 [9] PADS_BANK0 (1) 85 // 0x00000100 [8] JTAG (1) 86 // 0x00000080 [7] IO_QSPI (1) 87 // 0x00000040 [6] IO_BANK0 (1) 88 // 0x00000020 [5] I2C1 (1) 89 // 0x00000010 [4] I2C0 (1) 90 // 0x00000008 [3] HSTX (1) 91 // 0x00000004 [2] DMA (1) 92 // 0x00000002 [1] BUSCTRL (1) 93 // 0x00000001 [0] ADC (1) 94 io_rw_32 reset; 95 96 _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL 97 // 0x10000000 [28] USBCTRL (0) 98 // 0x08000000 [27] UART1 (0) 99 // 0x04000000 [26] UART0 (0) 100 // 0x02000000 [25] TRNG (0) 101 // 0x01000000 [24] TIMER1 (0) 102 // 0x00800000 [23] TIMER0 (0) 103 // 0x00400000 [22] TBMAN (0) 104 // 0x00200000 [21] SYSINFO (0) 105 // 0x00100000 [20] SYSCFG (0) 106 // 0x00080000 [19] SPI1 (0) 107 // 0x00040000 [18] SPI0 (0) 108 // 0x00020000 [17] SHA256 (0) 109 // 0x00010000 [16] PWM (0) 110 // 0x00008000 [15] PLL_USB (0) 111 // 0x00004000 [14] PLL_SYS (0) 112 // 0x00002000 [13] PIO2 (0) 113 // 0x00001000 [12] PIO1 (0) 114 // 0x00000800 [11] PIO0 (0) 115 // 0x00000400 [10] PADS_QSPI (0) 116 // 0x00000200 [9] PADS_BANK0 (0) 117 // 0x00000100 [8] JTAG (0) 118 // 0x00000080 [7] IO_QSPI (0) 119 // 0x00000040 [6] IO_BANK0 (0) 120 // 0x00000020 [5] I2C1 (0) 121 // 0x00000010 [4] I2C0 (0) 122 // 0x00000008 [3] HSTX (0) 123 // 0x00000004 [2] DMA (0) 124 // 0x00000002 [1] BUSCTRL (0) 125 // 0x00000001 [0] ADC (0) 126 io_rw_32 wdsel; 127 128 _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE 129 // 0x10000000 [28] USBCTRL (0) 130 // 0x08000000 [27] UART1 (0) 131 // 0x04000000 [26] UART0 (0) 132 // 0x02000000 [25] TRNG (0) 133 // 0x01000000 [24] TIMER1 (0) 134 // 0x00800000 [23] TIMER0 (0) 135 // 0x00400000 [22] TBMAN (0) 136 // 0x00200000 [21] SYSINFO (0) 137 // 0x00100000 [20] SYSCFG (0) 138 // 0x00080000 [19] SPI1 (0) 139 // 0x00040000 [18] SPI0 (0) 140 // 0x00020000 [17] SHA256 (0) 141 // 0x00010000 [16] PWM (0) 142 // 0x00008000 [15] PLL_USB (0) 143 // 0x00004000 [14] PLL_SYS (0) 144 // 0x00002000 [13] PIO2 (0) 145 // 0x00001000 [12] PIO1 (0) 146 // 0x00000800 [11] PIO0 (0) 147 // 0x00000400 [10] PADS_QSPI (0) 148 // 0x00000200 [9] PADS_BANK0 (0) 149 // 0x00000100 [8] JTAG (0) 150 // 0x00000080 [7] IO_QSPI (0) 151 // 0x00000040 [6] IO_BANK0 (0) 152 // 0x00000020 [5] I2C1 (0) 153 // 0x00000010 [4] I2C0 (0) 154 // 0x00000008 [3] HSTX (0) 155 // 0x00000004 [2] DMA (0) 156 // 0x00000002 [1] BUSCTRL (0) 157 // 0x00000001 [0] ADC (0) 158 io_ro_32 reset_done; 159 } resets_hw_t; 160 /// \end::resets_hw[] 161 162 #define resets_hw ((resets_hw_t *)RESETS_BASE) 163 static_assert(sizeof (resets_hw_t) == 0x000c, ""); 164 165 #endif // _HARDWARE_STRUCTS_RESETS_H 166 167