1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : RESETS 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_RESETS_H 14 #define _HARDWARE_REGS_RESETS_H 15 // ============================================================================= 16 // Register : RESETS_RESET 17 // Description : Reset control. If a bit is set it means the peripheral is in 18 // reset. 0 means the peripheral's reset is deasserted. 19 #define RESETS_RESET_OFFSET _u(0x00000000) 20 #define RESETS_RESET_BITS _u(0x01ffffff) 21 #define RESETS_RESET_RESET _u(0x01ffffff) 22 // ----------------------------------------------------------------------------- 23 // Field : RESETS_RESET_USBCTRL 24 #define RESETS_RESET_USBCTRL_RESET _u(0x1) 25 #define RESETS_RESET_USBCTRL_BITS _u(0x01000000) 26 #define RESETS_RESET_USBCTRL_MSB _u(24) 27 #define RESETS_RESET_USBCTRL_LSB _u(24) 28 #define RESETS_RESET_USBCTRL_ACCESS "RW" 29 // ----------------------------------------------------------------------------- 30 // Field : RESETS_RESET_UART1 31 #define RESETS_RESET_UART1_RESET _u(0x1) 32 #define RESETS_RESET_UART1_BITS _u(0x00800000) 33 #define RESETS_RESET_UART1_MSB _u(23) 34 #define RESETS_RESET_UART1_LSB _u(23) 35 #define RESETS_RESET_UART1_ACCESS "RW" 36 // ----------------------------------------------------------------------------- 37 // Field : RESETS_RESET_UART0 38 #define RESETS_RESET_UART0_RESET _u(0x1) 39 #define RESETS_RESET_UART0_BITS _u(0x00400000) 40 #define RESETS_RESET_UART0_MSB _u(22) 41 #define RESETS_RESET_UART0_LSB _u(22) 42 #define RESETS_RESET_UART0_ACCESS "RW" 43 // ----------------------------------------------------------------------------- 44 // Field : RESETS_RESET_TIMER 45 #define RESETS_RESET_TIMER_RESET _u(0x1) 46 #define RESETS_RESET_TIMER_BITS _u(0x00200000) 47 #define RESETS_RESET_TIMER_MSB _u(21) 48 #define RESETS_RESET_TIMER_LSB _u(21) 49 #define RESETS_RESET_TIMER_ACCESS "RW" 50 // ----------------------------------------------------------------------------- 51 // Field : RESETS_RESET_TBMAN 52 #define RESETS_RESET_TBMAN_RESET _u(0x1) 53 #define RESETS_RESET_TBMAN_BITS _u(0x00100000) 54 #define RESETS_RESET_TBMAN_MSB _u(20) 55 #define RESETS_RESET_TBMAN_LSB _u(20) 56 #define RESETS_RESET_TBMAN_ACCESS "RW" 57 // ----------------------------------------------------------------------------- 58 // Field : RESETS_RESET_SYSINFO 59 #define RESETS_RESET_SYSINFO_RESET _u(0x1) 60 #define RESETS_RESET_SYSINFO_BITS _u(0x00080000) 61 #define RESETS_RESET_SYSINFO_MSB _u(19) 62 #define RESETS_RESET_SYSINFO_LSB _u(19) 63 #define RESETS_RESET_SYSINFO_ACCESS "RW" 64 // ----------------------------------------------------------------------------- 65 // Field : RESETS_RESET_SYSCFG 66 #define RESETS_RESET_SYSCFG_RESET _u(0x1) 67 #define RESETS_RESET_SYSCFG_BITS _u(0x00040000) 68 #define RESETS_RESET_SYSCFG_MSB _u(18) 69 #define RESETS_RESET_SYSCFG_LSB _u(18) 70 #define RESETS_RESET_SYSCFG_ACCESS "RW" 71 // ----------------------------------------------------------------------------- 72 // Field : RESETS_RESET_SPI1 73 #define RESETS_RESET_SPI1_RESET _u(0x1) 74 #define RESETS_RESET_SPI1_BITS _u(0x00020000) 75 #define RESETS_RESET_SPI1_MSB _u(17) 76 #define RESETS_RESET_SPI1_LSB _u(17) 77 #define RESETS_RESET_SPI1_ACCESS "RW" 78 // ----------------------------------------------------------------------------- 79 // Field : RESETS_RESET_SPI0 80 #define RESETS_RESET_SPI0_RESET _u(0x1) 81 #define RESETS_RESET_SPI0_BITS _u(0x00010000) 82 #define RESETS_RESET_SPI0_MSB _u(16) 83 #define RESETS_RESET_SPI0_LSB _u(16) 84 #define RESETS_RESET_SPI0_ACCESS "RW" 85 // ----------------------------------------------------------------------------- 86 // Field : RESETS_RESET_RTC 87 #define RESETS_RESET_RTC_RESET _u(0x1) 88 #define RESETS_RESET_RTC_BITS _u(0x00008000) 89 #define RESETS_RESET_RTC_MSB _u(15) 90 #define RESETS_RESET_RTC_LSB _u(15) 91 #define RESETS_RESET_RTC_ACCESS "RW" 92 // ----------------------------------------------------------------------------- 93 // Field : RESETS_RESET_PWM 94 #define RESETS_RESET_PWM_RESET _u(0x1) 95 #define RESETS_RESET_PWM_BITS _u(0x00004000) 96 #define RESETS_RESET_PWM_MSB _u(14) 97 #define RESETS_RESET_PWM_LSB _u(14) 98 #define RESETS_RESET_PWM_ACCESS "RW" 99 // ----------------------------------------------------------------------------- 100 // Field : RESETS_RESET_PLL_USB 101 #define RESETS_RESET_PLL_USB_RESET _u(0x1) 102 #define RESETS_RESET_PLL_USB_BITS _u(0x00002000) 103 #define RESETS_RESET_PLL_USB_MSB _u(13) 104 #define RESETS_RESET_PLL_USB_LSB _u(13) 105 #define RESETS_RESET_PLL_USB_ACCESS "RW" 106 // ----------------------------------------------------------------------------- 107 // Field : RESETS_RESET_PLL_SYS 108 #define RESETS_RESET_PLL_SYS_RESET _u(0x1) 109 #define RESETS_RESET_PLL_SYS_BITS _u(0x00001000) 110 #define RESETS_RESET_PLL_SYS_MSB _u(12) 111 #define RESETS_RESET_PLL_SYS_LSB _u(12) 112 #define RESETS_RESET_PLL_SYS_ACCESS "RW" 113 // ----------------------------------------------------------------------------- 114 // Field : RESETS_RESET_PIO1 115 #define RESETS_RESET_PIO1_RESET _u(0x1) 116 #define RESETS_RESET_PIO1_BITS _u(0x00000800) 117 #define RESETS_RESET_PIO1_MSB _u(11) 118 #define RESETS_RESET_PIO1_LSB _u(11) 119 #define RESETS_RESET_PIO1_ACCESS "RW" 120 // ----------------------------------------------------------------------------- 121 // Field : RESETS_RESET_PIO0 122 #define RESETS_RESET_PIO0_RESET _u(0x1) 123 #define RESETS_RESET_PIO0_BITS _u(0x00000400) 124 #define RESETS_RESET_PIO0_MSB _u(10) 125 #define RESETS_RESET_PIO0_LSB _u(10) 126 #define RESETS_RESET_PIO0_ACCESS "RW" 127 // ----------------------------------------------------------------------------- 128 // Field : RESETS_RESET_PADS_QSPI 129 #define RESETS_RESET_PADS_QSPI_RESET _u(0x1) 130 #define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200) 131 #define RESETS_RESET_PADS_QSPI_MSB _u(9) 132 #define RESETS_RESET_PADS_QSPI_LSB _u(9) 133 #define RESETS_RESET_PADS_QSPI_ACCESS "RW" 134 // ----------------------------------------------------------------------------- 135 // Field : RESETS_RESET_PADS_BANK0 136 #define RESETS_RESET_PADS_BANK0_RESET _u(0x1) 137 #define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100) 138 #define RESETS_RESET_PADS_BANK0_MSB _u(8) 139 #define RESETS_RESET_PADS_BANK0_LSB _u(8) 140 #define RESETS_RESET_PADS_BANK0_ACCESS "RW" 141 // ----------------------------------------------------------------------------- 142 // Field : RESETS_RESET_JTAG 143 #define RESETS_RESET_JTAG_RESET _u(0x1) 144 #define RESETS_RESET_JTAG_BITS _u(0x00000080) 145 #define RESETS_RESET_JTAG_MSB _u(7) 146 #define RESETS_RESET_JTAG_LSB _u(7) 147 #define RESETS_RESET_JTAG_ACCESS "RW" 148 // ----------------------------------------------------------------------------- 149 // Field : RESETS_RESET_IO_QSPI 150 #define RESETS_RESET_IO_QSPI_RESET _u(0x1) 151 #define RESETS_RESET_IO_QSPI_BITS _u(0x00000040) 152 #define RESETS_RESET_IO_QSPI_MSB _u(6) 153 #define RESETS_RESET_IO_QSPI_LSB _u(6) 154 #define RESETS_RESET_IO_QSPI_ACCESS "RW" 155 // ----------------------------------------------------------------------------- 156 // Field : RESETS_RESET_IO_BANK0 157 #define RESETS_RESET_IO_BANK0_RESET _u(0x1) 158 #define RESETS_RESET_IO_BANK0_BITS _u(0x00000020) 159 #define RESETS_RESET_IO_BANK0_MSB _u(5) 160 #define RESETS_RESET_IO_BANK0_LSB _u(5) 161 #define RESETS_RESET_IO_BANK0_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : RESETS_RESET_I2C1 164 #define RESETS_RESET_I2C1_RESET _u(0x1) 165 #define RESETS_RESET_I2C1_BITS _u(0x00000010) 166 #define RESETS_RESET_I2C1_MSB _u(4) 167 #define RESETS_RESET_I2C1_LSB _u(4) 168 #define RESETS_RESET_I2C1_ACCESS "RW" 169 // ----------------------------------------------------------------------------- 170 // Field : RESETS_RESET_I2C0 171 #define RESETS_RESET_I2C0_RESET _u(0x1) 172 #define RESETS_RESET_I2C0_BITS _u(0x00000008) 173 #define RESETS_RESET_I2C0_MSB _u(3) 174 #define RESETS_RESET_I2C0_LSB _u(3) 175 #define RESETS_RESET_I2C0_ACCESS "RW" 176 // ----------------------------------------------------------------------------- 177 // Field : RESETS_RESET_DMA 178 #define RESETS_RESET_DMA_RESET _u(0x1) 179 #define RESETS_RESET_DMA_BITS _u(0x00000004) 180 #define RESETS_RESET_DMA_MSB _u(2) 181 #define RESETS_RESET_DMA_LSB _u(2) 182 #define RESETS_RESET_DMA_ACCESS "RW" 183 // ----------------------------------------------------------------------------- 184 // Field : RESETS_RESET_BUSCTRL 185 #define RESETS_RESET_BUSCTRL_RESET _u(0x1) 186 #define RESETS_RESET_BUSCTRL_BITS _u(0x00000002) 187 #define RESETS_RESET_BUSCTRL_MSB _u(1) 188 #define RESETS_RESET_BUSCTRL_LSB _u(1) 189 #define RESETS_RESET_BUSCTRL_ACCESS "RW" 190 // ----------------------------------------------------------------------------- 191 // Field : RESETS_RESET_ADC 192 #define RESETS_RESET_ADC_RESET _u(0x1) 193 #define RESETS_RESET_ADC_BITS _u(0x00000001) 194 #define RESETS_RESET_ADC_MSB _u(0) 195 #define RESETS_RESET_ADC_LSB _u(0) 196 #define RESETS_RESET_ADC_ACCESS "RW" 197 // ============================================================================= 198 // Register : RESETS_WDSEL 199 // Description : Watchdog select. If a bit is set then the watchdog will reset 200 // this peripheral when the watchdog fires. 201 #define RESETS_WDSEL_OFFSET _u(0x00000004) 202 #define RESETS_WDSEL_BITS _u(0x01ffffff) 203 #define RESETS_WDSEL_RESET _u(0x00000000) 204 // ----------------------------------------------------------------------------- 205 // Field : RESETS_WDSEL_USBCTRL 206 #define RESETS_WDSEL_USBCTRL_RESET _u(0x0) 207 #define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000) 208 #define RESETS_WDSEL_USBCTRL_MSB _u(24) 209 #define RESETS_WDSEL_USBCTRL_LSB _u(24) 210 #define RESETS_WDSEL_USBCTRL_ACCESS "RW" 211 // ----------------------------------------------------------------------------- 212 // Field : RESETS_WDSEL_UART1 213 #define RESETS_WDSEL_UART1_RESET _u(0x0) 214 #define RESETS_WDSEL_UART1_BITS _u(0x00800000) 215 #define RESETS_WDSEL_UART1_MSB _u(23) 216 #define RESETS_WDSEL_UART1_LSB _u(23) 217 #define RESETS_WDSEL_UART1_ACCESS "RW" 218 // ----------------------------------------------------------------------------- 219 // Field : RESETS_WDSEL_UART0 220 #define RESETS_WDSEL_UART0_RESET _u(0x0) 221 #define RESETS_WDSEL_UART0_BITS _u(0x00400000) 222 #define RESETS_WDSEL_UART0_MSB _u(22) 223 #define RESETS_WDSEL_UART0_LSB _u(22) 224 #define RESETS_WDSEL_UART0_ACCESS "RW" 225 // ----------------------------------------------------------------------------- 226 // Field : RESETS_WDSEL_TIMER 227 #define RESETS_WDSEL_TIMER_RESET _u(0x0) 228 #define RESETS_WDSEL_TIMER_BITS _u(0x00200000) 229 #define RESETS_WDSEL_TIMER_MSB _u(21) 230 #define RESETS_WDSEL_TIMER_LSB _u(21) 231 #define RESETS_WDSEL_TIMER_ACCESS "RW" 232 // ----------------------------------------------------------------------------- 233 // Field : RESETS_WDSEL_TBMAN 234 #define RESETS_WDSEL_TBMAN_RESET _u(0x0) 235 #define RESETS_WDSEL_TBMAN_BITS _u(0x00100000) 236 #define RESETS_WDSEL_TBMAN_MSB _u(20) 237 #define RESETS_WDSEL_TBMAN_LSB _u(20) 238 #define RESETS_WDSEL_TBMAN_ACCESS "RW" 239 // ----------------------------------------------------------------------------- 240 // Field : RESETS_WDSEL_SYSINFO 241 #define RESETS_WDSEL_SYSINFO_RESET _u(0x0) 242 #define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000) 243 #define RESETS_WDSEL_SYSINFO_MSB _u(19) 244 #define RESETS_WDSEL_SYSINFO_LSB _u(19) 245 #define RESETS_WDSEL_SYSINFO_ACCESS "RW" 246 // ----------------------------------------------------------------------------- 247 // Field : RESETS_WDSEL_SYSCFG 248 #define RESETS_WDSEL_SYSCFG_RESET _u(0x0) 249 #define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000) 250 #define RESETS_WDSEL_SYSCFG_MSB _u(18) 251 #define RESETS_WDSEL_SYSCFG_LSB _u(18) 252 #define RESETS_WDSEL_SYSCFG_ACCESS "RW" 253 // ----------------------------------------------------------------------------- 254 // Field : RESETS_WDSEL_SPI1 255 #define RESETS_WDSEL_SPI1_RESET _u(0x0) 256 #define RESETS_WDSEL_SPI1_BITS _u(0x00020000) 257 #define RESETS_WDSEL_SPI1_MSB _u(17) 258 #define RESETS_WDSEL_SPI1_LSB _u(17) 259 #define RESETS_WDSEL_SPI1_ACCESS "RW" 260 // ----------------------------------------------------------------------------- 261 // Field : RESETS_WDSEL_SPI0 262 #define RESETS_WDSEL_SPI0_RESET _u(0x0) 263 #define RESETS_WDSEL_SPI0_BITS _u(0x00010000) 264 #define RESETS_WDSEL_SPI0_MSB _u(16) 265 #define RESETS_WDSEL_SPI0_LSB _u(16) 266 #define RESETS_WDSEL_SPI0_ACCESS "RW" 267 // ----------------------------------------------------------------------------- 268 // Field : RESETS_WDSEL_RTC 269 #define RESETS_WDSEL_RTC_RESET _u(0x0) 270 #define RESETS_WDSEL_RTC_BITS _u(0x00008000) 271 #define RESETS_WDSEL_RTC_MSB _u(15) 272 #define RESETS_WDSEL_RTC_LSB _u(15) 273 #define RESETS_WDSEL_RTC_ACCESS "RW" 274 // ----------------------------------------------------------------------------- 275 // Field : RESETS_WDSEL_PWM 276 #define RESETS_WDSEL_PWM_RESET _u(0x0) 277 #define RESETS_WDSEL_PWM_BITS _u(0x00004000) 278 #define RESETS_WDSEL_PWM_MSB _u(14) 279 #define RESETS_WDSEL_PWM_LSB _u(14) 280 #define RESETS_WDSEL_PWM_ACCESS "RW" 281 // ----------------------------------------------------------------------------- 282 // Field : RESETS_WDSEL_PLL_USB 283 #define RESETS_WDSEL_PLL_USB_RESET _u(0x0) 284 #define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000) 285 #define RESETS_WDSEL_PLL_USB_MSB _u(13) 286 #define RESETS_WDSEL_PLL_USB_LSB _u(13) 287 #define RESETS_WDSEL_PLL_USB_ACCESS "RW" 288 // ----------------------------------------------------------------------------- 289 // Field : RESETS_WDSEL_PLL_SYS 290 #define RESETS_WDSEL_PLL_SYS_RESET _u(0x0) 291 #define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000) 292 #define RESETS_WDSEL_PLL_SYS_MSB _u(12) 293 #define RESETS_WDSEL_PLL_SYS_LSB _u(12) 294 #define RESETS_WDSEL_PLL_SYS_ACCESS "RW" 295 // ----------------------------------------------------------------------------- 296 // Field : RESETS_WDSEL_PIO1 297 #define RESETS_WDSEL_PIO1_RESET _u(0x0) 298 #define RESETS_WDSEL_PIO1_BITS _u(0x00000800) 299 #define RESETS_WDSEL_PIO1_MSB _u(11) 300 #define RESETS_WDSEL_PIO1_LSB _u(11) 301 #define RESETS_WDSEL_PIO1_ACCESS "RW" 302 // ----------------------------------------------------------------------------- 303 // Field : RESETS_WDSEL_PIO0 304 #define RESETS_WDSEL_PIO0_RESET _u(0x0) 305 #define RESETS_WDSEL_PIO0_BITS _u(0x00000400) 306 #define RESETS_WDSEL_PIO0_MSB _u(10) 307 #define RESETS_WDSEL_PIO0_LSB _u(10) 308 #define RESETS_WDSEL_PIO0_ACCESS "RW" 309 // ----------------------------------------------------------------------------- 310 // Field : RESETS_WDSEL_PADS_QSPI 311 #define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0) 312 #define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200) 313 #define RESETS_WDSEL_PADS_QSPI_MSB _u(9) 314 #define RESETS_WDSEL_PADS_QSPI_LSB _u(9) 315 #define RESETS_WDSEL_PADS_QSPI_ACCESS "RW" 316 // ----------------------------------------------------------------------------- 317 // Field : RESETS_WDSEL_PADS_BANK0 318 #define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0) 319 #define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100) 320 #define RESETS_WDSEL_PADS_BANK0_MSB _u(8) 321 #define RESETS_WDSEL_PADS_BANK0_LSB _u(8) 322 #define RESETS_WDSEL_PADS_BANK0_ACCESS "RW" 323 // ----------------------------------------------------------------------------- 324 // Field : RESETS_WDSEL_JTAG 325 #define RESETS_WDSEL_JTAG_RESET _u(0x0) 326 #define RESETS_WDSEL_JTAG_BITS _u(0x00000080) 327 #define RESETS_WDSEL_JTAG_MSB _u(7) 328 #define RESETS_WDSEL_JTAG_LSB _u(7) 329 #define RESETS_WDSEL_JTAG_ACCESS "RW" 330 // ----------------------------------------------------------------------------- 331 // Field : RESETS_WDSEL_IO_QSPI 332 #define RESETS_WDSEL_IO_QSPI_RESET _u(0x0) 333 #define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040) 334 #define RESETS_WDSEL_IO_QSPI_MSB _u(6) 335 #define RESETS_WDSEL_IO_QSPI_LSB _u(6) 336 #define RESETS_WDSEL_IO_QSPI_ACCESS "RW" 337 // ----------------------------------------------------------------------------- 338 // Field : RESETS_WDSEL_IO_BANK0 339 #define RESETS_WDSEL_IO_BANK0_RESET _u(0x0) 340 #define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020) 341 #define RESETS_WDSEL_IO_BANK0_MSB _u(5) 342 #define RESETS_WDSEL_IO_BANK0_LSB _u(5) 343 #define RESETS_WDSEL_IO_BANK0_ACCESS "RW" 344 // ----------------------------------------------------------------------------- 345 // Field : RESETS_WDSEL_I2C1 346 #define RESETS_WDSEL_I2C1_RESET _u(0x0) 347 #define RESETS_WDSEL_I2C1_BITS _u(0x00000010) 348 #define RESETS_WDSEL_I2C1_MSB _u(4) 349 #define RESETS_WDSEL_I2C1_LSB _u(4) 350 #define RESETS_WDSEL_I2C1_ACCESS "RW" 351 // ----------------------------------------------------------------------------- 352 // Field : RESETS_WDSEL_I2C0 353 #define RESETS_WDSEL_I2C0_RESET _u(0x0) 354 #define RESETS_WDSEL_I2C0_BITS _u(0x00000008) 355 #define RESETS_WDSEL_I2C0_MSB _u(3) 356 #define RESETS_WDSEL_I2C0_LSB _u(3) 357 #define RESETS_WDSEL_I2C0_ACCESS "RW" 358 // ----------------------------------------------------------------------------- 359 // Field : RESETS_WDSEL_DMA 360 #define RESETS_WDSEL_DMA_RESET _u(0x0) 361 #define RESETS_WDSEL_DMA_BITS _u(0x00000004) 362 #define RESETS_WDSEL_DMA_MSB _u(2) 363 #define RESETS_WDSEL_DMA_LSB _u(2) 364 #define RESETS_WDSEL_DMA_ACCESS "RW" 365 // ----------------------------------------------------------------------------- 366 // Field : RESETS_WDSEL_BUSCTRL 367 #define RESETS_WDSEL_BUSCTRL_RESET _u(0x0) 368 #define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002) 369 #define RESETS_WDSEL_BUSCTRL_MSB _u(1) 370 #define RESETS_WDSEL_BUSCTRL_LSB _u(1) 371 #define RESETS_WDSEL_BUSCTRL_ACCESS "RW" 372 // ----------------------------------------------------------------------------- 373 // Field : RESETS_WDSEL_ADC 374 #define RESETS_WDSEL_ADC_RESET _u(0x0) 375 #define RESETS_WDSEL_ADC_BITS _u(0x00000001) 376 #define RESETS_WDSEL_ADC_MSB _u(0) 377 #define RESETS_WDSEL_ADC_LSB _u(0) 378 #define RESETS_WDSEL_ADC_ACCESS "RW" 379 // ============================================================================= 380 // Register : RESETS_RESET_DONE 381 // Description : Reset done. If a bit is set then a reset done signal has been 382 // returned by the peripheral. This indicates that the 383 // peripheral's registers are ready to be accessed. 384 #define RESETS_RESET_DONE_OFFSET _u(0x00000008) 385 #define RESETS_RESET_DONE_BITS _u(0x01ffffff) 386 #define RESETS_RESET_DONE_RESET _u(0x00000000) 387 // ----------------------------------------------------------------------------- 388 // Field : RESETS_RESET_DONE_USBCTRL 389 #define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0) 390 #define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000) 391 #define RESETS_RESET_DONE_USBCTRL_MSB _u(24) 392 #define RESETS_RESET_DONE_USBCTRL_LSB _u(24) 393 #define RESETS_RESET_DONE_USBCTRL_ACCESS "RO" 394 // ----------------------------------------------------------------------------- 395 // Field : RESETS_RESET_DONE_UART1 396 #define RESETS_RESET_DONE_UART1_RESET _u(0x0) 397 #define RESETS_RESET_DONE_UART1_BITS _u(0x00800000) 398 #define RESETS_RESET_DONE_UART1_MSB _u(23) 399 #define RESETS_RESET_DONE_UART1_LSB _u(23) 400 #define RESETS_RESET_DONE_UART1_ACCESS "RO" 401 // ----------------------------------------------------------------------------- 402 // Field : RESETS_RESET_DONE_UART0 403 #define RESETS_RESET_DONE_UART0_RESET _u(0x0) 404 #define RESETS_RESET_DONE_UART0_BITS _u(0x00400000) 405 #define RESETS_RESET_DONE_UART0_MSB _u(22) 406 #define RESETS_RESET_DONE_UART0_LSB _u(22) 407 #define RESETS_RESET_DONE_UART0_ACCESS "RO" 408 // ----------------------------------------------------------------------------- 409 // Field : RESETS_RESET_DONE_TIMER 410 #define RESETS_RESET_DONE_TIMER_RESET _u(0x0) 411 #define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000) 412 #define RESETS_RESET_DONE_TIMER_MSB _u(21) 413 #define RESETS_RESET_DONE_TIMER_LSB _u(21) 414 #define RESETS_RESET_DONE_TIMER_ACCESS "RO" 415 // ----------------------------------------------------------------------------- 416 // Field : RESETS_RESET_DONE_TBMAN 417 #define RESETS_RESET_DONE_TBMAN_RESET _u(0x0) 418 #define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000) 419 #define RESETS_RESET_DONE_TBMAN_MSB _u(20) 420 #define RESETS_RESET_DONE_TBMAN_LSB _u(20) 421 #define RESETS_RESET_DONE_TBMAN_ACCESS "RO" 422 // ----------------------------------------------------------------------------- 423 // Field : RESETS_RESET_DONE_SYSINFO 424 #define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0) 425 #define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000) 426 #define RESETS_RESET_DONE_SYSINFO_MSB _u(19) 427 #define RESETS_RESET_DONE_SYSINFO_LSB _u(19) 428 #define RESETS_RESET_DONE_SYSINFO_ACCESS "RO" 429 // ----------------------------------------------------------------------------- 430 // Field : RESETS_RESET_DONE_SYSCFG 431 #define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0) 432 #define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000) 433 #define RESETS_RESET_DONE_SYSCFG_MSB _u(18) 434 #define RESETS_RESET_DONE_SYSCFG_LSB _u(18) 435 #define RESETS_RESET_DONE_SYSCFG_ACCESS "RO" 436 // ----------------------------------------------------------------------------- 437 // Field : RESETS_RESET_DONE_SPI1 438 #define RESETS_RESET_DONE_SPI1_RESET _u(0x0) 439 #define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000) 440 #define RESETS_RESET_DONE_SPI1_MSB _u(17) 441 #define RESETS_RESET_DONE_SPI1_LSB _u(17) 442 #define RESETS_RESET_DONE_SPI1_ACCESS "RO" 443 // ----------------------------------------------------------------------------- 444 // Field : RESETS_RESET_DONE_SPI0 445 #define RESETS_RESET_DONE_SPI0_RESET _u(0x0) 446 #define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000) 447 #define RESETS_RESET_DONE_SPI0_MSB _u(16) 448 #define RESETS_RESET_DONE_SPI0_LSB _u(16) 449 #define RESETS_RESET_DONE_SPI0_ACCESS "RO" 450 // ----------------------------------------------------------------------------- 451 // Field : RESETS_RESET_DONE_RTC 452 #define RESETS_RESET_DONE_RTC_RESET _u(0x0) 453 #define RESETS_RESET_DONE_RTC_BITS _u(0x00008000) 454 #define RESETS_RESET_DONE_RTC_MSB _u(15) 455 #define RESETS_RESET_DONE_RTC_LSB _u(15) 456 #define RESETS_RESET_DONE_RTC_ACCESS "RO" 457 // ----------------------------------------------------------------------------- 458 // Field : RESETS_RESET_DONE_PWM 459 #define RESETS_RESET_DONE_PWM_RESET _u(0x0) 460 #define RESETS_RESET_DONE_PWM_BITS _u(0x00004000) 461 #define RESETS_RESET_DONE_PWM_MSB _u(14) 462 #define RESETS_RESET_DONE_PWM_LSB _u(14) 463 #define RESETS_RESET_DONE_PWM_ACCESS "RO" 464 // ----------------------------------------------------------------------------- 465 // Field : RESETS_RESET_DONE_PLL_USB 466 #define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0) 467 #define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000) 468 #define RESETS_RESET_DONE_PLL_USB_MSB _u(13) 469 #define RESETS_RESET_DONE_PLL_USB_LSB _u(13) 470 #define RESETS_RESET_DONE_PLL_USB_ACCESS "RO" 471 // ----------------------------------------------------------------------------- 472 // Field : RESETS_RESET_DONE_PLL_SYS 473 #define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0) 474 #define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000) 475 #define RESETS_RESET_DONE_PLL_SYS_MSB _u(12) 476 #define RESETS_RESET_DONE_PLL_SYS_LSB _u(12) 477 #define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO" 478 // ----------------------------------------------------------------------------- 479 // Field : RESETS_RESET_DONE_PIO1 480 #define RESETS_RESET_DONE_PIO1_RESET _u(0x0) 481 #define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800) 482 #define RESETS_RESET_DONE_PIO1_MSB _u(11) 483 #define RESETS_RESET_DONE_PIO1_LSB _u(11) 484 #define RESETS_RESET_DONE_PIO1_ACCESS "RO" 485 // ----------------------------------------------------------------------------- 486 // Field : RESETS_RESET_DONE_PIO0 487 #define RESETS_RESET_DONE_PIO0_RESET _u(0x0) 488 #define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400) 489 #define RESETS_RESET_DONE_PIO0_MSB _u(10) 490 #define RESETS_RESET_DONE_PIO0_LSB _u(10) 491 #define RESETS_RESET_DONE_PIO0_ACCESS "RO" 492 // ----------------------------------------------------------------------------- 493 // Field : RESETS_RESET_DONE_PADS_QSPI 494 #define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0) 495 #define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200) 496 #define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9) 497 #define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9) 498 #define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO" 499 // ----------------------------------------------------------------------------- 500 // Field : RESETS_RESET_DONE_PADS_BANK0 501 #define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0) 502 #define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100) 503 #define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8) 504 #define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8) 505 #define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO" 506 // ----------------------------------------------------------------------------- 507 // Field : RESETS_RESET_DONE_JTAG 508 #define RESETS_RESET_DONE_JTAG_RESET _u(0x0) 509 #define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080) 510 #define RESETS_RESET_DONE_JTAG_MSB _u(7) 511 #define RESETS_RESET_DONE_JTAG_LSB _u(7) 512 #define RESETS_RESET_DONE_JTAG_ACCESS "RO" 513 // ----------------------------------------------------------------------------- 514 // Field : RESETS_RESET_DONE_IO_QSPI 515 #define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0) 516 #define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040) 517 #define RESETS_RESET_DONE_IO_QSPI_MSB _u(6) 518 #define RESETS_RESET_DONE_IO_QSPI_LSB _u(6) 519 #define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO" 520 // ----------------------------------------------------------------------------- 521 // Field : RESETS_RESET_DONE_IO_BANK0 522 #define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0) 523 #define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020) 524 #define RESETS_RESET_DONE_IO_BANK0_MSB _u(5) 525 #define RESETS_RESET_DONE_IO_BANK0_LSB _u(5) 526 #define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO" 527 // ----------------------------------------------------------------------------- 528 // Field : RESETS_RESET_DONE_I2C1 529 #define RESETS_RESET_DONE_I2C1_RESET _u(0x0) 530 #define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010) 531 #define RESETS_RESET_DONE_I2C1_MSB _u(4) 532 #define RESETS_RESET_DONE_I2C1_LSB _u(4) 533 #define RESETS_RESET_DONE_I2C1_ACCESS "RO" 534 // ----------------------------------------------------------------------------- 535 // Field : RESETS_RESET_DONE_I2C0 536 #define RESETS_RESET_DONE_I2C0_RESET _u(0x0) 537 #define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008) 538 #define RESETS_RESET_DONE_I2C0_MSB _u(3) 539 #define RESETS_RESET_DONE_I2C0_LSB _u(3) 540 #define RESETS_RESET_DONE_I2C0_ACCESS "RO" 541 // ----------------------------------------------------------------------------- 542 // Field : RESETS_RESET_DONE_DMA 543 #define RESETS_RESET_DONE_DMA_RESET _u(0x0) 544 #define RESETS_RESET_DONE_DMA_BITS _u(0x00000004) 545 #define RESETS_RESET_DONE_DMA_MSB _u(2) 546 #define RESETS_RESET_DONE_DMA_LSB _u(2) 547 #define RESETS_RESET_DONE_DMA_ACCESS "RO" 548 // ----------------------------------------------------------------------------- 549 // Field : RESETS_RESET_DONE_BUSCTRL 550 #define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0) 551 #define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002) 552 #define RESETS_RESET_DONE_BUSCTRL_MSB _u(1) 553 #define RESETS_RESET_DONE_BUSCTRL_LSB _u(1) 554 #define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO" 555 // ----------------------------------------------------------------------------- 556 // Field : RESETS_RESET_DONE_ADC 557 #define RESETS_RESET_DONE_ADC_RESET _u(0x0) 558 #define RESETS_RESET_DONE_ADC_BITS _u(0x00000001) 559 #define RESETS_RESET_DONE_ADC_MSB _u(0) 560 #define RESETS_RESET_DONE_ADC_LSB _u(0) 561 #define RESETS_RESET_DONE_ADC_ACCESS "RO" 562 // ============================================================================= 563 #endif // _HARDWARE_REGS_RESETS_H 564 565
