1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2 
3 /**
4  * Copyright (c) 2024 Raspberry Pi Ltd.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 // =============================================================================
9 // Register block : PSM
10 // Version        : 1
11 // Bus type       : apb
12 // =============================================================================
13 #ifndef _HARDWARE_REGS_PSM_H
14 #define _HARDWARE_REGS_PSM_H
15 // =============================================================================
16 // Register    : PSM_FRCE_ON
17 // Description : Force block out of reset (i.e. power it on)
18 #define PSM_FRCE_ON_OFFSET _u(0x00000000)
19 #define PSM_FRCE_ON_BITS   _u(0x01ffffff)
20 #define PSM_FRCE_ON_RESET  _u(0x00000000)
21 // -----------------------------------------------------------------------------
22 // Field       : PSM_FRCE_ON_PROC1
23 #define PSM_FRCE_ON_PROC1_RESET  _u(0x0)
24 #define PSM_FRCE_ON_PROC1_BITS   _u(0x01000000)
25 #define PSM_FRCE_ON_PROC1_MSB    _u(24)
26 #define PSM_FRCE_ON_PROC1_LSB    _u(24)
27 #define PSM_FRCE_ON_PROC1_ACCESS "RW"
28 // -----------------------------------------------------------------------------
29 // Field       : PSM_FRCE_ON_PROC0
30 #define PSM_FRCE_ON_PROC0_RESET  _u(0x0)
31 #define PSM_FRCE_ON_PROC0_BITS   _u(0x00800000)
32 #define PSM_FRCE_ON_PROC0_MSB    _u(23)
33 #define PSM_FRCE_ON_PROC0_LSB    _u(23)
34 #define PSM_FRCE_ON_PROC0_ACCESS "RW"
35 // -----------------------------------------------------------------------------
36 // Field       : PSM_FRCE_ON_ACCESSCTRL
37 #define PSM_FRCE_ON_ACCESSCTRL_RESET  _u(0x0)
38 #define PSM_FRCE_ON_ACCESSCTRL_BITS   _u(0x00400000)
39 #define PSM_FRCE_ON_ACCESSCTRL_MSB    _u(22)
40 #define PSM_FRCE_ON_ACCESSCTRL_LSB    _u(22)
41 #define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW"
42 // -----------------------------------------------------------------------------
43 // Field       : PSM_FRCE_ON_SIO
44 #define PSM_FRCE_ON_SIO_RESET  _u(0x0)
45 #define PSM_FRCE_ON_SIO_BITS   _u(0x00200000)
46 #define PSM_FRCE_ON_SIO_MSB    _u(21)
47 #define PSM_FRCE_ON_SIO_LSB    _u(21)
48 #define PSM_FRCE_ON_SIO_ACCESS "RW"
49 // -----------------------------------------------------------------------------
50 // Field       : PSM_FRCE_ON_XIP
51 #define PSM_FRCE_ON_XIP_RESET  _u(0x0)
52 #define PSM_FRCE_ON_XIP_BITS   _u(0x00100000)
53 #define PSM_FRCE_ON_XIP_MSB    _u(20)
54 #define PSM_FRCE_ON_XIP_LSB    _u(20)
55 #define PSM_FRCE_ON_XIP_ACCESS "RW"
56 // -----------------------------------------------------------------------------
57 // Field       : PSM_FRCE_ON_SRAM9
58 #define PSM_FRCE_ON_SRAM9_RESET  _u(0x0)
59 #define PSM_FRCE_ON_SRAM9_BITS   _u(0x00080000)
60 #define PSM_FRCE_ON_SRAM9_MSB    _u(19)
61 #define PSM_FRCE_ON_SRAM9_LSB    _u(19)
62 #define PSM_FRCE_ON_SRAM9_ACCESS "RW"
63 // -----------------------------------------------------------------------------
64 // Field       : PSM_FRCE_ON_SRAM8
65 #define PSM_FRCE_ON_SRAM8_RESET  _u(0x0)
66 #define PSM_FRCE_ON_SRAM8_BITS   _u(0x00040000)
67 #define PSM_FRCE_ON_SRAM8_MSB    _u(18)
68 #define PSM_FRCE_ON_SRAM8_LSB    _u(18)
69 #define PSM_FRCE_ON_SRAM8_ACCESS "RW"
70 // -----------------------------------------------------------------------------
71 // Field       : PSM_FRCE_ON_SRAM7
72 #define PSM_FRCE_ON_SRAM7_RESET  _u(0x0)
73 #define PSM_FRCE_ON_SRAM7_BITS   _u(0x00020000)
74 #define PSM_FRCE_ON_SRAM7_MSB    _u(17)
75 #define PSM_FRCE_ON_SRAM7_LSB    _u(17)
76 #define PSM_FRCE_ON_SRAM7_ACCESS "RW"
77 // -----------------------------------------------------------------------------
78 // Field       : PSM_FRCE_ON_SRAM6
79 #define PSM_FRCE_ON_SRAM6_RESET  _u(0x0)
80 #define PSM_FRCE_ON_SRAM6_BITS   _u(0x00010000)
81 #define PSM_FRCE_ON_SRAM6_MSB    _u(16)
82 #define PSM_FRCE_ON_SRAM6_LSB    _u(16)
83 #define PSM_FRCE_ON_SRAM6_ACCESS "RW"
84 // -----------------------------------------------------------------------------
85 // Field       : PSM_FRCE_ON_SRAM5
86 #define PSM_FRCE_ON_SRAM5_RESET  _u(0x0)
87 #define PSM_FRCE_ON_SRAM5_BITS   _u(0x00008000)
88 #define PSM_FRCE_ON_SRAM5_MSB    _u(15)
89 #define PSM_FRCE_ON_SRAM5_LSB    _u(15)
90 #define PSM_FRCE_ON_SRAM5_ACCESS "RW"
91 // -----------------------------------------------------------------------------
92 // Field       : PSM_FRCE_ON_SRAM4
93 #define PSM_FRCE_ON_SRAM4_RESET  _u(0x0)
94 #define PSM_FRCE_ON_SRAM4_BITS   _u(0x00004000)
95 #define PSM_FRCE_ON_SRAM4_MSB    _u(14)
96 #define PSM_FRCE_ON_SRAM4_LSB    _u(14)
97 #define PSM_FRCE_ON_SRAM4_ACCESS "RW"
98 // -----------------------------------------------------------------------------
99 // Field       : PSM_FRCE_ON_SRAM3
100 #define PSM_FRCE_ON_SRAM3_RESET  _u(0x0)
101 #define PSM_FRCE_ON_SRAM3_BITS   _u(0x00002000)
102 #define PSM_FRCE_ON_SRAM3_MSB    _u(13)
103 #define PSM_FRCE_ON_SRAM3_LSB    _u(13)
104 #define PSM_FRCE_ON_SRAM3_ACCESS "RW"
105 // -----------------------------------------------------------------------------
106 // Field       : PSM_FRCE_ON_SRAM2
107 #define PSM_FRCE_ON_SRAM2_RESET  _u(0x0)
108 #define PSM_FRCE_ON_SRAM2_BITS   _u(0x00001000)
109 #define PSM_FRCE_ON_SRAM2_MSB    _u(12)
110 #define PSM_FRCE_ON_SRAM2_LSB    _u(12)
111 #define PSM_FRCE_ON_SRAM2_ACCESS "RW"
112 // -----------------------------------------------------------------------------
113 // Field       : PSM_FRCE_ON_SRAM1
114 #define PSM_FRCE_ON_SRAM1_RESET  _u(0x0)
115 #define PSM_FRCE_ON_SRAM1_BITS   _u(0x00000800)
116 #define PSM_FRCE_ON_SRAM1_MSB    _u(11)
117 #define PSM_FRCE_ON_SRAM1_LSB    _u(11)
118 #define PSM_FRCE_ON_SRAM1_ACCESS "RW"
119 // -----------------------------------------------------------------------------
120 // Field       : PSM_FRCE_ON_SRAM0
121 #define PSM_FRCE_ON_SRAM0_RESET  _u(0x0)
122 #define PSM_FRCE_ON_SRAM0_BITS   _u(0x00000400)
123 #define PSM_FRCE_ON_SRAM0_MSB    _u(10)
124 #define PSM_FRCE_ON_SRAM0_LSB    _u(10)
125 #define PSM_FRCE_ON_SRAM0_ACCESS "RW"
126 // -----------------------------------------------------------------------------
127 // Field       : PSM_FRCE_ON_BOOTRAM
128 #define PSM_FRCE_ON_BOOTRAM_RESET  _u(0x0)
129 #define PSM_FRCE_ON_BOOTRAM_BITS   _u(0x00000200)
130 #define PSM_FRCE_ON_BOOTRAM_MSB    _u(9)
131 #define PSM_FRCE_ON_BOOTRAM_LSB    _u(9)
132 #define PSM_FRCE_ON_BOOTRAM_ACCESS "RW"
133 // -----------------------------------------------------------------------------
134 // Field       : PSM_FRCE_ON_ROM
135 #define PSM_FRCE_ON_ROM_RESET  _u(0x0)
136 #define PSM_FRCE_ON_ROM_BITS   _u(0x00000100)
137 #define PSM_FRCE_ON_ROM_MSB    _u(8)
138 #define PSM_FRCE_ON_ROM_LSB    _u(8)
139 #define PSM_FRCE_ON_ROM_ACCESS "RW"
140 // -----------------------------------------------------------------------------
141 // Field       : PSM_FRCE_ON_BUSFABRIC
142 #define PSM_FRCE_ON_BUSFABRIC_RESET  _u(0x0)
143 #define PSM_FRCE_ON_BUSFABRIC_BITS   _u(0x00000080)
144 #define PSM_FRCE_ON_BUSFABRIC_MSB    _u(7)
145 #define PSM_FRCE_ON_BUSFABRIC_LSB    _u(7)
146 #define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
147 // -----------------------------------------------------------------------------
148 // Field       : PSM_FRCE_ON_PSM_READY
149 #define PSM_FRCE_ON_PSM_READY_RESET  _u(0x0)
150 #define PSM_FRCE_ON_PSM_READY_BITS   _u(0x00000040)
151 #define PSM_FRCE_ON_PSM_READY_MSB    _u(6)
152 #define PSM_FRCE_ON_PSM_READY_LSB    _u(6)
153 #define PSM_FRCE_ON_PSM_READY_ACCESS "RW"
154 // -----------------------------------------------------------------------------
155 // Field       : PSM_FRCE_ON_CLOCKS
156 #define PSM_FRCE_ON_CLOCKS_RESET  _u(0x0)
157 #define PSM_FRCE_ON_CLOCKS_BITS   _u(0x00000020)
158 #define PSM_FRCE_ON_CLOCKS_MSB    _u(5)
159 #define PSM_FRCE_ON_CLOCKS_LSB    _u(5)
160 #define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
161 // -----------------------------------------------------------------------------
162 // Field       : PSM_FRCE_ON_RESETS
163 #define PSM_FRCE_ON_RESETS_RESET  _u(0x0)
164 #define PSM_FRCE_ON_RESETS_BITS   _u(0x00000010)
165 #define PSM_FRCE_ON_RESETS_MSB    _u(4)
166 #define PSM_FRCE_ON_RESETS_LSB    _u(4)
167 #define PSM_FRCE_ON_RESETS_ACCESS "RW"
168 // -----------------------------------------------------------------------------
169 // Field       : PSM_FRCE_ON_XOSC
170 #define PSM_FRCE_ON_XOSC_RESET  _u(0x0)
171 #define PSM_FRCE_ON_XOSC_BITS   _u(0x00000008)
172 #define PSM_FRCE_ON_XOSC_MSB    _u(3)
173 #define PSM_FRCE_ON_XOSC_LSB    _u(3)
174 #define PSM_FRCE_ON_XOSC_ACCESS "RW"
175 // -----------------------------------------------------------------------------
176 // Field       : PSM_FRCE_ON_ROSC
177 #define PSM_FRCE_ON_ROSC_RESET  _u(0x0)
178 #define PSM_FRCE_ON_ROSC_BITS   _u(0x00000004)
179 #define PSM_FRCE_ON_ROSC_MSB    _u(2)
180 #define PSM_FRCE_ON_ROSC_LSB    _u(2)
181 #define PSM_FRCE_ON_ROSC_ACCESS "RW"
182 // -----------------------------------------------------------------------------
183 // Field       : PSM_FRCE_ON_OTP
184 #define PSM_FRCE_ON_OTP_RESET  _u(0x0)
185 #define PSM_FRCE_ON_OTP_BITS   _u(0x00000002)
186 #define PSM_FRCE_ON_OTP_MSB    _u(1)
187 #define PSM_FRCE_ON_OTP_LSB    _u(1)
188 #define PSM_FRCE_ON_OTP_ACCESS "RW"
189 // -----------------------------------------------------------------------------
190 // Field       : PSM_FRCE_ON_PROC_COLD
191 #define PSM_FRCE_ON_PROC_COLD_RESET  _u(0x0)
192 #define PSM_FRCE_ON_PROC_COLD_BITS   _u(0x00000001)
193 #define PSM_FRCE_ON_PROC_COLD_MSB    _u(0)
194 #define PSM_FRCE_ON_PROC_COLD_LSB    _u(0)
195 #define PSM_FRCE_ON_PROC_COLD_ACCESS "RW"
196 // =============================================================================
197 // Register    : PSM_FRCE_OFF
198 // Description : Force into reset (i.e. power it off)
199 #define PSM_FRCE_OFF_OFFSET _u(0x00000004)
200 #define PSM_FRCE_OFF_BITS   _u(0x01ffffff)
201 #define PSM_FRCE_OFF_RESET  _u(0x00000000)
202 // -----------------------------------------------------------------------------
203 // Field       : PSM_FRCE_OFF_PROC1
204 #define PSM_FRCE_OFF_PROC1_RESET  _u(0x0)
205 #define PSM_FRCE_OFF_PROC1_BITS   _u(0x01000000)
206 #define PSM_FRCE_OFF_PROC1_MSB    _u(24)
207 #define PSM_FRCE_OFF_PROC1_LSB    _u(24)
208 #define PSM_FRCE_OFF_PROC1_ACCESS "RW"
209 // -----------------------------------------------------------------------------
210 // Field       : PSM_FRCE_OFF_PROC0
211 #define PSM_FRCE_OFF_PROC0_RESET  _u(0x0)
212 #define PSM_FRCE_OFF_PROC0_BITS   _u(0x00800000)
213 #define PSM_FRCE_OFF_PROC0_MSB    _u(23)
214 #define PSM_FRCE_OFF_PROC0_LSB    _u(23)
215 #define PSM_FRCE_OFF_PROC0_ACCESS "RW"
216 // -----------------------------------------------------------------------------
217 // Field       : PSM_FRCE_OFF_ACCESSCTRL
218 #define PSM_FRCE_OFF_ACCESSCTRL_RESET  _u(0x0)
219 #define PSM_FRCE_OFF_ACCESSCTRL_BITS   _u(0x00400000)
220 #define PSM_FRCE_OFF_ACCESSCTRL_MSB    _u(22)
221 #define PSM_FRCE_OFF_ACCESSCTRL_LSB    _u(22)
222 #define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW"
223 // -----------------------------------------------------------------------------
224 // Field       : PSM_FRCE_OFF_SIO
225 #define PSM_FRCE_OFF_SIO_RESET  _u(0x0)
226 #define PSM_FRCE_OFF_SIO_BITS   _u(0x00200000)
227 #define PSM_FRCE_OFF_SIO_MSB    _u(21)
228 #define PSM_FRCE_OFF_SIO_LSB    _u(21)
229 #define PSM_FRCE_OFF_SIO_ACCESS "RW"
230 // -----------------------------------------------------------------------------
231 // Field       : PSM_FRCE_OFF_XIP
232 #define PSM_FRCE_OFF_XIP_RESET  _u(0x0)
233 #define PSM_FRCE_OFF_XIP_BITS   _u(0x00100000)
234 #define PSM_FRCE_OFF_XIP_MSB    _u(20)
235 #define PSM_FRCE_OFF_XIP_LSB    _u(20)
236 #define PSM_FRCE_OFF_XIP_ACCESS "RW"
237 // -----------------------------------------------------------------------------
238 // Field       : PSM_FRCE_OFF_SRAM9
239 #define PSM_FRCE_OFF_SRAM9_RESET  _u(0x0)
240 #define PSM_FRCE_OFF_SRAM9_BITS   _u(0x00080000)
241 #define PSM_FRCE_OFF_SRAM9_MSB    _u(19)
242 #define PSM_FRCE_OFF_SRAM9_LSB    _u(19)
243 #define PSM_FRCE_OFF_SRAM9_ACCESS "RW"
244 // -----------------------------------------------------------------------------
245 // Field       : PSM_FRCE_OFF_SRAM8
246 #define PSM_FRCE_OFF_SRAM8_RESET  _u(0x0)
247 #define PSM_FRCE_OFF_SRAM8_BITS   _u(0x00040000)
248 #define PSM_FRCE_OFF_SRAM8_MSB    _u(18)
249 #define PSM_FRCE_OFF_SRAM8_LSB    _u(18)
250 #define PSM_FRCE_OFF_SRAM8_ACCESS "RW"
251 // -----------------------------------------------------------------------------
252 // Field       : PSM_FRCE_OFF_SRAM7
253 #define PSM_FRCE_OFF_SRAM7_RESET  _u(0x0)
254 #define PSM_FRCE_OFF_SRAM7_BITS   _u(0x00020000)
255 #define PSM_FRCE_OFF_SRAM7_MSB    _u(17)
256 #define PSM_FRCE_OFF_SRAM7_LSB    _u(17)
257 #define PSM_FRCE_OFF_SRAM7_ACCESS "RW"
258 // -----------------------------------------------------------------------------
259 // Field       : PSM_FRCE_OFF_SRAM6
260 #define PSM_FRCE_OFF_SRAM6_RESET  _u(0x0)
261 #define PSM_FRCE_OFF_SRAM6_BITS   _u(0x00010000)
262 #define PSM_FRCE_OFF_SRAM6_MSB    _u(16)
263 #define PSM_FRCE_OFF_SRAM6_LSB    _u(16)
264 #define PSM_FRCE_OFF_SRAM6_ACCESS "RW"
265 // -----------------------------------------------------------------------------
266 // Field       : PSM_FRCE_OFF_SRAM5
267 #define PSM_FRCE_OFF_SRAM5_RESET  _u(0x0)
268 #define PSM_FRCE_OFF_SRAM5_BITS   _u(0x00008000)
269 #define PSM_FRCE_OFF_SRAM5_MSB    _u(15)
270 #define PSM_FRCE_OFF_SRAM5_LSB    _u(15)
271 #define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
272 // -----------------------------------------------------------------------------
273 // Field       : PSM_FRCE_OFF_SRAM4
274 #define PSM_FRCE_OFF_SRAM4_RESET  _u(0x0)
275 #define PSM_FRCE_OFF_SRAM4_BITS   _u(0x00004000)
276 #define PSM_FRCE_OFF_SRAM4_MSB    _u(14)
277 #define PSM_FRCE_OFF_SRAM4_LSB    _u(14)
278 #define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
279 // -----------------------------------------------------------------------------
280 // Field       : PSM_FRCE_OFF_SRAM3
281 #define PSM_FRCE_OFF_SRAM3_RESET  _u(0x0)
282 #define PSM_FRCE_OFF_SRAM3_BITS   _u(0x00002000)
283 #define PSM_FRCE_OFF_SRAM3_MSB    _u(13)
284 #define PSM_FRCE_OFF_SRAM3_LSB    _u(13)
285 #define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
286 // -----------------------------------------------------------------------------
287 // Field       : PSM_FRCE_OFF_SRAM2
288 #define PSM_FRCE_OFF_SRAM2_RESET  _u(0x0)
289 #define PSM_FRCE_OFF_SRAM2_BITS   _u(0x00001000)
290 #define PSM_FRCE_OFF_SRAM2_MSB    _u(12)
291 #define PSM_FRCE_OFF_SRAM2_LSB    _u(12)
292 #define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
293 // -----------------------------------------------------------------------------
294 // Field       : PSM_FRCE_OFF_SRAM1
295 #define PSM_FRCE_OFF_SRAM1_RESET  _u(0x0)
296 #define PSM_FRCE_OFF_SRAM1_BITS   _u(0x00000800)
297 #define PSM_FRCE_OFF_SRAM1_MSB    _u(11)
298 #define PSM_FRCE_OFF_SRAM1_LSB    _u(11)
299 #define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
300 // -----------------------------------------------------------------------------
301 // Field       : PSM_FRCE_OFF_SRAM0
302 #define PSM_FRCE_OFF_SRAM0_RESET  _u(0x0)
303 #define PSM_FRCE_OFF_SRAM0_BITS   _u(0x00000400)
304 #define PSM_FRCE_OFF_SRAM0_MSB    _u(10)
305 #define PSM_FRCE_OFF_SRAM0_LSB    _u(10)
306 #define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
307 // -----------------------------------------------------------------------------
308 // Field       : PSM_FRCE_OFF_BOOTRAM
309 #define PSM_FRCE_OFF_BOOTRAM_RESET  _u(0x0)
310 #define PSM_FRCE_OFF_BOOTRAM_BITS   _u(0x00000200)
311 #define PSM_FRCE_OFF_BOOTRAM_MSB    _u(9)
312 #define PSM_FRCE_OFF_BOOTRAM_LSB    _u(9)
313 #define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW"
314 // -----------------------------------------------------------------------------
315 // Field       : PSM_FRCE_OFF_ROM
316 #define PSM_FRCE_OFF_ROM_RESET  _u(0x0)
317 #define PSM_FRCE_OFF_ROM_BITS   _u(0x00000100)
318 #define PSM_FRCE_OFF_ROM_MSB    _u(8)
319 #define PSM_FRCE_OFF_ROM_LSB    _u(8)
320 #define PSM_FRCE_OFF_ROM_ACCESS "RW"
321 // -----------------------------------------------------------------------------
322 // Field       : PSM_FRCE_OFF_BUSFABRIC
323 #define PSM_FRCE_OFF_BUSFABRIC_RESET  _u(0x0)
324 #define PSM_FRCE_OFF_BUSFABRIC_BITS   _u(0x00000080)
325 #define PSM_FRCE_OFF_BUSFABRIC_MSB    _u(7)
326 #define PSM_FRCE_OFF_BUSFABRIC_LSB    _u(7)
327 #define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
328 // -----------------------------------------------------------------------------
329 // Field       : PSM_FRCE_OFF_PSM_READY
330 #define PSM_FRCE_OFF_PSM_READY_RESET  _u(0x0)
331 #define PSM_FRCE_OFF_PSM_READY_BITS   _u(0x00000040)
332 #define PSM_FRCE_OFF_PSM_READY_MSB    _u(6)
333 #define PSM_FRCE_OFF_PSM_READY_LSB    _u(6)
334 #define PSM_FRCE_OFF_PSM_READY_ACCESS "RW"
335 // -----------------------------------------------------------------------------
336 // Field       : PSM_FRCE_OFF_CLOCKS
337 #define PSM_FRCE_OFF_CLOCKS_RESET  _u(0x0)
338 #define PSM_FRCE_OFF_CLOCKS_BITS   _u(0x00000020)
339 #define PSM_FRCE_OFF_CLOCKS_MSB    _u(5)
340 #define PSM_FRCE_OFF_CLOCKS_LSB    _u(5)
341 #define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
342 // -----------------------------------------------------------------------------
343 // Field       : PSM_FRCE_OFF_RESETS
344 #define PSM_FRCE_OFF_RESETS_RESET  _u(0x0)
345 #define PSM_FRCE_OFF_RESETS_BITS   _u(0x00000010)
346 #define PSM_FRCE_OFF_RESETS_MSB    _u(4)
347 #define PSM_FRCE_OFF_RESETS_LSB    _u(4)
348 #define PSM_FRCE_OFF_RESETS_ACCESS "RW"
349 // -----------------------------------------------------------------------------
350 // Field       : PSM_FRCE_OFF_XOSC
351 #define PSM_FRCE_OFF_XOSC_RESET  _u(0x0)
352 #define PSM_FRCE_OFF_XOSC_BITS   _u(0x00000008)
353 #define PSM_FRCE_OFF_XOSC_MSB    _u(3)
354 #define PSM_FRCE_OFF_XOSC_LSB    _u(3)
355 #define PSM_FRCE_OFF_XOSC_ACCESS "RW"
356 // -----------------------------------------------------------------------------
357 // Field       : PSM_FRCE_OFF_ROSC
358 #define PSM_FRCE_OFF_ROSC_RESET  _u(0x0)
359 #define PSM_FRCE_OFF_ROSC_BITS   _u(0x00000004)
360 #define PSM_FRCE_OFF_ROSC_MSB    _u(2)
361 #define PSM_FRCE_OFF_ROSC_LSB    _u(2)
362 #define PSM_FRCE_OFF_ROSC_ACCESS "RW"
363 // -----------------------------------------------------------------------------
364 // Field       : PSM_FRCE_OFF_OTP
365 #define PSM_FRCE_OFF_OTP_RESET  _u(0x0)
366 #define PSM_FRCE_OFF_OTP_BITS   _u(0x00000002)
367 #define PSM_FRCE_OFF_OTP_MSB    _u(1)
368 #define PSM_FRCE_OFF_OTP_LSB    _u(1)
369 #define PSM_FRCE_OFF_OTP_ACCESS "RW"
370 // -----------------------------------------------------------------------------
371 // Field       : PSM_FRCE_OFF_PROC_COLD
372 #define PSM_FRCE_OFF_PROC_COLD_RESET  _u(0x0)
373 #define PSM_FRCE_OFF_PROC_COLD_BITS   _u(0x00000001)
374 #define PSM_FRCE_OFF_PROC_COLD_MSB    _u(0)
375 #define PSM_FRCE_OFF_PROC_COLD_LSB    _u(0)
376 #define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW"
377 // =============================================================================
378 // Register    : PSM_WDSEL
379 // Description : Set to 1 if the watchdog should reset this
380 #define PSM_WDSEL_OFFSET _u(0x00000008)
381 #define PSM_WDSEL_BITS   _u(0x01ffffff)
382 #define PSM_WDSEL_RESET  _u(0x00000000)
383 // -----------------------------------------------------------------------------
384 // Field       : PSM_WDSEL_PROC1
385 #define PSM_WDSEL_PROC1_RESET  _u(0x0)
386 #define PSM_WDSEL_PROC1_BITS   _u(0x01000000)
387 #define PSM_WDSEL_PROC1_MSB    _u(24)
388 #define PSM_WDSEL_PROC1_LSB    _u(24)
389 #define PSM_WDSEL_PROC1_ACCESS "RW"
390 // -----------------------------------------------------------------------------
391 // Field       : PSM_WDSEL_PROC0
392 #define PSM_WDSEL_PROC0_RESET  _u(0x0)
393 #define PSM_WDSEL_PROC0_BITS   _u(0x00800000)
394 #define PSM_WDSEL_PROC0_MSB    _u(23)
395 #define PSM_WDSEL_PROC0_LSB    _u(23)
396 #define PSM_WDSEL_PROC0_ACCESS "RW"
397 // -----------------------------------------------------------------------------
398 // Field       : PSM_WDSEL_ACCESSCTRL
399 #define PSM_WDSEL_ACCESSCTRL_RESET  _u(0x0)
400 #define PSM_WDSEL_ACCESSCTRL_BITS   _u(0x00400000)
401 #define PSM_WDSEL_ACCESSCTRL_MSB    _u(22)
402 #define PSM_WDSEL_ACCESSCTRL_LSB    _u(22)
403 #define PSM_WDSEL_ACCESSCTRL_ACCESS "RW"
404 // -----------------------------------------------------------------------------
405 // Field       : PSM_WDSEL_SIO
406 #define PSM_WDSEL_SIO_RESET  _u(0x0)
407 #define PSM_WDSEL_SIO_BITS   _u(0x00200000)
408 #define PSM_WDSEL_SIO_MSB    _u(21)
409 #define PSM_WDSEL_SIO_LSB    _u(21)
410 #define PSM_WDSEL_SIO_ACCESS "RW"
411 // -----------------------------------------------------------------------------
412 // Field       : PSM_WDSEL_XIP
413 #define PSM_WDSEL_XIP_RESET  _u(0x0)
414 #define PSM_WDSEL_XIP_BITS   _u(0x00100000)
415 #define PSM_WDSEL_XIP_MSB    _u(20)
416 #define PSM_WDSEL_XIP_LSB    _u(20)
417 #define PSM_WDSEL_XIP_ACCESS "RW"
418 // -----------------------------------------------------------------------------
419 // Field       : PSM_WDSEL_SRAM9
420 #define PSM_WDSEL_SRAM9_RESET  _u(0x0)
421 #define PSM_WDSEL_SRAM9_BITS   _u(0x00080000)
422 #define PSM_WDSEL_SRAM9_MSB    _u(19)
423 #define PSM_WDSEL_SRAM9_LSB    _u(19)
424 #define PSM_WDSEL_SRAM9_ACCESS "RW"
425 // -----------------------------------------------------------------------------
426 // Field       : PSM_WDSEL_SRAM8
427 #define PSM_WDSEL_SRAM8_RESET  _u(0x0)
428 #define PSM_WDSEL_SRAM8_BITS   _u(0x00040000)
429 #define PSM_WDSEL_SRAM8_MSB    _u(18)
430 #define PSM_WDSEL_SRAM8_LSB    _u(18)
431 #define PSM_WDSEL_SRAM8_ACCESS "RW"
432 // -----------------------------------------------------------------------------
433 // Field       : PSM_WDSEL_SRAM7
434 #define PSM_WDSEL_SRAM7_RESET  _u(0x0)
435 #define PSM_WDSEL_SRAM7_BITS   _u(0x00020000)
436 #define PSM_WDSEL_SRAM7_MSB    _u(17)
437 #define PSM_WDSEL_SRAM7_LSB    _u(17)
438 #define PSM_WDSEL_SRAM7_ACCESS "RW"
439 // -----------------------------------------------------------------------------
440 // Field       : PSM_WDSEL_SRAM6
441 #define PSM_WDSEL_SRAM6_RESET  _u(0x0)
442 #define PSM_WDSEL_SRAM6_BITS   _u(0x00010000)
443 #define PSM_WDSEL_SRAM6_MSB    _u(16)
444 #define PSM_WDSEL_SRAM6_LSB    _u(16)
445 #define PSM_WDSEL_SRAM6_ACCESS "RW"
446 // -----------------------------------------------------------------------------
447 // Field       : PSM_WDSEL_SRAM5
448 #define PSM_WDSEL_SRAM5_RESET  _u(0x0)
449 #define PSM_WDSEL_SRAM5_BITS   _u(0x00008000)
450 #define PSM_WDSEL_SRAM5_MSB    _u(15)
451 #define PSM_WDSEL_SRAM5_LSB    _u(15)
452 #define PSM_WDSEL_SRAM5_ACCESS "RW"
453 // -----------------------------------------------------------------------------
454 // Field       : PSM_WDSEL_SRAM4
455 #define PSM_WDSEL_SRAM4_RESET  _u(0x0)
456 #define PSM_WDSEL_SRAM4_BITS   _u(0x00004000)
457 #define PSM_WDSEL_SRAM4_MSB    _u(14)
458 #define PSM_WDSEL_SRAM4_LSB    _u(14)
459 #define PSM_WDSEL_SRAM4_ACCESS "RW"
460 // -----------------------------------------------------------------------------
461 // Field       : PSM_WDSEL_SRAM3
462 #define PSM_WDSEL_SRAM3_RESET  _u(0x0)
463 #define PSM_WDSEL_SRAM3_BITS   _u(0x00002000)
464 #define PSM_WDSEL_SRAM3_MSB    _u(13)
465 #define PSM_WDSEL_SRAM3_LSB    _u(13)
466 #define PSM_WDSEL_SRAM3_ACCESS "RW"
467 // -----------------------------------------------------------------------------
468 // Field       : PSM_WDSEL_SRAM2
469 #define PSM_WDSEL_SRAM2_RESET  _u(0x0)
470 #define PSM_WDSEL_SRAM2_BITS   _u(0x00001000)
471 #define PSM_WDSEL_SRAM2_MSB    _u(12)
472 #define PSM_WDSEL_SRAM2_LSB    _u(12)
473 #define PSM_WDSEL_SRAM2_ACCESS "RW"
474 // -----------------------------------------------------------------------------
475 // Field       : PSM_WDSEL_SRAM1
476 #define PSM_WDSEL_SRAM1_RESET  _u(0x0)
477 #define PSM_WDSEL_SRAM1_BITS   _u(0x00000800)
478 #define PSM_WDSEL_SRAM1_MSB    _u(11)
479 #define PSM_WDSEL_SRAM1_LSB    _u(11)
480 #define PSM_WDSEL_SRAM1_ACCESS "RW"
481 // -----------------------------------------------------------------------------
482 // Field       : PSM_WDSEL_SRAM0
483 #define PSM_WDSEL_SRAM0_RESET  _u(0x0)
484 #define PSM_WDSEL_SRAM0_BITS   _u(0x00000400)
485 #define PSM_WDSEL_SRAM0_MSB    _u(10)
486 #define PSM_WDSEL_SRAM0_LSB    _u(10)
487 #define PSM_WDSEL_SRAM0_ACCESS "RW"
488 // -----------------------------------------------------------------------------
489 // Field       : PSM_WDSEL_BOOTRAM
490 #define PSM_WDSEL_BOOTRAM_RESET  _u(0x0)
491 #define PSM_WDSEL_BOOTRAM_BITS   _u(0x00000200)
492 #define PSM_WDSEL_BOOTRAM_MSB    _u(9)
493 #define PSM_WDSEL_BOOTRAM_LSB    _u(9)
494 #define PSM_WDSEL_BOOTRAM_ACCESS "RW"
495 // -----------------------------------------------------------------------------
496 // Field       : PSM_WDSEL_ROM
497 #define PSM_WDSEL_ROM_RESET  _u(0x0)
498 #define PSM_WDSEL_ROM_BITS   _u(0x00000100)
499 #define PSM_WDSEL_ROM_MSB    _u(8)
500 #define PSM_WDSEL_ROM_LSB    _u(8)
501 #define PSM_WDSEL_ROM_ACCESS "RW"
502 // -----------------------------------------------------------------------------
503 // Field       : PSM_WDSEL_BUSFABRIC
504 #define PSM_WDSEL_BUSFABRIC_RESET  _u(0x0)
505 #define PSM_WDSEL_BUSFABRIC_BITS   _u(0x00000080)
506 #define PSM_WDSEL_BUSFABRIC_MSB    _u(7)
507 #define PSM_WDSEL_BUSFABRIC_LSB    _u(7)
508 #define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
509 // -----------------------------------------------------------------------------
510 // Field       : PSM_WDSEL_PSM_READY
511 #define PSM_WDSEL_PSM_READY_RESET  _u(0x0)
512 #define PSM_WDSEL_PSM_READY_BITS   _u(0x00000040)
513 #define PSM_WDSEL_PSM_READY_MSB    _u(6)
514 #define PSM_WDSEL_PSM_READY_LSB    _u(6)
515 #define PSM_WDSEL_PSM_READY_ACCESS "RW"
516 // -----------------------------------------------------------------------------
517 // Field       : PSM_WDSEL_CLOCKS
518 #define PSM_WDSEL_CLOCKS_RESET  _u(0x0)
519 #define PSM_WDSEL_CLOCKS_BITS   _u(0x00000020)
520 #define PSM_WDSEL_CLOCKS_MSB    _u(5)
521 #define PSM_WDSEL_CLOCKS_LSB    _u(5)
522 #define PSM_WDSEL_CLOCKS_ACCESS "RW"
523 // -----------------------------------------------------------------------------
524 // Field       : PSM_WDSEL_RESETS
525 #define PSM_WDSEL_RESETS_RESET  _u(0x0)
526 #define PSM_WDSEL_RESETS_BITS   _u(0x00000010)
527 #define PSM_WDSEL_RESETS_MSB    _u(4)
528 #define PSM_WDSEL_RESETS_LSB    _u(4)
529 #define PSM_WDSEL_RESETS_ACCESS "RW"
530 // -----------------------------------------------------------------------------
531 // Field       : PSM_WDSEL_XOSC
532 #define PSM_WDSEL_XOSC_RESET  _u(0x0)
533 #define PSM_WDSEL_XOSC_BITS   _u(0x00000008)
534 #define PSM_WDSEL_XOSC_MSB    _u(3)
535 #define PSM_WDSEL_XOSC_LSB    _u(3)
536 #define PSM_WDSEL_XOSC_ACCESS "RW"
537 // -----------------------------------------------------------------------------
538 // Field       : PSM_WDSEL_ROSC
539 #define PSM_WDSEL_ROSC_RESET  _u(0x0)
540 #define PSM_WDSEL_ROSC_BITS   _u(0x00000004)
541 #define PSM_WDSEL_ROSC_MSB    _u(2)
542 #define PSM_WDSEL_ROSC_LSB    _u(2)
543 #define PSM_WDSEL_ROSC_ACCESS "RW"
544 // -----------------------------------------------------------------------------
545 // Field       : PSM_WDSEL_OTP
546 #define PSM_WDSEL_OTP_RESET  _u(0x0)
547 #define PSM_WDSEL_OTP_BITS   _u(0x00000002)
548 #define PSM_WDSEL_OTP_MSB    _u(1)
549 #define PSM_WDSEL_OTP_LSB    _u(1)
550 #define PSM_WDSEL_OTP_ACCESS "RW"
551 // -----------------------------------------------------------------------------
552 // Field       : PSM_WDSEL_PROC_COLD
553 #define PSM_WDSEL_PROC_COLD_RESET  _u(0x0)
554 #define PSM_WDSEL_PROC_COLD_BITS   _u(0x00000001)
555 #define PSM_WDSEL_PROC_COLD_MSB    _u(0)
556 #define PSM_WDSEL_PROC_COLD_LSB    _u(0)
557 #define PSM_WDSEL_PROC_COLD_ACCESS "RW"
558 // =============================================================================
559 // Register    : PSM_DONE
560 // Description : Is the subsystem ready?
561 #define PSM_DONE_OFFSET _u(0x0000000c)
562 #define PSM_DONE_BITS   _u(0x01ffffff)
563 #define PSM_DONE_RESET  _u(0x00000000)
564 // -----------------------------------------------------------------------------
565 // Field       : PSM_DONE_PROC1
566 #define PSM_DONE_PROC1_RESET  _u(0x0)
567 #define PSM_DONE_PROC1_BITS   _u(0x01000000)
568 #define PSM_DONE_PROC1_MSB    _u(24)
569 #define PSM_DONE_PROC1_LSB    _u(24)
570 #define PSM_DONE_PROC1_ACCESS "RO"
571 // -----------------------------------------------------------------------------
572 // Field       : PSM_DONE_PROC0
573 #define PSM_DONE_PROC0_RESET  _u(0x0)
574 #define PSM_DONE_PROC0_BITS   _u(0x00800000)
575 #define PSM_DONE_PROC0_MSB    _u(23)
576 #define PSM_DONE_PROC0_LSB    _u(23)
577 #define PSM_DONE_PROC0_ACCESS "RO"
578 // -----------------------------------------------------------------------------
579 // Field       : PSM_DONE_ACCESSCTRL
580 #define PSM_DONE_ACCESSCTRL_RESET  _u(0x0)
581 #define PSM_DONE_ACCESSCTRL_BITS   _u(0x00400000)
582 #define PSM_DONE_ACCESSCTRL_MSB    _u(22)
583 #define PSM_DONE_ACCESSCTRL_LSB    _u(22)
584 #define PSM_DONE_ACCESSCTRL_ACCESS "RO"
585 // -----------------------------------------------------------------------------
586 // Field       : PSM_DONE_SIO
587 #define PSM_DONE_SIO_RESET  _u(0x0)
588 #define PSM_DONE_SIO_BITS   _u(0x00200000)
589 #define PSM_DONE_SIO_MSB    _u(21)
590 #define PSM_DONE_SIO_LSB    _u(21)
591 #define PSM_DONE_SIO_ACCESS "RO"
592 // -----------------------------------------------------------------------------
593 // Field       : PSM_DONE_XIP
594 #define PSM_DONE_XIP_RESET  _u(0x0)
595 #define PSM_DONE_XIP_BITS   _u(0x00100000)
596 #define PSM_DONE_XIP_MSB    _u(20)
597 #define PSM_DONE_XIP_LSB    _u(20)
598 #define PSM_DONE_XIP_ACCESS "RO"
599 // -----------------------------------------------------------------------------
600 // Field       : PSM_DONE_SRAM9
601 #define PSM_DONE_SRAM9_RESET  _u(0x0)
602 #define PSM_DONE_SRAM9_BITS   _u(0x00080000)
603 #define PSM_DONE_SRAM9_MSB    _u(19)
604 #define PSM_DONE_SRAM9_LSB    _u(19)
605 #define PSM_DONE_SRAM9_ACCESS "RO"
606 // -----------------------------------------------------------------------------
607 // Field       : PSM_DONE_SRAM8
608 #define PSM_DONE_SRAM8_RESET  _u(0x0)
609 #define PSM_DONE_SRAM8_BITS   _u(0x00040000)
610 #define PSM_DONE_SRAM8_MSB    _u(18)
611 #define PSM_DONE_SRAM8_LSB    _u(18)
612 #define PSM_DONE_SRAM8_ACCESS "RO"
613 // -----------------------------------------------------------------------------
614 // Field       : PSM_DONE_SRAM7
615 #define PSM_DONE_SRAM7_RESET  _u(0x0)
616 #define PSM_DONE_SRAM7_BITS   _u(0x00020000)
617 #define PSM_DONE_SRAM7_MSB    _u(17)
618 #define PSM_DONE_SRAM7_LSB    _u(17)
619 #define PSM_DONE_SRAM7_ACCESS "RO"
620 // -----------------------------------------------------------------------------
621 // Field       : PSM_DONE_SRAM6
622 #define PSM_DONE_SRAM6_RESET  _u(0x0)
623 #define PSM_DONE_SRAM6_BITS   _u(0x00010000)
624 #define PSM_DONE_SRAM6_MSB    _u(16)
625 #define PSM_DONE_SRAM6_LSB    _u(16)
626 #define PSM_DONE_SRAM6_ACCESS "RO"
627 // -----------------------------------------------------------------------------
628 // Field       : PSM_DONE_SRAM5
629 #define PSM_DONE_SRAM5_RESET  _u(0x0)
630 #define PSM_DONE_SRAM5_BITS   _u(0x00008000)
631 #define PSM_DONE_SRAM5_MSB    _u(15)
632 #define PSM_DONE_SRAM5_LSB    _u(15)
633 #define PSM_DONE_SRAM5_ACCESS "RO"
634 // -----------------------------------------------------------------------------
635 // Field       : PSM_DONE_SRAM4
636 #define PSM_DONE_SRAM4_RESET  _u(0x0)
637 #define PSM_DONE_SRAM4_BITS   _u(0x00004000)
638 #define PSM_DONE_SRAM4_MSB    _u(14)
639 #define PSM_DONE_SRAM4_LSB    _u(14)
640 #define PSM_DONE_SRAM4_ACCESS "RO"
641 // -----------------------------------------------------------------------------
642 // Field       : PSM_DONE_SRAM3
643 #define PSM_DONE_SRAM3_RESET  _u(0x0)
644 #define PSM_DONE_SRAM3_BITS   _u(0x00002000)
645 #define PSM_DONE_SRAM3_MSB    _u(13)
646 #define PSM_DONE_SRAM3_LSB    _u(13)
647 #define PSM_DONE_SRAM3_ACCESS "RO"
648 // -----------------------------------------------------------------------------
649 // Field       : PSM_DONE_SRAM2
650 #define PSM_DONE_SRAM2_RESET  _u(0x0)
651 #define PSM_DONE_SRAM2_BITS   _u(0x00001000)
652 #define PSM_DONE_SRAM2_MSB    _u(12)
653 #define PSM_DONE_SRAM2_LSB    _u(12)
654 #define PSM_DONE_SRAM2_ACCESS "RO"
655 // -----------------------------------------------------------------------------
656 // Field       : PSM_DONE_SRAM1
657 #define PSM_DONE_SRAM1_RESET  _u(0x0)
658 #define PSM_DONE_SRAM1_BITS   _u(0x00000800)
659 #define PSM_DONE_SRAM1_MSB    _u(11)
660 #define PSM_DONE_SRAM1_LSB    _u(11)
661 #define PSM_DONE_SRAM1_ACCESS "RO"
662 // -----------------------------------------------------------------------------
663 // Field       : PSM_DONE_SRAM0
664 #define PSM_DONE_SRAM0_RESET  _u(0x0)
665 #define PSM_DONE_SRAM0_BITS   _u(0x00000400)
666 #define PSM_DONE_SRAM0_MSB    _u(10)
667 #define PSM_DONE_SRAM0_LSB    _u(10)
668 #define PSM_DONE_SRAM0_ACCESS "RO"
669 // -----------------------------------------------------------------------------
670 // Field       : PSM_DONE_BOOTRAM
671 #define PSM_DONE_BOOTRAM_RESET  _u(0x0)
672 #define PSM_DONE_BOOTRAM_BITS   _u(0x00000200)
673 #define PSM_DONE_BOOTRAM_MSB    _u(9)
674 #define PSM_DONE_BOOTRAM_LSB    _u(9)
675 #define PSM_DONE_BOOTRAM_ACCESS "RO"
676 // -----------------------------------------------------------------------------
677 // Field       : PSM_DONE_ROM
678 #define PSM_DONE_ROM_RESET  _u(0x0)
679 #define PSM_DONE_ROM_BITS   _u(0x00000100)
680 #define PSM_DONE_ROM_MSB    _u(8)
681 #define PSM_DONE_ROM_LSB    _u(8)
682 #define PSM_DONE_ROM_ACCESS "RO"
683 // -----------------------------------------------------------------------------
684 // Field       : PSM_DONE_BUSFABRIC
685 #define PSM_DONE_BUSFABRIC_RESET  _u(0x0)
686 #define PSM_DONE_BUSFABRIC_BITS   _u(0x00000080)
687 #define PSM_DONE_BUSFABRIC_MSB    _u(7)
688 #define PSM_DONE_BUSFABRIC_LSB    _u(7)
689 #define PSM_DONE_BUSFABRIC_ACCESS "RO"
690 // -----------------------------------------------------------------------------
691 // Field       : PSM_DONE_PSM_READY
692 #define PSM_DONE_PSM_READY_RESET  _u(0x0)
693 #define PSM_DONE_PSM_READY_BITS   _u(0x00000040)
694 #define PSM_DONE_PSM_READY_MSB    _u(6)
695 #define PSM_DONE_PSM_READY_LSB    _u(6)
696 #define PSM_DONE_PSM_READY_ACCESS "RO"
697 // -----------------------------------------------------------------------------
698 // Field       : PSM_DONE_CLOCKS
699 #define PSM_DONE_CLOCKS_RESET  _u(0x0)
700 #define PSM_DONE_CLOCKS_BITS   _u(0x00000020)
701 #define PSM_DONE_CLOCKS_MSB    _u(5)
702 #define PSM_DONE_CLOCKS_LSB    _u(5)
703 #define PSM_DONE_CLOCKS_ACCESS "RO"
704 // -----------------------------------------------------------------------------
705 // Field       : PSM_DONE_RESETS
706 #define PSM_DONE_RESETS_RESET  _u(0x0)
707 #define PSM_DONE_RESETS_BITS   _u(0x00000010)
708 #define PSM_DONE_RESETS_MSB    _u(4)
709 #define PSM_DONE_RESETS_LSB    _u(4)
710 #define PSM_DONE_RESETS_ACCESS "RO"
711 // -----------------------------------------------------------------------------
712 // Field       : PSM_DONE_XOSC
713 #define PSM_DONE_XOSC_RESET  _u(0x0)
714 #define PSM_DONE_XOSC_BITS   _u(0x00000008)
715 #define PSM_DONE_XOSC_MSB    _u(3)
716 #define PSM_DONE_XOSC_LSB    _u(3)
717 #define PSM_DONE_XOSC_ACCESS "RO"
718 // -----------------------------------------------------------------------------
719 // Field       : PSM_DONE_ROSC
720 #define PSM_DONE_ROSC_RESET  _u(0x0)
721 #define PSM_DONE_ROSC_BITS   _u(0x00000004)
722 #define PSM_DONE_ROSC_MSB    _u(2)
723 #define PSM_DONE_ROSC_LSB    _u(2)
724 #define PSM_DONE_ROSC_ACCESS "RO"
725 // -----------------------------------------------------------------------------
726 // Field       : PSM_DONE_OTP
727 #define PSM_DONE_OTP_RESET  _u(0x0)
728 #define PSM_DONE_OTP_BITS   _u(0x00000002)
729 #define PSM_DONE_OTP_MSB    _u(1)
730 #define PSM_DONE_OTP_LSB    _u(1)
731 #define PSM_DONE_OTP_ACCESS "RO"
732 // -----------------------------------------------------------------------------
733 // Field       : PSM_DONE_PROC_COLD
734 #define PSM_DONE_PROC_COLD_RESET  _u(0x0)
735 #define PSM_DONE_PROC_COLD_BITS   _u(0x00000001)
736 #define PSM_DONE_PROC_COLD_MSB    _u(0)
737 #define PSM_DONE_PROC_COLD_LSB    _u(0)
738 #define PSM_DONE_PROC_COLD_ACCESS "RO"
739 // =============================================================================
740 #endif // _HARDWARE_REGS_PSM_H
741 
742