1 /* 2 * Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause 3 * 4 * @file src/rp2_common/cmsis/stub/CMSIS/Device/RP2350/Include/RP2350.h 5 * @brief CMSIS HeaderFile 6 * @version 0.1 7 * @date Thu Aug 8 04:04:02 2024 8 * @note Generated by SVDConv V3.3.47 9 * from File 'src/rp2_common/cmsis/../../rp2350/hardware_regs/RP2350.svd', 10 * last modified on Thu Aug 8 03:59:33 2024 11 */ 12 13 14 /** @addtogroup Raspberry Pi 15 * @{ 16 */ 17 18 19 /** @addtogroup RP2350 20 * @{ 21 */ 22 23 24 #ifndef RP2350_H 25 #define RP2350_H 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif 30 31 32 /** @addtogroup Configuration_of_CMSIS 33 * @{ 34 */ 35 36 37 38 /* =========================================================================================================================== */ 39 /* ================ Interrupt Number Definition ================ */ 40 /* =========================================================================================================================== */ 41 42 typedef enum { 43 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ 44 Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ 45 NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ 46 HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ 47 MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation 48 and No Match */ 49 BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory 50 related Fault */ 51 UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 52 SecureFault_IRQn = -9, /*!< -9 Secure Fault Handler */ 53 SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ 54 DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ 55 PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ 56 SysTick_IRQn = -1, /*!< -1 System Tick Timer */ 57 /* =========================================== RP2350 Specific Interrupt Numbers =========================================== */ 58 TIMER0_IRQ_0_IRQn = 0, /*!< 0 TIMER0_IRQ_0 */ 59 TIMER0_IRQ_1_IRQn = 1, /*!< 1 TIMER0_IRQ_1 */ 60 TIMER0_IRQ_2_IRQn = 2, /*!< 2 TIMER0_IRQ_2 */ 61 TIMER0_IRQ_3_IRQn = 3, /*!< 3 TIMER0_IRQ_3 */ 62 TIMER1_IRQ_0_IRQn = 4, /*!< 4 TIMER1_IRQ_0 */ 63 TIMER1_IRQ_1_IRQn = 5, /*!< 5 TIMER1_IRQ_1 */ 64 TIMER1_IRQ_2_IRQn = 6, /*!< 6 TIMER1_IRQ_2 */ 65 TIMER1_IRQ_3_IRQn = 7, /*!< 7 TIMER1_IRQ_3 */ 66 PWM_IRQ_WRAP_0_IRQn = 8, /*!< 8 PWM_IRQ_WRAP_0 */ 67 PWM_IRQ_WRAP_1_IRQn = 9, /*!< 9 PWM_IRQ_WRAP_1 */ 68 DMA_IRQ_0_IRQn = 10, /*!< 10 DMA_IRQ_0 */ 69 DMA_IRQ_1_IRQn = 11, /*!< 11 DMA_IRQ_1 */ 70 DMA_IRQ_2_IRQn = 12, /*!< 12 DMA_IRQ_2 */ 71 DMA_IRQ_3_IRQn = 13, /*!< 13 DMA_IRQ_3 */ 72 USBCTRL_IRQ_IRQn = 14, /*!< 14 USBCTRL_IRQ */ 73 PIO0_IRQ_0_IRQn = 15, /*!< 15 PIO0_IRQ_0 */ 74 PIO0_IRQ_1_IRQn = 16, /*!< 16 PIO0_IRQ_1 */ 75 PIO1_IRQ_0_IRQn = 17, /*!< 17 PIO1_IRQ_0 */ 76 PIO1_IRQ_1_IRQn = 18, /*!< 18 PIO1_IRQ_1 */ 77 PIO2_IRQ_0_IRQn = 19, /*!< 19 PIO2_IRQ_0 */ 78 PIO2_IRQ_1_IRQn = 20, /*!< 20 PIO2_IRQ_1 */ 79 IO_IRQ_BANK0_IRQn = 21, /*!< 21 IO_IRQ_BANK0 */ 80 IO_IRQ_BANK0_NS_IRQn = 22, /*!< 22 IO_IRQ_BANK0_NS */ 81 IO_IRQ_QSPI_IRQn = 23, /*!< 23 IO_IRQ_QSPI */ 82 IO_IRQ_QSPI_NS_IRQn = 24, /*!< 24 IO_IRQ_QSPI_NS */ 83 SIO_IRQ_FIFO_IRQn = 25, /*!< 25 SIO_IRQ_FIFO */ 84 SIO_IRQ_BELL_IRQn = 26, /*!< 26 SIO_IRQ_BELL */ 85 SIO_IRQ_FIFO_NS_IRQn = 27, /*!< 27 SIO_IRQ_FIFO_NS */ 86 SIO_IRQ_BELL_NS_IRQn = 28, /*!< 28 SIO_IRQ_BELL_NS */ 87 SIO_IRQ_MTIMECMP_IRQn = 29, /*!< 29 SIO_IRQ_MTIMECMP */ 88 CLOCKS_IRQ_IRQn = 30, /*!< 30 CLOCKS_IRQ */ 89 SPI0_IRQ_IRQn = 31, /*!< 31 SPI0_IRQ */ 90 SPI1_IRQ_IRQn = 32, /*!< 32 SPI1_IRQ */ 91 UART0_IRQ_IRQn = 33, /*!< 33 UART0_IRQ */ 92 UART1_IRQ_IRQn = 34, /*!< 34 UART1_IRQ */ 93 ADC_IRQ_FIFO_IRQn = 35, /*!< 35 ADC_IRQ_FIFO */ 94 I2C0_IRQ_IRQn = 36, /*!< 36 I2C0_IRQ */ 95 I2C1_IRQ_IRQn = 37, /*!< 37 I2C1_IRQ */ 96 OTP_IRQ_IRQn = 38, /*!< 38 OTP_IRQ */ 97 TRNG_IRQ_IRQn = 39, /*!< 39 TRNG_IRQ */ 98 PLL_SYS_IRQ_IRQn = 42, /*!< 42 PLL_SYS_IRQ */ 99 PLL_USB_IRQ_IRQn = 43, /*!< 43 PLL_USB_IRQ */ 100 POWMAN_IRQ_POW_IRQn = 44, /*!< 44 POWMAN_IRQ_POW */ 101 POWMAN_IRQ_TIMER_IRQn = 45 /*!< 45 POWMAN_IRQ_TIMER */ 102 } IRQn_Type; 103 104 105 106 /* =========================================================================================================================== */ 107 /* ================ Processor and Core Peripheral Section ================ */ 108 /* =========================================================================================================================== */ 109 110 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */ 111 #define __CM33_REV 0x0100U /*!< CM33 Core Revision */ 112 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ 113 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 114 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ 115 #define __MPU_PRESENT 1 /*!< MPU present */ 116 #define __FPU_PRESENT 1 /*!< FPU present */ 117 #define __FPU_DP 0 /*!< Double Precision FPU */ 118 #define __DSP_PRESENT 1 /*!< DSP extension present */ 119 #define __SAUREGION_PRESENT 1 /*!< SAU region present */ 120 121 122 /** @} */ /* End of group Configuration_of_CMSIS */ 123 124 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ 125 #include "system_RP2350.h" /*!< RP2350 System */ 126 127 #ifndef __IM /*!< Fallback for older CMSIS versions */ 128 #define __IM __I 129 #endif 130 #ifndef __OM /*!< Fallback for older CMSIS versions */ 131 #define __OM __O 132 #endif 133 #ifndef __IOM /*!< Fallback for older CMSIS versions */ 134 #define __IOM __IO 135 #endif 136 137 138 /* =========================================================================================================================== */ 139 /* ================ Device Specific Peripheral Section ================ */ 140 /* =========================================================================================================================== */ 141 142 143 /** @addtogroup Device_Peripheral_peripherals 144 * @{ 145 */ 146 147 148 149 /* =========================================================================================================================== */ 150 /* ================ RESETS ================ */ 151 /* =========================================================================================================================== */ 152 153 154 /** 155 * @brief RESETS (RESETS) 156 */ 157 158 typedef struct { /*!< RESETS Structure */ 159 __IOM uint32_t RESET; /*!< RESET */ 160 __IOM uint32_t WDSEL; /*!< WDSEL */ 161 __IOM uint32_t RESET_DONE; /*!< RESET_DONE */ 162 } RESETS_Type; /*!< Size = 12 (0xc) */ 163 164 165 166 /* =========================================================================================================================== */ 167 /* ================ PSM ================ */ 168 /* =========================================================================================================================== */ 169 170 171 /** 172 * @brief PSM (PSM) 173 */ 174 175 typedef struct { /*!< PSM Structure */ 176 __IOM uint32_t FRCE_ON; /*!< Force block out of reset (i.e. power it on) */ 177 __IOM uint32_t FRCE_OFF; /*!< Force into reset (i.e. power it off) */ 178 __IOM uint32_t WDSEL; /*!< Set to 1 if the watchdog should reset this */ 179 __IOM uint32_t DONE; /*!< Is the subsystem ready? */ 180 } PSM_Type; /*!< Size = 16 (0x10) */ 181 182 183 184 /* =========================================================================================================================== */ 185 /* ================ CLOCKS ================ */ 186 /* =========================================================================================================================== */ 187 188 189 /** 190 * @brief CLOCKS (CLOCKS) 191 */ 192 193 typedef struct { /*!< CLOCKS Structure */ 194 __IOM uint32_t CLK_GPOUT0_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 195 __IOM uint32_t CLK_GPOUT0_DIV; /*!< CLK_GPOUT0_DIV */ 196 __IOM uint32_t CLK_GPOUT0_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 197 __IOM uint32_t CLK_GPOUT1_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 198 __IOM uint32_t CLK_GPOUT1_DIV; /*!< CLK_GPOUT1_DIV */ 199 __IOM uint32_t CLK_GPOUT1_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 200 __IOM uint32_t CLK_GPOUT2_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 201 __IOM uint32_t CLK_GPOUT2_DIV; /*!< CLK_GPOUT2_DIV */ 202 __IOM uint32_t CLK_GPOUT2_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 203 __IOM uint32_t CLK_GPOUT3_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 204 __IOM uint32_t CLK_GPOUT3_DIV; /*!< CLK_GPOUT3_DIV */ 205 __IOM uint32_t CLK_GPOUT3_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 206 __IOM uint32_t CLK_REF_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 207 __IOM uint32_t CLK_REF_DIV; /*!< CLK_REF_DIV */ 208 __IOM uint32_t CLK_REF_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 209 __IOM uint32_t CLK_SYS_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 210 __IOM uint32_t CLK_SYS_DIV; /*!< CLK_SYS_DIV */ 211 __IOM uint32_t CLK_SYS_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 212 __IOM uint32_t CLK_PERI_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 213 __IOM uint32_t CLK_PERI_DIV; /*!< CLK_PERI_DIV */ 214 __IOM uint32_t CLK_PERI_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 215 __IOM uint32_t CLK_HSTX_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 216 __IOM uint32_t CLK_HSTX_DIV; /*!< CLK_HSTX_DIV */ 217 __IOM uint32_t CLK_HSTX_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 218 __IOM uint32_t CLK_USB_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 219 __IOM uint32_t CLK_USB_DIV; /*!< CLK_USB_DIV */ 220 __IOM uint32_t CLK_USB_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 221 __IOM uint32_t CLK_ADC_CTRL; /*!< Clock control, can be changed on-the-fly (except for auxsrc) */ 222 __IOM uint32_t CLK_ADC_DIV; /*!< CLK_ADC_DIV */ 223 __IOM uint32_t CLK_ADC_SELECTED; /*!< Indicates which src is currently selected (one-hot) */ 224 __IOM uint32_t DFTCLK_XOSC_CTRL; /*!< DFTCLK_XOSC_CTRL */ 225 __IOM uint32_t DFTCLK_ROSC_CTRL; /*!< DFTCLK_ROSC_CTRL */ 226 __IOM uint32_t DFTCLK_LPOSC_CTRL; /*!< DFTCLK_LPOSC_CTRL */ 227 __IOM uint32_t CLK_SYS_RESUS_CTRL; /*!< CLK_SYS_RESUS_CTRL */ 228 __IOM uint32_t CLK_SYS_RESUS_STATUS; /*!< CLK_SYS_RESUS_STATUS */ 229 __IOM uint32_t FC0_REF_KHZ; /*!< Reference clock frequency in kHz */ 230 __IOM uint32_t FC0_MIN_KHZ; /*!< Minimum pass frequency in kHz. This is optional. Set to 0 if 231 you are not using the pass/fail flags */ 232 __IOM uint32_t FC0_MAX_KHZ; /*!< Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff 233 if you are not using the pass/fail flags */ 234 __IOM uint32_t FC0_DELAY; /*!< Delays the start of frequency counting to allow the mux to settle 235 Delay is measured in multiples of the reference clock period */ 236 __IOM uint32_t FC0_INTERVAL; /*!< The test interval is 0.98us * 2**interval, but let's call it 237 1us * 2**interval The default gives a test interval of 238 250us */ 239 __IOM uint32_t FC0_SRC; /*!< Clock sent to frequency counter, set to 0 when not required 240 Writing to this register initiates the frequency count */ 241 __IOM uint32_t FC0_STATUS; /*!< Frequency counter status */ 242 __IOM uint32_t FC0_RESULT; /*!< Result of frequency measurement, only valid when status_done=1 */ 243 __IOM uint32_t WAKE_EN0; /*!< enable clock in wake mode */ 244 __IOM uint32_t WAKE_EN1; /*!< enable clock in wake mode */ 245 __IOM uint32_t SLEEP_EN0; /*!< enable clock in sleep mode */ 246 __IOM uint32_t SLEEP_EN1; /*!< enable clock in sleep mode */ 247 __IOM uint32_t ENABLED0; /*!< indicates the state of the clock enable */ 248 __IOM uint32_t ENABLED1; /*!< indicates the state of the clock enable */ 249 __IOM uint32_t INTR; /*!< Raw Interrupts */ 250 __IOM uint32_t INTE; /*!< Interrupt Enable */ 251 __IOM uint32_t INTF; /*!< Interrupt Force */ 252 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 253 } CLOCKS_Type; /*!< Size = 212 (0xd4) */ 254 255 256 257 /* =========================================================================================================================== */ 258 /* ================ TICKS ================ */ 259 /* =========================================================================================================================== */ 260 261 262 /** 263 * @brief TICKS (TICKS) 264 */ 265 266 typedef struct { /*!< TICKS Structure */ 267 __IOM uint32_t PROC0_CTRL; /*!< Controls the tick generator */ 268 __IOM uint32_t PROC0_CYCLES; /*!< PROC0_CYCLES */ 269 __IOM uint32_t PROC0_COUNT; /*!< PROC0_COUNT */ 270 __IOM uint32_t PROC1_CTRL; /*!< Controls the tick generator */ 271 __IOM uint32_t PROC1_CYCLES; /*!< PROC1_CYCLES */ 272 __IOM uint32_t PROC1_COUNT; /*!< PROC1_COUNT */ 273 __IOM uint32_t TIMER0_CTRL; /*!< Controls the tick generator */ 274 __IOM uint32_t TIMER0_CYCLES; /*!< TIMER0_CYCLES */ 275 __IOM uint32_t TIMER0_COUNT; /*!< TIMER0_COUNT */ 276 __IOM uint32_t TIMER1_CTRL; /*!< Controls the tick generator */ 277 __IOM uint32_t TIMER1_CYCLES; /*!< TIMER1_CYCLES */ 278 __IOM uint32_t TIMER1_COUNT; /*!< TIMER1_COUNT */ 279 __IOM uint32_t WATCHDOG_CTRL; /*!< Controls the tick generator */ 280 __IOM uint32_t WATCHDOG_CYCLES; /*!< WATCHDOG_CYCLES */ 281 __IOM uint32_t WATCHDOG_COUNT; /*!< WATCHDOG_COUNT */ 282 __IOM uint32_t RISCV_CTRL; /*!< Controls the tick generator */ 283 __IOM uint32_t RISCV_CYCLES; /*!< RISCV_CYCLES */ 284 __IOM uint32_t RISCV_COUNT; /*!< RISCV_COUNT */ 285 } TICKS_Type; /*!< Size = 72 (0x48) */ 286 287 288 289 /* =========================================================================================================================== */ 290 /* ================ PADS_BANK0 ================ */ 291 /* =========================================================================================================================== */ 292 293 294 /** 295 * @brief PADS_BANK0 (PADS_BANK0) 296 */ 297 298 typedef struct { /*!< PADS_BANK0 Structure */ 299 __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ 300 __IOM uint32_t GPIO0; /*!< GPIO0 */ 301 __IOM uint32_t GPIO1; /*!< GPIO1 */ 302 __IOM uint32_t GPIO2; /*!< GPIO2 */ 303 __IOM uint32_t GPIO3; /*!< GPIO3 */ 304 __IOM uint32_t GPIO4; /*!< GPIO4 */ 305 __IOM uint32_t GPIO5; /*!< GPIO5 */ 306 __IOM uint32_t GPIO6; /*!< GPIO6 */ 307 __IOM uint32_t GPIO7; /*!< GPIO7 */ 308 __IOM uint32_t GPIO8; /*!< GPIO8 */ 309 __IOM uint32_t GPIO9; /*!< GPIO9 */ 310 __IOM uint32_t GPIO10; /*!< GPIO10 */ 311 __IOM uint32_t GPIO11; /*!< GPIO11 */ 312 __IOM uint32_t GPIO12; /*!< GPIO12 */ 313 __IOM uint32_t GPIO13; /*!< GPIO13 */ 314 __IOM uint32_t GPIO14; /*!< GPIO14 */ 315 __IOM uint32_t GPIO15; /*!< GPIO15 */ 316 __IOM uint32_t GPIO16; /*!< GPIO16 */ 317 __IOM uint32_t GPIO17; /*!< GPIO17 */ 318 __IOM uint32_t GPIO18; /*!< GPIO18 */ 319 __IOM uint32_t GPIO19; /*!< GPIO19 */ 320 __IOM uint32_t GPIO20; /*!< GPIO20 */ 321 __IOM uint32_t GPIO21; /*!< GPIO21 */ 322 __IOM uint32_t GPIO22; /*!< GPIO22 */ 323 __IOM uint32_t GPIO23; /*!< GPIO23 */ 324 __IOM uint32_t GPIO24; /*!< GPIO24 */ 325 __IOM uint32_t GPIO25; /*!< GPIO25 */ 326 __IOM uint32_t GPIO26; /*!< GPIO26 */ 327 __IOM uint32_t GPIO27; /*!< GPIO27 */ 328 __IOM uint32_t GPIO28; /*!< GPIO28 */ 329 __IOM uint32_t GPIO29; /*!< GPIO29 */ 330 __IOM uint32_t GPIO30; /*!< GPIO30 */ 331 __IOM uint32_t GPIO31; /*!< GPIO31 */ 332 __IOM uint32_t GPIO32; /*!< GPIO32 */ 333 __IOM uint32_t GPIO33; /*!< GPIO33 */ 334 __IOM uint32_t GPIO34; /*!< GPIO34 */ 335 __IOM uint32_t GPIO35; /*!< GPIO35 */ 336 __IOM uint32_t GPIO36; /*!< GPIO36 */ 337 __IOM uint32_t GPIO37; /*!< GPIO37 */ 338 __IOM uint32_t GPIO38; /*!< GPIO38 */ 339 __IOM uint32_t GPIO39; /*!< GPIO39 */ 340 __IOM uint32_t GPIO40; /*!< GPIO40 */ 341 __IOM uint32_t GPIO41; /*!< GPIO41 */ 342 __IOM uint32_t GPIO42; /*!< GPIO42 */ 343 __IOM uint32_t GPIO43; /*!< GPIO43 */ 344 __IOM uint32_t GPIO44; /*!< GPIO44 */ 345 __IOM uint32_t GPIO45; /*!< GPIO45 */ 346 __IOM uint32_t GPIO46; /*!< GPIO46 */ 347 __IOM uint32_t GPIO47; /*!< GPIO47 */ 348 __IOM uint32_t SWCLK; /*!< SWCLK */ 349 __IOM uint32_t SWD; /*!< SWD */ 350 } PADS_BANK0_Type; /*!< Size = 204 (0xcc) */ 351 352 353 354 /* =========================================================================================================================== */ 355 /* ================ PADS_QSPI ================ */ 356 /* =========================================================================================================================== */ 357 358 359 /** 360 * @brief PADS_QSPI (PADS_QSPI) 361 */ 362 363 typedef struct { /*!< PADS_QSPI Structure */ 364 __IOM uint32_t VOLTAGE_SELECT; /*!< Voltage select. Per bank control */ 365 __IOM uint32_t GPIO_QSPI_SCLK; /*!< GPIO_QSPI_SCLK */ 366 __IOM uint32_t GPIO_QSPI_SD0; /*!< GPIO_QSPI_SD0 */ 367 __IOM uint32_t GPIO_QSPI_SD1; /*!< GPIO_QSPI_SD1 */ 368 __IOM uint32_t GPIO_QSPI_SD2; /*!< GPIO_QSPI_SD2 */ 369 __IOM uint32_t GPIO_QSPI_SD3; /*!< GPIO_QSPI_SD3 */ 370 __IOM uint32_t GPIO_QSPI_SS; /*!< GPIO_QSPI_SS */ 371 } PADS_QSPI_Type; /*!< Size = 28 (0x1c) */ 372 373 374 375 /* =========================================================================================================================== */ 376 /* ================ IO_QSPI ================ */ 377 /* =========================================================================================================================== */ 378 379 380 /** 381 * @brief IO_QSPI (IO_QSPI) 382 */ 383 384 typedef struct { /*!< IO_QSPI Structure */ 385 __IOM uint32_t USBPHY_DP_STATUS; /*!< USBPHY_DP_STATUS */ 386 __IOM uint32_t USBPHY_DP_CTRL; /*!< USBPHY_DP_CTRL */ 387 __IOM uint32_t USBPHY_DM_STATUS; /*!< USBPHY_DM_STATUS */ 388 __IOM uint32_t USBPHY_DM_CTRL; /*!< USBPHY_DM_CTRL */ 389 __IOM uint32_t GPIO_QSPI_SCLK_STATUS; /*!< GPIO_QSPI_SCLK_STATUS */ 390 __IOM uint32_t GPIO_QSPI_SCLK_CTRL; /*!< GPIO_QSPI_SCLK_CTRL */ 391 __IOM uint32_t GPIO_QSPI_SS_STATUS; /*!< GPIO_QSPI_SS_STATUS */ 392 __IOM uint32_t GPIO_QSPI_SS_CTRL; /*!< GPIO_QSPI_SS_CTRL */ 393 __IOM uint32_t GPIO_QSPI_SD0_STATUS; /*!< GPIO_QSPI_SD0_STATUS */ 394 __IOM uint32_t GPIO_QSPI_SD0_CTRL; /*!< GPIO_QSPI_SD0_CTRL */ 395 __IOM uint32_t GPIO_QSPI_SD1_STATUS; /*!< GPIO_QSPI_SD1_STATUS */ 396 __IOM uint32_t GPIO_QSPI_SD1_CTRL; /*!< GPIO_QSPI_SD1_CTRL */ 397 __IOM uint32_t GPIO_QSPI_SD2_STATUS; /*!< GPIO_QSPI_SD2_STATUS */ 398 __IOM uint32_t GPIO_QSPI_SD2_CTRL; /*!< GPIO_QSPI_SD2_CTRL */ 399 __IOM uint32_t GPIO_QSPI_SD3_STATUS; /*!< GPIO_QSPI_SD3_STATUS */ 400 __IOM uint32_t GPIO_QSPI_SD3_CTRL; /*!< GPIO_QSPI_SD3_CTRL */ 401 __IM uint32_t RESERVED[112]; 402 __IOM uint32_t IRQSUMMARY_PROC0_SECURE; /*!< IRQSUMMARY_PROC0_SECURE */ 403 __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE; /*!< IRQSUMMARY_PROC0_NONSECURE */ 404 __IOM uint32_t IRQSUMMARY_PROC1_SECURE; /*!< IRQSUMMARY_PROC1_SECURE */ 405 __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE; /*!< IRQSUMMARY_PROC1_NONSECURE */ 406 __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE */ 407 __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE */ 408 __IOM uint32_t INTR; /*!< Raw Interrupts */ 409 __IOM uint32_t PROC0_INTE; /*!< Interrupt Enable for proc0 */ 410 __IOM uint32_t PROC0_INTF; /*!< Interrupt Force for proc0 */ 411 __IOM uint32_t PROC0_INTS; /*!< Interrupt status after masking & forcing for proc0 */ 412 __IOM uint32_t PROC1_INTE; /*!< Interrupt Enable for proc1 */ 413 __IOM uint32_t PROC1_INTF; /*!< Interrupt Force for proc1 */ 414 __IOM uint32_t PROC1_INTS; /*!< Interrupt status after masking & forcing for proc1 */ 415 __IOM uint32_t DORMANT_WAKE_INTE; /*!< Interrupt Enable for dormant_wake */ 416 __IOM uint32_t DORMANT_WAKE_INTF; /*!< Interrupt Force for dormant_wake */ 417 __IOM uint32_t DORMANT_WAKE_INTS; /*!< Interrupt status after masking & forcing for dormant_wake */ 418 } IO_QSPI_Type; /*!< Size = 576 (0x240) */ 419 420 421 422 /* =========================================================================================================================== */ 423 /* ================ IO_BANK0 ================ */ 424 /* =========================================================================================================================== */ 425 426 427 /** 428 * @brief IO_BANK0 (IO_BANK0) 429 */ 430 431 typedef struct { /*!< IO_BANK0 Structure */ 432 __IOM uint32_t GPIO0_STATUS; /*!< GPIO0_STATUS */ 433 __IOM uint32_t GPIO0_CTRL; /*!< GPIO0_CTRL */ 434 __IOM uint32_t GPIO1_STATUS; /*!< GPIO1_STATUS */ 435 __IOM uint32_t GPIO1_CTRL; /*!< GPIO1_CTRL */ 436 __IOM uint32_t GPIO2_STATUS; /*!< GPIO2_STATUS */ 437 __IOM uint32_t GPIO2_CTRL; /*!< GPIO2_CTRL */ 438 __IOM uint32_t GPIO3_STATUS; /*!< GPIO3_STATUS */ 439 __IOM uint32_t GPIO3_CTRL; /*!< GPIO3_CTRL */ 440 __IOM uint32_t GPIO4_STATUS; /*!< GPIO4_STATUS */ 441 __IOM uint32_t GPIO4_CTRL; /*!< GPIO4_CTRL */ 442 __IOM uint32_t GPIO5_STATUS; /*!< GPIO5_STATUS */ 443 __IOM uint32_t GPIO5_CTRL; /*!< GPIO5_CTRL */ 444 __IOM uint32_t GPIO6_STATUS; /*!< GPIO6_STATUS */ 445 __IOM uint32_t GPIO6_CTRL; /*!< GPIO6_CTRL */ 446 __IOM uint32_t GPIO7_STATUS; /*!< GPIO7_STATUS */ 447 __IOM uint32_t GPIO7_CTRL; /*!< GPIO7_CTRL */ 448 __IOM uint32_t GPIO8_STATUS; /*!< GPIO8_STATUS */ 449 __IOM uint32_t GPIO8_CTRL; /*!< GPIO8_CTRL */ 450 __IOM uint32_t GPIO9_STATUS; /*!< GPIO9_STATUS */ 451 __IOM uint32_t GPIO9_CTRL; /*!< GPIO9_CTRL */ 452 __IOM uint32_t GPIO10_STATUS; /*!< GPIO10_STATUS */ 453 __IOM uint32_t GPIO10_CTRL; /*!< GPIO10_CTRL */ 454 __IOM uint32_t GPIO11_STATUS; /*!< GPIO11_STATUS */ 455 __IOM uint32_t GPIO11_CTRL; /*!< GPIO11_CTRL */ 456 __IOM uint32_t GPIO12_STATUS; /*!< GPIO12_STATUS */ 457 __IOM uint32_t GPIO12_CTRL; /*!< GPIO12_CTRL */ 458 __IOM uint32_t GPIO13_STATUS; /*!< GPIO13_STATUS */ 459 __IOM uint32_t GPIO13_CTRL; /*!< GPIO13_CTRL */ 460 __IOM uint32_t GPIO14_STATUS; /*!< GPIO14_STATUS */ 461 __IOM uint32_t GPIO14_CTRL; /*!< GPIO14_CTRL */ 462 __IOM uint32_t GPIO15_STATUS; /*!< GPIO15_STATUS */ 463 __IOM uint32_t GPIO15_CTRL; /*!< GPIO15_CTRL */ 464 __IOM uint32_t GPIO16_STATUS; /*!< GPIO16_STATUS */ 465 __IOM uint32_t GPIO16_CTRL; /*!< GPIO16_CTRL */ 466 __IOM uint32_t GPIO17_STATUS; /*!< GPIO17_STATUS */ 467 __IOM uint32_t GPIO17_CTRL; /*!< GPIO17_CTRL */ 468 __IOM uint32_t GPIO18_STATUS; /*!< GPIO18_STATUS */ 469 __IOM uint32_t GPIO18_CTRL; /*!< GPIO18_CTRL */ 470 __IOM uint32_t GPIO19_STATUS; /*!< GPIO19_STATUS */ 471 __IOM uint32_t GPIO19_CTRL; /*!< GPIO19_CTRL */ 472 __IOM uint32_t GPIO20_STATUS; /*!< GPIO20_STATUS */ 473 __IOM uint32_t GPIO20_CTRL; /*!< GPIO20_CTRL */ 474 __IOM uint32_t GPIO21_STATUS; /*!< GPIO21_STATUS */ 475 __IOM uint32_t GPIO21_CTRL; /*!< GPIO21_CTRL */ 476 __IOM uint32_t GPIO22_STATUS; /*!< GPIO22_STATUS */ 477 __IOM uint32_t GPIO22_CTRL; /*!< GPIO22_CTRL */ 478 __IOM uint32_t GPIO23_STATUS; /*!< GPIO23_STATUS */ 479 __IOM uint32_t GPIO23_CTRL; /*!< GPIO23_CTRL */ 480 __IOM uint32_t GPIO24_STATUS; /*!< GPIO24_STATUS */ 481 __IOM uint32_t GPIO24_CTRL; /*!< GPIO24_CTRL */ 482 __IOM uint32_t GPIO25_STATUS; /*!< GPIO25_STATUS */ 483 __IOM uint32_t GPIO25_CTRL; /*!< GPIO25_CTRL */ 484 __IOM uint32_t GPIO26_STATUS; /*!< GPIO26_STATUS */ 485 __IOM uint32_t GPIO26_CTRL; /*!< GPIO26_CTRL */ 486 __IOM uint32_t GPIO27_STATUS; /*!< GPIO27_STATUS */ 487 __IOM uint32_t GPIO27_CTRL; /*!< GPIO27_CTRL */ 488 __IOM uint32_t GPIO28_STATUS; /*!< GPIO28_STATUS */ 489 __IOM uint32_t GPIO28_CTRL; /*!< GPIO28_CTRL */ 490 __IOM uint32_t GPIO29_STATUS; /*!< GPIO29_STATUS */ 491 __IOM uint32_t GPIO29_CTRL; /*!< GPIO29_CTRL */ 492 __IOM uint32_t GPIO30_STATUS; /*!< GPIO30_STATUS */ 493 __IOM uint32_t GPIO30_CTRL; /*!< GPIO30_CTRL */ 494 __IOM uint32_t GPIO31_STATUS; /*!< GPIO31_STATUS */ 495 __IOM uint32_t GPIO31_CTRL; /*!< GPIO31_CTRL */ 496 __IOM uint32_t GPIO32_STATUS; /*!< GPIO32_STATUS */ 497 __IOM uint32_t GPIO32_CTRL; /*!< GPIO32_CTRL */ 498 __IOM uint32_t GPIO33_STATUS; /*!< GPIO33_STATUS */ 499 __IOM uint32_t GPIO33_CTRL; /*!< GPIO33_CTRL */ 500 __IOM uint32_t GPIO34_STATUS; /*!< GPIO34_STATUS */ 501 __IOM uint32_t GPIO34_CTRL; /*!< GPIO34_CTRL */ 502 __IOM uint32_t GPIO35_STATUS; /*!< GPIO35_STATUS */ 503 __IOM uint32_t GPIO35_CTRL; /*!< GPIO35_CTRL */ 504 __IOM uint32_t GPIO36_STATUS; /*!< GPIO36_STATUS */ 505 __IOM uint32_t GPIO36_CTRL; /*!< GPIO36_CTRL */ 506 __IOM uint32_t GPIO37_STATUS; /*!< GPIO37_STATUS */ 507 __IOM uint32_t GPIO37_CTRL; /*!< GPIO37_CTRL */ 508 __IOM uint32_t GPIO38_STATUS; /*!< GPIO38_STATUS */ 509 __IOM uint32_t GPIO38_CTRL; /*!< GPIO38_CTRL */ 510 __IOM uint32_t GPIO39_STATUS; /*!< GPIO39_STATUS */ 511 __IOM uint32_t GPIO39_CTRL; /*!< GPIO39_CTRL */ 512 __IOM uint32_t GPIO40_STATUS; /*!< GPIO40_STATUS */ 513 __IOM uint32_t GPIO40_CTRL; /*!< GPIO40_CTRL */ 514 __IOM uint32_t GPIO41_STATUS; /*!< GPIO41_STATUS */ 515 __IOM uint32_t GPIO41_CTRL; /*!< GPIO41_CTRL */ 516 __IOM uint32_t GPIO42_STATUS; /*!< GPIO42_STATUS */ 517 __IOM uint32_t GPIO42_CTRL; /*!< GPIO42_CTRL */ 518 __IOM uint32_t GPIO43_STATUS; /*!< GPIO43_STATUS */ 519 __IOM uint32_t GPIO43_CTRL; /*!< GPIO43_CTRL */ 520 __IOM uint32_t GPIO44_STATUS; /*!< GPIO44_STATUS */ 521 __IOM uint32_t GPIO44_CTRL; /*!< GPIO44_CTRL */ 522 __IOM uint32_t GPIO45_STATUS; /*!< GPIO45_STATUS */ 523 __IOM uint32_t GPIO45_CTRL; /*!< GPIO45_CTRL */ 524 __IOM uint32_t GPIO46_STATUS; /*!< GPIO46_STATUS */ 525 __IOM uint32_t GPIO46_CTRL; /*!< GPIO46_CTRL */ 526 __IOM uint32_t GPIO47_STATUS; /*!< GPIO47_STATUS */ 527 __IOM uint32_t GPIO47_CTRL; /*!< GPIO47_CTRL */ 528 __IM uint32_t RESERVED[32]; 529 __IOM uint32_t IRQSUMMARY_PROC0_SECURE0; /*!< IRQSUMMARY_PROC0_SECURE0 */ 530 __IOM uint32_t IRQSUMMARY_PROC0_SECURE1; /*!< IRQSUMMARY_PROC0_SECURE1 */ 531 __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE0; /*!< IRQSUMMARY_PROC0_NONSECURE0 */ 532 __IOM uint32_t IRQSUMMARY_PROC0_NONSECURE1; /*!< IRQSUMMARY_PROC0_NONSECURE1 */ 533 __IOM uint32_t IRQSUMMARY_PROC1_SECURE0; /*!< IRQSUMMARY_PROC1_SECURE0 */ 534 __IOM uint32_t IRQSUMMARY_PROC1_SECURE1; /*!< IRQSUMMARY_PROC1_SECURE1 */ 535 __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE0; /*!< IRQSUMMARY_PROC1_NONSECURE0 */ 536 __IOM uint32_t IRQSUMMARY_PROC1_NONSECURE1; /*!< IRQSUMMARY_PROC1_NONSECURE1 */ 537 __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE0 */ 538 __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_SECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_SECURE1 */ 539 __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE0;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE0 */ 540 __IOM uint32_t IRQSUMMARY_DORMANT_WAKE_NONSECURE1;/*!< IRQSUMMARY_DORMANT_WAKE_NONSECURE1 */ 541 __IOM uint32_t INTR0; /*!< Raw Interrupts */ 542 __IOM uint32_t INTR1; /*!< Raw Interrupts */ 543 __IOM uint32_t INTR2; /*!< Raw Interrupts */ 544 __IOM uint32_t INTR3; /*!< Raw Interrupts */ 545 __IOM uint32_t INTR4; /*!< Raw Interrupts */ 546 __IOM uint32_t INTR5; /*!< Raw Interrupts */ 547 __IOM uint32_t PROC0_INTE0; /*!< Interrupt Enable for proc0 */ 548 __IOM uint32_t PROC0_INTE1; /*!< Interrupt Enable for proc0 */ 549 __IOM uint32_t PROC0_INTE2; /*!< Interrupt Enable for proc0 */ 550 __IOM uint32_t PROC0_INTE3; /*!< Interrupt Enable for proc0 */ 551 __IOM uint32_t PROC0_INTE4; /*!< Interrupt Enable for proc0 */ 552 __IOM uint32_t PROC0_INTE5; /*!< Interrupt Enable for proc0 */ 553 __IOM uint32_t PROC0_INTF0; /*!< Interrupt Force for proc0 */ 554 __IOM uint32_t PROC0_INTF1; /*!< Interrupt Force for proc0 */ 555 __IOM uint32_t PROC0_INTF2; /*!< Interrupt Force for proc0 */ 556 __IOM uint32_t PROC0_INTF3; /*!< Interrupt Force for proc0 */ 557 __IOM uint32_t PROC0_INTF4; /*!< Interrupt Force for proc0 */ 558 __IOM uint32_t PROC0_INTF5; /*!< Interrupt Force for proc0 */ 559 __IOM uint32_t PROC0_INTS0; /*!< Interrupt status after masking & forcing for proc0 */ 560 __IOM uint32_t PROC0_INTS1; /*!< Interrupt status after masking & forcing for proc0 */ 561 __IOM uint32_t PROC0_INTS2; /*!< Interrupt status after masking & forcing for proc0 */ 562 __IOM uint32_t PROC0_INTS3; /*!< Interrupt status after masking & forcing for proc0 */ 563 __IOM uint32_t PROC0_INTS4; /*!< Interrupt status after masking & forcing for proc0 */ 564 __IOM uint32_t PROC0_INTS5; /*!< Interrupt status after masking & forcing for proc0 */ 565 __IOM uint32_t PROC1_INTE0; /*!< Interrupt Enable for proc1 */ 566 __IOM uint32_t PROC1_INTE1; /*!< Interrupt Enable for proc1 */ 567 __IOM uint32_t PROC1_INTE2; /*!< Interrupt Enable for proc1 */ 568 __IOM uint32_t PROC1_INTE3; /*!< Interrupt Enable for proc1 */ 569 __IOM uint32_t PROC1_INTE4; /*!< Interrupt Enable for proc1 */ 570 __IOM uint32_t PROC1_INTE5; /*!< Interrupt Enable for proc1 */ 571 __IOM uint32_t PROC1_INTF0; /*!< Interrupt Force for proc1 */ 572 __IOM uint32_t PROC1_INTF1; /*!< Interrupt Force for proc1 */ 573 __IOM uint32_t PROC1_INTF2; /*!< Interrupt Force for proc1 */ 574 __IOM uint32_t PROC1_INTF3; /*!< Interrupt Force for proc1 */ 575 __IOM uint32_t PROC1_INTF4; /*!< Interrupt Force for proc1 */ 576 __IOM uint32_t PROC1_INTF5; /*!< Interrupt Force for proc1 */ 577 __IOM uint32_t PROC1_INTS0; /*!< Interrupt status after masking & forcing for proc1 */ 578 __IOM uint32_t PROC1_INTS1; /*!< Interrupt status after masking & forcing for proc1 */ 579 __IOM uint32_t PROC1_INTS2; /*!< Interrupt status after masking & forcing for proc1 */ 580 __IOM uint32_t PROC1_INTS3; /*!< Interrupt status after masking & forcing for proc1 */ 581 __IOM uint32_t PROC1_INTS4; /*!< Interrupt status after masking & forcing for proc1 */ 582 __IOM uint32_t PROC1_INTS5; /*!< Interrupt status after masking & forcing for proc1 */ 583 __IOM uint32_t DORMANT_WAKE_INTE0; /*!< Interrupt Enable for dormant_wake */ 584 __IOM uint32_t DORMANT_WAKE_INTE1; /*!< Interrupt Enable for dormant_wake */ 585 __IOM uint32_t DORMANT_WAKE_INTE2; /*!< Interrupt Enable for dormant_wake */ 586 __IOM uint32_t DORMANT_WAKE_INTE3; /*!< Interrupt Enable for dormant_wake */ 587 __IOM uint32_t DORMANT_WAKE_INTE4; /*!< Interrupt Enable for dormant_wake */ 588 __IOM uint32_t DORMANT_WAKE_INTE5; /*!< Interrupt Enable for dormant_wake */ 589 __IOM uint32_t DORMANT_WAKE_INTF0; /*!< Interrupt Force for dormant_wake */ 590 __IOM uint32_t DORMANT_WAKE_INTF1; /*!< Interrupt Force for dormant_wake */ 591 __IOM uint32_t DORMANT_WAKE_INTF2; /*!< Interrupt Force for dormant_wake */ 592 __IOM uint32_t DORMANT_WAKE_INTF3; /*!< Interrupt Force for dormant_wake */ 593 __IOM uint32_t DORMANT_WAKE_INTF4; /*!< Interrupt Force for dormant_wake */ 594 __IOM uint32_t DORMANT_WAKE_INTF5; /*!< Interrupt Force for dormant_wake */ 595 __IOM uint32_t DORMANT_WAKE_INTS0; /*!< Interrupt status after masking & forcing for dormant_wake */ 596 __IOM uint32_t DORMANT_WAKE_INTS1; /*!< Interrupt status after masking & forcing for dormant_wake */ 597 __IOM uint32_t DORMANT_WAKE_INTS2; /*!< Interrupt status after masking & forcing for dormant_wake */ 598 __IOM uint32_t DORMANT_WAKE_INTS3; /*!< Interrupt status after masking & forcing for dormant_wake */ 599 __IOM uint32_t DORMANT_WAKE_INTS4; /*!< Interrupt status after masking & forcing for dormant_wake */ 600 __IOM uint32_t DORMANT_WAKE_INTS5; /*!< Interrupt status after masking & forcing for dormant_wake */ 601 } IO_BANK0_Type; /*!< Size = 800 (0x320) */ 602 603 604 605 /* =========================================================================================================================== */ 606 /* ================ SYSINFO ================ */ 607 /* =========================================================================================================================== */ 608 609 610 /** 611 * @brief SYSINFO (SYSINFO) 612 */ 613 614 typedef struct { /*!< SYSINFO Structure */ 615 __IOM uint32_t CHIP_ID; /*!< JEDEC JEP-106 compliant chip identifier. */ 616 __IOM uint32_t PACKAGE_SEL; /*!< PACKAGE_SEL */ 617 __IOM uint32_t PLATFORM; /*!< Platform register. Allows software to know what environment 618 it is running in during pre-production development. Post-production, 619 the PLATFORM is always ASIC, non-SIM. */ 620 __IM uint32_t RESERVED[2]; 621 __IOM uint32_t GITREF_RP2350; /*!< Git hash of the chip source. Used to identify chip version. */ 622 } SYSINFO_Type; /*!< Size = 24 (0x18) */ 623 624 625 626 /* =========================================================================================================================== */ 627 /* ================ SHA256 ================ */ 628 /* =========================================================================================================================== */ 629 630 631 /** 632 * @brief SHA-256 hash function implementation (SHA256) 633 */ 634 635 typedef struct { /*!< SHA256 Structure */ 636 __IOM uint32_t CSR; /*!< Control and status register */ 637 __IOM uint32_t WDATA; /*!< Write data register */ 638 __IOM uint32_t SUM0; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 639 is 0. */ 640 __IOM uint32_t SUM1; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 641 is 0. */ 642 __IOM uint32_t SUM2; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 643 is 0. */ 644 __IOM uint32_t SUM3; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 645 is 0. */ 646 __IOM uint32_t SUM4; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 647 is 0. */ 648 __IOM uint32_t SUM5; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 649 is 0. */ 650 __IOM uint32_t SUM6; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 651 is 0. */ 652 __IOM uint32_t SUM7; /*!< 256-bit checksum result. Contents are undefined when CSR_SUM_VLD 653 is 0. */ 654 } SHA256_Type; /*!< Size = 40 (0x28) */ 655 656 657 658 /* =========================================================================================================================== */ 659 /* ================ HSTX_FIFO ================ */ 660 /* =========================================================================================================================== */ 661 662 663 /** 664 * @brief FIFO status and write access for HSTX (HSTX_FIFO) 665 */ 666 667 typedef struct { /*!< HSTX_FIFO Structure */ 668 __IOM uint32_t STAT; /*!< FIFO status */ 669 __IOM uint32_t FIFO; /*!< Write access to FIFO */ 670 } HSTX_FIFO_Type; /*!< Size = 8 (0x8) */ 671 672 673 674 /* =========================================================================================================================== */ 675 /* ================ HSTX_CTRL ================ */ 676 /* =========================================================================================================================== */ 677 678 679 /** 680 * @brief Control interface to HSTX. For FIFO write access and status, see the HSTX_FIFO register block. (HSTX_CTRL) 681 */ 682 683 typedef struct { /*!< HSTX_CTRL Structure */ 684 __IOM uint32_t CSR; /*!< CSR */ 685 __IOM uint32_t BIT0; /*!< Data control register for output bit 0 */ 686 __IOM uint32_t BIT1; /*!< Data control register for output bit 1 */ 687 __IOM uint32_t BIT2; /*!< Data control register for output bit 2 */ 688 __IOM uint32_t BIT3; /*!< Data control register for output bit 3 */ 689 __IOM uint32_t BIT4; /*!< Data control register for output bit 4 */ 690 __IOM uint32_t BIT5; /*!< Data control register for output bit 5 */ 691 __IOM uint32_t BIT6; /*!< Data control register for output bit 6 */ 692 __IOM uint32_t BIT7; /*!< Data control register for output bit 7 */ 693 __IOM uint32_t EXPAND_SHIFT; /*!< Configure the optional shifter inside the command expander */ 694 __IOM uint32_t EXPAND_TMDS; /*!< Configure the optional TMDS encoder inside the command expander */ 695 } HSTX_CTRL_Type; /*!< Size = 44 (0x2c) */ 696 697 698 699 /* =========================================================================================================================== */ 700 /* ================ EPPB ================ */ 701 /* =========================================================================================================================== */ 702 703 704 /** 705 * @brief Cortex-M33 EPPB vendor register block for RP2350 (EPPB) 706 */ 707 708 typedef struct { /*!< EPPB Structure */ 709 __IOM uint32_t NMI_MASK0; /*!< NMI mask for IRQs 0 through 31. This register is core-local, 710 and is reset by a processor warm reset. */ 711 __IOM uint32_t NMI_MASK1; /*!< NMI mask for IRQs 0 though 51. This register is core-local, 712 and is reset by a processor warm reset. */ 713 __IOM uint32_t SLEEPCTRL; /*!< Nonstandard sleep control register */ 714 } EPPB_Type; /*!< Size = 12 (0xc) */ 715 716 717 718 /* =========================================================================================================================== */ 719 /* ================ PPB ================ */ 720 /* =========================================================================================================================== */ 721 722 723 /** 724 * @brief TEAL registers accessible through the debug interface (PPB) 725 */ 726 727 typedef struct { /*!< PPB Structure */ 728 __IOM uint32_t ITM_STIM0; /*!< Provides the interface for generating Instrumentation packets */ 729 __IOM uint32_t ITM_STIM1; /*!< Provides the interface for generating Instrumentation packets */ 730 __IOM uint32_t ITM_STIM2; /*!< Provides the interface for generating Instrumentation packets */ 731 __IOM uint32_t ITM_STIM3; /*!< Provides the interface for generating Instrumentation packets */ 732 __IOM uint32_t ITM_STIM4; /*!< Provides the interface for generating Instrumentation packets */ 733 __IOM uint32_t ITM_STIM5; /*!< Provides the interface for generating Instrumentation packets */ 734 __IOM uint32_t ITM_STIM6; /*!< Provides the interface for generating Instrumentation packets */ 735 __IOM uint32_t ITM_STIM7; /*!< Provides the interface for generating Instrumentation packets */ 736 __IOM uint32_t ITM_STIM8; /*!< Provides the interface for generating Instrumentation packets */ 737 __IOM uint32_t ITM_STIM9; /*!< Provides the interface for generating Instrumentation packets */ 738 __IOM uint32_t ITM_STIM10; /*!< Provides the interface for generating Instrumentation packets */ 739 __IOM uint32_t ITM_STIM11; /*!< Provides the interface for generating Instrumentation packets */ 740 __IOM uint32_t ITM_STIM12; /*!< Provides the interface for generating Instrumentation packets */ 741 __IOM uint32_t ITM_STIM13; /*!< Provides the interface for generating Instrumentation packets */ 742 __IOM uint32_t ITM_STIM14; /*!< Provides the interface for generating Instrumentation packets */ 743 __IOM uint32_t ITM_STIM15; /*!< Provides the interface for generating Instrumentation packets */ 744 __IOM uint32_t ITM_STIM16; /*!< Provides the interface for generating Instrumentation packets */ 745 __IOM uint32_t ITM_STIM17; /*!< Provides the interface for generating Instrumentation packets */ 746 __IOM uint32_t ITM_STIM18; /*!< Provides the interface for generating Instrumentation packets */ 747 __IOM uint32_t ITM_STIM19; /*!< Provides the interface for generating Instrumentation packets */ 748 __IOM uint32_t ITM_STIM20; /*!< Provides the interface for generating Instrumentation packets */ 749 __IOM uint32_t ITM_STIM21; /*!< Provides the interface for generating Instrumentation packets */ 750 __IOM uint32_t ITM_STIM22; /*!< Provides the interface for generating Instrumentation packets */ 751 __IOM uint32_t ITM_STIM23; /*!< Provides the interface for generating Instrumentation packets */ 752 __IOM uint32_t ITM_STIM24; /*!< Provides the interface for generating Instrumentation packets */ 753 __IOM uint32_t ITM_STIM25; /*!< Provides the interface for generating Instrumentation packets */ 754 __IOM uint32_t ITM_STIM26; /*!< Provides the interface for generating Instrumentation packets */ 755 __IOM uint32_t ITM_STIM27; /*!< Provides the interface for generating Instrumentation packets */ 756 __IOM uint32_t ITM_STIM28; /*!< Provides the interface for generating Instrumentation packets */ 757 __IOM uint32_t ITM_STIM29; /*!< Provides the interface for generating Instrumentation packets */ 758 __IOM uint32_t ITM_STIM30; /*!< Provides the interface for generating Instrumentation packets */ 759 __IOM uint32_t ITM_STIM31; /*!< Provides the interface for generating Instrumentation packets */ 760 __IM uint32_t RESERVED[864]; 761 __IOM uint32_t ITM_TER0; /*!< Provide an individual enable bit for each ITM_STIM register */ 762 __IM uint32_t RESERVED1[15]; 763 __IOM uint32_t ITM_TPR; /*!< Controls which stimulus ports can be accessed by unprivileged 764 code */ 765 __IM uint32_t RESERVED2[15]; 766 __IOM uint32_t ITM_TCR; /*!< Configures and controls transfers through the ITM interface */ 767 __IM uint32_t RESERVED3[27]; 768 __IOM uint32_t INT_ATREADY; /*!< Integration Mode: Read ATB Ready */ 769 __IM uint32_t RESERVED4; 770 __IOM uint32_t INT_ATVALID; /*!< Integration Mode: Write ATB Valid */ 771 __IM uint32_t RESERVED5; 772 __IOM uint32_t ITM_ITCTRL; /*!< Integration Mode Control Register */ 773 __IM uint32_t RESERVED6[46]; 774 __IOM uint32_t ITM_DEVARCH; /*!< Provides CoreSight discovery information for the ITM */ 775 __IM uint32_t RESERVED7[3]; 776 __IOM uint32_t ITM_DEVTYPE; /*!< Provides CoreSight discovery information for the ITM */ 777 __IOM uint32_t ITM_PIDR4; /*!< Provides CoreSight discovery information for the ITM */ 778 __IOM uint32_t ITM_PIDR5; /*!< Provides CoreSight discovery information for the ITM */ 779 __IOM uint32_t ITM_PIDR6; /*!< Provides CoreSight discovery information for the ITM */ 780 __IOM uint32_t ITM_PIDR7; /*!< Provides CoreSight discovery information for the ITM */ 781 __IOM uint32_t ITM_PIDR0; /*!< Provides CoreSight discovery information for the ITM */ 782 __IOM uint32_t ITM_PIDR1; /*!< Provides CoreSight discovery information for the ITM */ 783 __IOM uint32_t ITM_PIDR2; /*!< Provides CoreSight discovery information for the ITM */ 784 __IOM uint32_t ITM_PIDR3; /*!< Provides CoreSight discovery information for the ITM */ 785 __IOM uint32_t ITM_CIDR0; /*!< Provides CoreSight discovery information for the ITM */ 786 __IOM uint32_t ITM_CIDR1; /*!< Provides CoreSight discovery information for the ITM */ 787 __IOM uint32_t ITM_CIDR2; /*!< Provides CoreSight discovery information for the ITM */ 788 __IOM uint32_t ITM_CIDR3; /*!< Provides CoreSight discovery information for the ITM */ 789 __IOM uint32_t DWT_CTRL; /*!< Provides configuration and status information for the DWT unit, 790 and used to control features of the unit */ 791 __IOM uint32_t DWT_CYCCNT; /*!< Shows or sets the value of the processor cycle counter, CYCCNT */ 792 __IM uint32_t RESERVED8; 793 __IOM uint32_t DWT_EXCCNT; /*!< Counts the total cycles spent in exception processing */ 794 __IM uint32_t RESERVED9; 795 __IOM uint32_t DWT_LSUCNT; /*!< Increments on the additional cycles required to execute all 796 load or store instructions */ 797 __IOM uint32_t DWT_FOLDCNT; /*!< Increments on the additional cycles required to execute all 798 load or store instructions */ 799 __IM uint32_t RESERVED10; 800 __IOM uint32_t DWT_COMP0; /*!< Provides a reference value for use by watchpoint comparator 801 0 */ 802 __IM uint32_t RESERVED11; 803 __IOM uint32_t DWT_FUNCTION0; /*!< Controls the operation of watchpoint comparator 0 */ 804 __IM uint32_t RESERVED12; 805 __IOM uint32_t DWT_COMP1; /*!< Provides a reference value for use by watchpoint comparator 806 1 */ 807 __IM uint32_t RESERVED13; 808 __IOM uint32_t DWT_FUNCTION1; /*!< Controls the operation of watchpoint comparator 1 */ 809 __IM uint32_t RESERVED14; 810 __IOM uint32_t DWT_COMP2; /*!< Provides a reference value for use by watchpoint comparator 811 2 */ 812 __IM uint32_t RESERVED15; 813 __IOM uint32_t DWT_FUNCTION2; /*!< Controls the operation of watchpoint comparator 2 */ 814 __IM uint32_t RESERVED16; 815 __IOM uint32_t DWT_COMP3; /*!< Provides a reference value for use by watchpoint comparator 816 3 */ 817 __IM uint32_t RESERVED17; 818 __IOM uint32_t DWT_FUNCTION3; /*!< Controls the operation of watchpoint comparator 3 */ 819 __IM uint32_t RESERVED18[984]; 820 __IOM uint32_t DWT_DEVARCH; /*!< Provides CoreSight discovery information for the DWT */ 821 __IM uint32_t RESERVED19[3]; 822 __IOM uint32_t DWT_DEVTYPE; /*!< Provides CoreSight discovery information for the DWT */ 823 __IOM uint32_t DWT_PIDR4; /*!< Provides CoreSight discovery information for the DWT */ 824 __IOM uint32_t DWT_PIDR5; /*!< Provides CoreSight discovery information for the DWT */ 825 __IOM uint32_t DWT_PIDR6; /*!< Provides CoreSight discovery information for the DWT */ 826 __IOM uint32_t DWT_PIDR7; /*!< Provides CoreSight discovery information for the DWT */ 827 __IOM uint32_t DWT_PIDR0; /*!< Provides CoreSight discovery information for the DWT */ 828 __IOM uint32_t DWT_PIDR1; /*!< Provides CoreSight discovery information for the DWT */ 829 __IOM uint32_t DWT_PIDR2; /*!< Provides CoreSight discovery information for the DWT */ 830 __IOM uint32_t DWT_PIDR3; /*!< Provides CoreSight discovery information for the DWT */ 831 __IOM uint32_t DWT_CIDR0; /*!< Provides CoreSight discovery information for the DWT */ 832 __IOM uint32_t DWT_CIDR1; /*!< Provides CoreSight discovery information for the DWT */ 833 __IOM uint32_t DWT_CIDR2; /*!< Provides CoreSight discovery information for the DWT */ 834 __IOM uint32_t DWT_CIDR3; /*!< Provides CoreSight discovery information for the DWT */ 835 __IOM uint32_t FP_CTRL; /*!< Provides FPB implementation information, and the global enable 836 for the FPB unit */ 837 __IOM uint32_t FP_REMAP; /*!< Indicates whether the implementation supports Flash Patch remap 838 and, if it does, holds the target address for remap */ 839 __IOM uint32_t FP_COMP0; /*!< Holds an address for comparison. The effect of the match depends 840 on the configuration of the FPB and whether the comparator 841 is an instruction address comparator or a literal address 842 comparator */ 843 __IOM uint32_t FP_COMP1; /*!< Holds an address for comparison. The effect of the match depends 844 on the configuration of the FPB and whether the comparator 845 is an instruction address comparator or a literal address 846 comparator */ 847 __IOM uint32_t FP_COMP2; /*!< Holds an address for comparison. The effect of the match depends 848 on the configuration of the FPB and whether the comparator 849 is an instruction address comparator or a literal address 850 comparator */ 851 __IOM uint32_t FP_COMP3; /*!< Holds an address for comparison. The effect of the match depends 852 on the configuration of the FPB and whether the comparator 853 is an instruction address comparator or a literal address 854 comparator */ 855 __IOM uint32_t FP_COMP4; /*!< Holds an address for comparison. The effect of the match depends 856 on the configuration of the FPB and whether the comparator 857 is an instruction address comparator or a literal address 858 comparator */ 859 __IOM uint32_t FP_COMP5; /*!< Holds an address for comparison. The effect of the match depends 860 on the configuration of the FPB and whether the comparator 861 is an instruction address comparator or a literal address 862 comparator */ 863 __IOM uint32_t FP_COMP6; /*!< Holds an address for comparison. The effect of the match depends 864 on the configuration of the FPB and whether the comparator 865 is an instruction address comparator or a literal address 866 comparator */ 867 __IOM uint32_t FP_COMP7; /*!< Holds an address for comparison. The effect of the match depends 868 on the configuration of the FPB and whether the comparator 869 is an instruction address comparator or a literal address 870 comparator */ 871 __IM uint32_t RESERVED20[997]; 872 __IOM uint32_t FP_DEVARCH; /*!< Provides CoreSight discovery information for the FPB */ 873 __IM uint32_t RESERVED21[3]; 874 __IOM uint32_t FP_DEVTYPE; /*!< Provides CoreSight discovery information for the FPB */ 875 __IOM uint32_t FP_PIDR4; /*!< Provides CoreSight discovery information for the FP */ 876 __IOM uint32_t FP_PIDR5; /*!< Provides CoreSight discovery information for the FP */ 877 __IOM uint32_t FP_PIDR6; /*!< Provides CoreSight discovery information for the FP */ 878 __IOM uint32_t FP_PIDR7; /*!< Provides CoreSight discovery information for the FP */ 879 __IOM uint32_t FP_PIDR0; /*!< Provides CoreSight discovery information for the FP */ 880 __IOM uint32_t FP_PIDR1; /*!< Provides CoreSight discovery information for the FP */ 881 __IOM uint32_t FP_PIDR2; /*!< Provides CoreSight discovery information for the FP */ 882 __IOM uint32_t FP_PIDR3; /*!< Provides CoreSight discovery information for the FP */ 883 __IOM uint32_t FP_CIDR0; /*!< Provides CoreSight discovery information for the FP */ 884 __IOM uint32_t FP_CIDR1; /*!< Provides CoreSight discovery information for the FP */ 885 __IOM uint32_t FP_CIDR2; /*!< Provides CoreSight discovery information for the FP */ 886 __IOM uint32_t FP_CIDR3; /*!< Provides CoreSight discovery information for the FP */ 887 __IM uint32_t RESERVED22[11265]; 888 __IOM uint32_t ICTR; /*!< Provides information about the interrupt controller */ 889 __IOM uint32_t ACTLR; /*!< Provides IMPLEMENTATION DEFINED configuration and control options */ 890 __IM uint32_t RESERVED23; 891 __IOM uint32_t SYST_CSR; /*!< Use the SysTick Control and Status Register to enable the SysTick 892 features. */ 893 __IOM uint32_t SYST_RVR; /*!< Use the SysTick Reload Value Register to specify the start value 894 to load into the current value register when the counter 895 reaches 0. It can be any value between 0 and 0x00FFFFFF. 896 A start value of 0 is possible, but has no effect because 897 the SysTick interrupt and COUNTFLAG are activated when 898 counting from 1 to 0. The reset value of this register 899 is UNKNOWN. To generate a multi-shot timer with a period 900 of N processor clock cycles, use a RELOAD value of N-1. 901 For example, if the SysTick interrupt is required every 902 100 clock pulses, set RELOAD to 99. */ 903 __IOM uint32_t SYST_CVR; /*!< Use the SysTick Current Value Register to find the current value 904 in the register. The reset value of this register is UNKNOWN. */ 905 __IOM uint32_t SYST_CALIB; /*!< Use the SysTick Calibration Value Register to enable software 906 to scale to any required speed using divide and multiply. */ 907 __IM uint32_t RESERVED24[56]; 908 __IOM uint32_t NVIC_ISER0; /*!< Enables or reads the enabled state of each group of 32 interrupts */ 909 __IOM uint32_t NVIC_ISER1; /*!< Enables or reads the enabled state of each group of 32 interrupts */ 910 __IM uint32_t RESERVED25[30]; 911 __IOM uint32_t NVIC_ICER0; /*!< Clears or reads the enabled state of each group of 32 interrupts */ 912 __IOM uint32_t NVIC_ICER1; /*!< Clears or reads the enabled state of each group of 32 interrupts */ 913 __IM uint32_t RESERVED26[30]; 914 __IOM uint32_t NVIC_ISPR0; /*!< Enables or reads the pending state of each group of 32 interrupts */ 915 __IOM uint32_t NVIC_ISPR1; /*!< Enables or reads the pending state of each group of 32 interrupts */ 916 __IM uint32_t RESERVED27[30]; 917 __IOM uint32_t NVIC_ICPR0; /*!< Clears or reads the pending state of each group of 32 interrupts */ 918 __IOM uint32_t NVIC_ICPR1; /*!< Clears or reads the pending state of each group of 32 interrupts */ 919 __IM uint32_t RESERVED28[30]; 920 __IOM uint32_t NVIC_IABR0; /*!< For each group of 32 interrupts, shows the active state of each 921 interrupt */ 922 __IOM uint32_t NVIC_IABR1; /*!< For each group of 32 interrupts, shows the active state of each 923 interrupt */ 924 __IM uint32_t RESERVED29[30]; 925 __IOM uint32_t NVIC_ITNS0; /*!< For each group of 32 interrupts, determines whether each interrupt 926 targets Non-secure or Secure state */ 927 __IOM uint32_t NVIC_ITNS1; /*!< For each group of 32 interrupts, determines whether each interrupt 928 targets Non-secure or Secure state */ 929 __IM uint32_t RESERVED30[30]; 930 __IOM uint32_t NVIC_IPR0; /*!< Sets or reads interrupt priorities */ 931 __IOM uint32_t NVIC_IPR1; /*!< Sets or reads interrupt priorities */ 932 __IOM uint32_t NVIC_IPR2; /*!< Sets or reads interrupt priorities */ 933 __IOM uint32_t NVIC_IPR3; /*!< Sets or reads interrupt priorities */ 934 __IOM uint32_t NVIC_IPR4; /*!< Sets or reads interrupt priorities */ 935 __IOM uint32_t NVIC_IPR5; /*!< Sets or reads interrupt priorities */ 936 __IOM uint32_t NVIC_IPR6; /*!< Sets or reads interrupt priorities */ 937 __IOM uint32_t NVIC_IPR7; /*!< Sets or reads interrupt priorities */ 938 __IOM uint32_t NVIC_IPR8; /*!< Sets or reads interrupt priorities */ 939 __IOM uint32_t NVIC_IPR9; /*!< Sets or reads interrupt priorities */ 940 __IOM uint32_t NVIC_IPR10; /*!< Sets or reads interrupt priorities */ 941 __IOM uint32_t NVIC_IPR11; /*!< Sets or reads interrupt priorities */ 942 __IOM uint32_t NVIC_IPR12; /*!< Sets or reads interrupt priorities */ 943 __IOM uint32_t NVIC_IPR13; /*!< Sets or reads interrupt priorities */ 944 __IOM uint32_t NVIC_IPR14; /*!< Sets or reads interrupt priorities */ 945 __IOM uint32_t NVIC_IPR15; /*!< Sets or reads interrupt priorities */ 946 __IM uint32_t RESERVED31[560]; 947 __IOM uint32_t CPUID; /*!< Provides identification information for the PE, including an 948 implementer code for the device and a device ID number */ 949 __IOM uint32_t ICSR; /*!< Controls and provides status information for NMI, PendSV, SysTick 950 and interrupts */ 951 __IOM uint32_t VTOR; /*!< The VTOR indicates the offset of the vector table base address 952 from memory address 0x00000000. */ 953 __IOM uint32_t AIRCR; /*!< Use the Application Interrupt and Reset Control Register to: 954 determine data endianness, clear all active state information 955 from debug halt mode, request a system reset. */ 956 __IOM uint32_t SCR; /*!< System Control Register. Use the System Control Register for 957 power-management functions: signal to the system when the 958 processor can enter a low power state, control how the 959 processor enters and exits low power states. */ 960 __IOM uint32_t CCR; /*!< Sets or returns configuration and control data */ 961 __IOM uint32_t SHPR1; /*!< Sets or returns priority for system handlers 4 - 7 */ 962 __IOM uint32_t SHPR2; /*!< Sets or returns priority for system handlers 8 - 11 */ 963 __IOM uint32_t SHPR3; /*!< Sets or returns priority for system handlers 12 - 15 */ 964 __IOM uint32_t SHCSR; /*!< Provides access to the active and pending status of system exceptions */ 965 __IOM uint32_t CFSR; /*!< Contains the three Configurable Fault Status Registers. 31:16 966 UFSR: Provides information on UsageFault exceptions 15:8 967 BFSR: Provides information on BusFault exceptions 7:0 MMFSR: 968 Provides information on MemManage exceptions */ 969 __IOM uint32_t HFSR; /*!< Shows the cause of any HardFaults */ 970 __IOM uint32_t DFSR; /*!< Shows which debug event occurred */ 971 __IOM uint32_t MMFAR; /*!< Shows the address of the memory location that caused an MPU 972 fault */ 973 __IOM uint32_t BFAR; /*!< Shows the address associated with a precise data access BusFault */ 974 __IM uint32_t RESERVED32; 975 __IOM uint32_t ID_PFR0; /*!< Gives top-level information about the instruction set supported 976 by the PE */ 977 __IOM uint32_t ID_PFR1; /*!< Gives information about the programmers' model and Extensions 978 support */ 979 __IOM uint32_t ID_DFR0; /*!< Provides top level information about the debug system */ 980 __IOM uint32_t ID_AFR0; /*!< Provides information about the IMPLEMENTATION DEFINED features 981 of the PE */ 982 __IOM uint32_t ID_MMFR0; /*!< Provides information about the implemented memory model and 983 memory management support */ 984 __IOM uint32_t ID_MMFR1; /*!< Provides information about the implemented memory model and 985 memory management support */ 986 __IOM uint32_t ID_MMFR2; /*!< Provides information about the implemented memory model and 987 memory management support */ 988 __IOM uint32_t ID_MMFR3; /*!< Provides information about the implemented memory model and 989 memory management support */ 990 __IOM uint32_t ID_ISAR0; /*!< Provides information about the instruction set implemented by 991 the PE */ 992 __IOM uint32_t ID_ISAR1; /*!< Provides information about the instruction set implemented by 993 the PE */ 994 __IOM uint32_t ID_ISAR2; /*!< Provides information about the instruction set implemented by 995 the PE */ 996 __IOM uint32_t ID_ISAR3; /*!< Provides information about the instruction set implemented by 997 the PE */ 998 __IOM uint32_t ID_ISAR4; /*!< Provides information about the instruction set implemented by 999 the PE */ 1000 __IOM uint32_t ID_ISAR5; /*!< Provides information about the instruction set implemented by 1001 the PE */ 1002 __IM uint32_t RESERVED33; 1003 __IOM uint32_t CTR; /*!< Provides information about the architecture of the caches. CTR 1004 is RES0 if CLIDR is zero. */ 1005 __IM uint32_t RESERVED34[2]; 1006 __IOM uint32_t CPACR; /*!< Specifies the access privileges for coprocessors and the FP 1007 Extension */ 1008 __IOM uint32_t NSACR; /*!< Defines the Non-secure access permissions for both the FP Extension 1009 and coprocessors CP0 to CP7 */ 1010 __IOM uint32_t MPU_TYPE; /*!< The MPU Type Register indicates how many regions the MPU `FTSSS 1011 supports */ 1012 __IOM uint32_t MPU_CTRL; /*!< Enables the MPU and, when the MPU is enabled, controls whether 1013 the default memory map is enabled as a background region 1014 for privileged accesses, and whether the MPU is enabled 1015 for HardFaults, NMIs, and exception handlers when FAULTMASK 1016 is set to 1 */ 1017 __IOM uint32_t MPU_RNR; /*!< Selects the region currently accessed by MPU_RBAR and MPU_RLAR */ 1018 __IOM uint32_t MPU_RBAR; /*!< Provides indirect read and write access to the base address 1019 of the currently selected MPU region `FTSSS */ 1020 __IOM uint32_t MPU_RLAR; /*!< Provides indirect read and write access to the limit address 1021 of the currently selected MPU region `FTSSS */ 1022 __IOM uint32_t MPU_RBAR_A1; /*!< Provides indirect read and write access to the base address 1023 of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS */ 1024 __IOM uint32_t MPU_RLAR_A1; /*!< Provides indirect read and write access to the limit address 1025 of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) 1026 `FTSSS */ 1027 __IOM uint32_t MPU_RBAR_A2; /*!< Provides indirect read and write access to the base address 1028 of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS */ 1029 __IOM uint32_t MPU_RLAR_A2; /*!< Provides indirect read and write access to the limit address 1030 of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) 1031 `FTSSS */ 1032 __IOM uint32_t MPU_RBAR_A3; /*!< Provides indirect read and write access to the base address 1033 of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS */ 1034 __IOM uint32_t MPU_RLAR_A3; /*!< Provides indirect read and write access to the limit address 1035 of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) 1036 `FTSSS */ 1037 __IM uint32_t RESERVED35; 1038 __IOM uint32_t MPU_MAIR0; /*!< Along with MPU_MAIR1, provides the memory attribute encodings 1039 corresponding to the AttrIndex values */ 1040 __IOM uint32_t MPU_MAIR1; /*!< Along with MPU_MAIR0, provides the memory attribute encodings 1041 corresponding to the AttrIndex values */ 1042 __IM uint32_t RESERVED36[2]; 1043 __IOM uint32_t SAU_CTRL; /*!< Allows enabling of the Security Attribution Unit */ 1044 __IOM uint32_t SAU_TYPE; /*!< Indicates the number of regions implemented by the Security 1045 Attribution Unit */ 1046 __IOM uint32_t SAU_RNR; /*!< Selects the region currently accessed by SAU_RBAR and SAU_RLAR */ 1047 __IOM uint32_t SAU_RBAR; /*!< Provides indirect read and write access to the base address 1048 of the currently selected SAU region */ 1049 __IOM uint32_t SAU_RLAR; /*!< Provides indirect read and write access to the limit address 1050 of the currently selected SAU region */ 1051 __IOM uint32_t SFSR; /*!< Provides information about any security related faults */ 1052 __IOM uint32_t SFAR; /*!< Shows the address of the memory location that caused a Security 1053 violation */ 1054 __IM uint32_t RESERVED37; 1055 __IOM uint32_t DHCSR; /*!< Controls halting debug */ 1056 __IOM uint32_t DCRSR; /*!< With the DCRDR, provides debug access to the general-purpose 1057 registers, special-purpose registers, and the FP extension 1058 registers. A write to the DCRSR specifies the register 1059 to transfer, whether the transfer is a read or write, and 1060 starts the transfer */ 1061 __IOM uint32_t DCRDR; /*!< With the DCRSR, provides debug access to the general-purpose 1062 registers, special-purpose registers, and the FP Extension 1063 registers. If the Main Extension is implemented, it can 1064 also be used for message passing between an external debugger 1065 and a debug agent running on the PE */ 1066 __IOM uint32_t DEMCR; /*!< Manages vector catch behavior and DebugMonitor handling when 1067 debugging */ 1068 __IM uint32_t RESERVED38[2]; 1069 __IOM uint32_t DSCSR; /*!< Provides control and status information for Secure debug */ 1070 __IM uint32_t RESERVED39[61]; 1071 __IOM uint32_t STIR; /*!< Provides a mechanism for software to generate an interrupt */ 1072 __IM uint32_t RESERVED40[12]; 1073 __IOM uint32_t FPCCR; /*!< Holds control data for the Floating-point extension */ 1074 __IOM uint32_t FPCAR; /*!< Holds the location of the unpopulated floating-point register 1075 space allocated on an exception stack frame */ 1076 __IOM uint32_t FPDSCR; /*!< Holds the default values for the floating-point status control 1077 data that the PE assigns to the FPSCR when it creates a 1078 new floating-point context */ 1079 __IOM uint32_t MVFR0; /*!< Describes the features provided by the Floating-point Extension */ 1080 __IOM uint32_t MVFR1; /*!< Describes the features provided by the Floating-point Extension */ 1081 __IOM uint32_t MVFR2; /*!< Describes the features provided by the Floating-point Extension */ 1082 __IM uint32_t RESERVED41[28]; 1083 __IOM uint32_t DDEVARCH; /*!< Provides CoreSight discovery information for the SCS */ 1084 __IM uint32_t RESERVED42[3]; 1085 __IOM uint32_t DDEVTYPE; /*!< Provides CoreSight discovery information for the SCS */ 1086 __IOM uint32_t DPIDR4; /*!< Provides CoreSight discovery information for the SCS */ 1087 __IOM uint32_t DPIDR5; /*!< Provides CoreSight discovery information for the SCS */ 1088 __IOM uint32_t DPIDR6; /*!< Provides CoreSight discovery information for the SCS */ 1089 __IOM uint32_t DPIDR7; /*!< Provides CoreSight discovery information for the SCS */ 1090 __IOM uint32_t DPIDR0; /*!< Provides CoreSight discovery information for the SCS */ 1091 __IOM uint32_t DPIDR1; /*!< Provides CoreSight discovery information for the SCS */ 1092 __IOM uint32_t DPIDR2; /*!< Provides CoreSight discovery information for the SCS */ 1093 __IOM uint32_t DPIDR3; /*!< Provides CoreSight discovery information for the SCS */ 1094 __IOM uint32_t DCIDR0; /*!< Provides CoreSight discovery information for the SCS */ 1095 __IOM uint32_t DCIDR1; /*!< Provides CoreSight discovery information for the SCS */ 1096 __IOM uint32_t DCIDR2; /*!< Provides CoreSight discovery information for the SCS */ 1097 __IOM uint32_t DCIDR3; /*!< Provides CoreSight discovery information for the SCS */ 1098 __IM uint32_t RESERVED43[51201]; 1099 __IOM uint32_t TRCPRGCTLR; /*!< Programming Control Register */ 1100 __IM uint32_t RESERVED44; 1101 __IOM uint32_t TRCSTATR; /*!< The TRCSTATR indicates the ETM-Teal status */ 1102 __IOM uint32_t TRCCONFIGR; /*!< The TRCCONFIGR sets the basic tracing options for the trace 1103 unit */ 1104 __IM uint32_t RESERVED45[3]; 1105 __IOM uint32_t TRCEVENTCTL0R; /*!< The TRCEVENTCTL0R controls the tracing of events in the trace 1106 stream. The events also drive the ETM-Teal external outputs. */ 1107 __IOM uint32_t TRCEVENTCTL1R; /*!< The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R 1108 behave */ 1109 __IM uint32_t RESERVED46; 1110 __IOM uint32_t TRCSTALLCTLR; /*!< The TRCSTALLCTLR enables ETM-Teal to stall the processor if 1111 the ETM-Teal FIFO goes over the programmed level to minimize 1112 risk of overflow */ 1113 __IOM uint32_t TRCTSCTLR; /*!< The TRCTSCTLR controls the insertion of global timestamps into 1114 the trace stream. A timestamp is always inserted into the 1115 instruction trace stream */ 1116 __IOM uint32_t TRCSYNCPR; /*!< The TRCSYNCPR specifies the period of trace synchronization 1117 of the trace streams. TRCSYNCPR defines a number of bytes 1118 of trace between requests for trace synchronization. This 1119 value is always a power of two */ 1120 __IOM uint32_t TRCCCCTLR; /*!< The TRCCCCTLR sets the threshold value for instruction trace 1121 cycle counting. The threshold represents the minimum interval 1122 between cycle count trace packets */ 1123 __IM uint32_t RESERVED47[17]; 1124 __IOM uint32_t TRCVICTLR; /*!< The TRCVICTLR controls instruction trace filtering */ 1125 __IM uint32_t RESERVED48[47]; 1126 __IOM uint32_t TRCCNTRLDVR0; /*!< The TRCCNTRLDVR defines the reload value for the reduced function 1127 counter */ 1128 __IM uint32_t RESERVED49[15]; 1129 __IOM uint32_t TRCIDR8; /*!< TRCIDR8 */ 1130 __IOM uint32_t TRCIDR9; /*!< TRCIDR9 */ 1131 __IOM uint32_t TRCIDR10; /*!< TRCIDR10 */ 1132 __IOM uint32_t TRCIDR11; /*!< TRCIDR11 */ 1133 __IOM uint32_t TRCIDR12; /*!< TRCIDR12 */ 1134 __IOM uint32_t TRCIDR13; /*!< TRCIDR13 */ 1135 __IM uint32_t RESERVED50[10]; 1136 __IOM uint32_t TRCIMSPEC; /*!< The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC 1137 features, and enables any features that are provided */ 1138 __IM uint32_t RESERVED51[7]; 1139 __IOM uint32_t TRCIDR0; /*!< TRCIDR0 */ 1140 __IOM uint32_t TRCIDR1; /*!< TRCIDR1 */ 1141 __IOM uint32_t TRCIDR2; /*!< TRCIDR2 */ 1142 __IOM uint32_t TRCIDR3; /*!< TRCIDR3 */ 1143 __IOM uint32_t TRCIDR4; /*!< TRCIDR4 */ 1144 __IOM uint32_t TRCIDR5; /*!< TRCIDR5 */ 1145 __IOM uint32_t TRCIDR6; /*!< TRCIDR6 */ 1146 __IOM uint32_t TRCIDR7; /*!< TRCIDR7 */ 1147 __IM uint32_t RESERVED52[2]; 1148 __IOM uint32_t TRCRSCTLR2; /*!< The TRCRSCTLR controls the trace resources */ 1149 __IOM uint32_t TRCRSCTLR3; /*!< The TRCRSCTLR controls the trace resources */ 1150 __IM uint32_t RESERVED53[36]; 1151 __IOM uint32_t TRCSSCSR; /*!< Controls the corresponding single-shot comparator resource */ 1152 __IM uint32_t RESERVED54[7]; 1153 __IOM uint32_t TRCSSPCICR; /*!< Selects the PE comparator inputs for Single-shot control */ 1154 __IM uint32_t RESERVED55[19]; 1155 __IOM uint32_t TRCPDCR; /*!< Requests the system to provide power to the trace unit */ 1156 __IOM uint32_t TRCPDSR; /*!< Returns the following information about the trace unit: - OS 1157 Lock status. - Core power domain status. - Power interruption 1158 status */ 1159 __IM uint32_t RESERVED56[755]; 1160 __IOM uint32_t TRCITATBIDR; /*!< Trace Integration ATB Identification Register */ 1161 __IM uint32_t RESERVED57[3]; 1162 __IOM uint32_t TRCITIATBINR; /*!< Trace Integration Instruction ATB In Register */ 1163 __IM uint32_t RESERVED58; 1164 __IOM uint32_t TRCITIATBOUTR; /*!< Trace Integration Instruction ATB Out Register */ 1165 __IM uint32_t RESERVED59[40]; 1166 __IOM uint32_t TRCCLAIMSET; /*!< Claim Tag Set Register */ 1167 __IOM uint32_t TRCCLAIMCLR; /*!< Claim Tag Clear Register */ 1168 __IM uint32_t RESERVED60[4]; 1169 __IOM uint32_t TRCAUTHSTATUS; /*!< Returns the level of tracing that the trace unit can support */ 1170 __IOM uint32_t TRCDEVARCH; /*!< TRCDEVARCH */ 1171 __IM uint32_t RESERVED61[2]; 1172 __IOM uint32_t TRCDEVID; /*!< TRCDEVID */ 1173 __IOM uint32_t TRCDEVTYPE; /*!< TRCDEVTYPE */ 1174 __IOM uint32_t TRCPIDR4; /*!< TRCPIDR4 */ 1175 __IOM uint32_t TRCPIDR5; /*!< TRCPIDR5 */ 1176 __IOM uint32_t TRCPIDR6; /*!< TRCPIDR6 */ 1177 __IOM uint32_t TRCPIDR7; /*!< TRCPIDR7 */ 1178 __IOM uint32_t TRCPIDR0; /*!< TRCPIDR0 */ 1179 __IOM uint32_t TRCPIDR1; /*!< TRCPIDR1 */ 1180 __IOM uint32_t TRCPIDR2; /*!< TRCPIDR2 */ 1181 __IOM uint32_t TRCPIDR3; /*!< TRCPIDR3 */ 1182 __IOM uint32_t TRCCIDR0; /*!< TRCCIDR0 */ 1183 __IOM uint32_t TRCCIDR1; /*!< TRCCIDR1 */ 1184 __IOM uint32_t TRCCIDR2; /*!< TRCCIDR2 */ 1185 __IOM uint32_t TRCCIDR3; /*!< TRCCIDR3 */ 1186 __IOM uint32_t CTICONTROL; /*!< CTI Control Register */ 1187 __IM uint32_t RESERVED62[3]; 1188 __IOM uint32_t CTIINTACK; /*!< CTI Interrupt Acknowledge Register */ 1189 __IOM uint32_t CTIAPPSET; /*!< CTI Application Trigger Set Register */ 1190 __IOM uint32_t CTIAPPCLEAR; /*!< CTI Application Trigger Clear Register */ 1191 __IOM uint32_t CTIAPPPULSE; /*!< CTI Application Pulse Register */ 1192 __IOM uint32_t CTIINEN0; /*!< CTI Trigger to Channel Enable Registers */ 1193 __IOM uint32_t CTIINEN1; /*!< CTI Trigger to Channel Enable Registers */ 1194 __IOM uint32_t CTIINEN2; /*!< CTI Trigger to Channel Enable Registers */ 1195 __IOM uint32_t CTIINEN3; /*!< CTI Trigger to Channel Enable Registers */ 1196 __IOM uint32_t CTIINEN4; /*!< CTI Trigger to Channel Enable Registers */ 1197 __IOM uint32_t CTIINEN5; /*!< CTI Trigger to Channel Enable Registers */ 1198 __IOM uint32_t CTIINEN6; /*!< CTI Trigger to Channel Enable Registers */ 1199 __IOM uint32_t CTIINEN7; /*!< CTI Trigger to Channel Enable Registers */ 1200 __IM uint32_t RESERVED63[24]; 1201 __IOM uint32_t CTIOUTEN0; /*!< CTI Trigger to Channel Enable Registers */ 1202 __IOM uint32_t CTIOUTEN1; /*!< CTI Trigger to Channel Enable Registers */ 1203 __IOM uint32_t CTIOUTEN2; /*!< CTI Trigger to Channel Enable Registers */ 1204 __IOM uint32_t CTIOUTEN3; /*!< CTI Trigger to Channel Enable Registers */ 1205 __IOM uint32_t CTIOUTEN4; /*!< CTI Trigger to Channel Enable Registers */ 1206 __IOM uint32_t CTIOUTEN5; /*!< CTI Trigger to Channel Enable Registers */ 1207 __IOM uint32_t CTIOUTEN6; /*!< CTI Trigger to Channel Enable Registers */ 1208 __IOM uint32_t CTIOUTEN7; /*!< CTI Trigger to Channel Enable Registers */ 1209 __IM uint32_t RESERVED64[28]; 1210 __IOM uint32_t CTITRIGINSTATUS; /*!< CTI Trigger to Channel Enable Registers */ 1211 __IOM uint32_t CTITRIGOUTSTATUS; /*!< CTI Trigger In Status Register */ 1212 __IOM uint32_t CTICHINSTATUS; /*!< CTI Channel In Status Register */ 1213 __IM uint32_t RESERVED65; 1214 __IOM uint32_t CTIGATE; /*!< Enable CTI Channel Gate register */ 1215 __IOM uint32_t ASICCTL; /*!< External Multiplexer Control register */ 1216 __IM uint32_t RESERVED66[871]; 1217 __IOM uint32_t ITCHOUT; /*!< Integration Test Channel Output register */ 1218 __IOM uint32_t ITTRIGOUT; /*!< Integration Test Trigger Output register */ 1219 __IM uint32_t RESERVED67[2]; 1220 __IOM uint32_t ITCHIN; /*!< Integration Test Channel Input register */ 1221 __IM uint32_t RESERVED68[2]; 1222 __IOM uint32_t ITCTRL; /*!< Integration Mode Control register */ 1223 __IM uint32_t RESERVED69[46]; 1224 __IOM uint32_t DEVARCH; /*!< Device Architecture register */ 1225 __IM uint32_t RESERVED70[2]; 1226 __IOM uint32_t DEVID; /*!< Device Configuration register */ 1227 __IOM uint32_t DEVTYPE; /*!< Device Type Identifier register */ 1228 __IOM uint32_t PIDR4; /*!< CoreSight Peripheral ID4 */ 1229 __IOM uint32_t PIDR5; /*!< CoreSight Peripheral ID5 */ 1230 __IOM uint32_t PIDR6; /*!< CoreSight Peripheral ID6 */ 1231 __IOM uint32_t PIDR7; /*!< CoreSight Peripheral ID7 */ 1232 __IOM uint32_t PIDR0; /*!< CoreSight Peripheral ID0 */ 1233 __IOM uint32_t PIDR1; /*!< CoreSight Peripheral ID1 */ 1234 __IOM uint32_t PIDR2; /*!< CoreSight Peripheral ID2 */ 1235 __IOM uint32_t PIDR3; /*!< CoreSight Peripheral ID3 */ 1236 __IOM uint32_t CIDR0; /*!< CoreSight Component ID0 */ 1237 __IOM uint32_t CIDR1; /*!< CoreSight Component ID1 */ 1238 __IOM uint32_t CIDR2; /*!< CoreSight Component ID2 */ 1239 __IOM uint32_t CIDR3; /*!< CoreSight Component ID3 */ 1240 } PPB_Type; /*!< Size = 274432 (0x43000) */ 1241 1242 1243 1244 /* =========================================================================================================================== */ 1245 /* ================ QMI ================ */ 1246 /* =========================================================================================================================== */ 1247 1248 1249 /** 1250 * @brief QSPI Memory Interface. 1251 1252 Provides a memory-mapped interface to up to two SPI/DSPI/QSPI flash or PSRAM devices. Also provides a serial interface for programming and configuration of the external device. (QMI) 1253 */ 1254 1255 typedef struct { /*!< QMI Structure */ 1256 __IOM uint32_t DIRECT_CSR; /*!< Control and status for direct serial mode Direct serial mode 1257 allows the processor to send and receive raw serial frames, 1258 for programming, configuration and control of the external 1259 memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported. */ 1260 __IOM uint32_t DIRECT_TX; /*!< Transmit FIFO for direct mode */ 1261 __IOM uint32_t DIRECT_RX; /*!< Receive FIFO for direct mode */ 1262 __IOM uint32_t M0_TIMING; /*!< Timing configuration register for memory address window 0. */ 1263 __IOM uint32_t M0_RFMT; /*!< Read transfer format configuration for memory address window 1264 0. Configure the bus width of each transfer phase individually, 1265 and configure the length or presence of the command prefix, 1266 command suffix and dummy/turnaround transfer phases. Only 1267 24-bit addresses are supported. The reset value of the 1268 M0_RFMT register is configured to support a basic 03h serial 1269 read transfer with no additional configuration. */ 1270 __IOM uint32_t M0_RCMD; /*!< Command constants used for reads from memory address window 1271 0. The reset value of the M0_RCMD register is configured 1272 to support a basic 03h serial read transfer with no additional 1273 configuration. */ 1274 __IOM uint32_t M0_WFMT; /*!< Write transfer format configuration for memory address window 1275 0. Configure the bus width of each transfer phase individually, 1276 and configure the length or presence of the command prefix, 1277 command suffix and dummy/turnaround transfer phases. Only 1278 24-bit addresses are supported. The reset value of the 1279 M0_WFMT register is configured to support a basic 02h serial 1280 write transfer. However, writes to this window must first 1281 be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory 1282 is read-only by default. */ 1283 __IOM uint32_t M0_WCMD; /*!< Command constants used for writes to memory address window 0. 1284 The reset value of the M0_WCMD register is configured to 1285 support a basic 02h serial write transfer with no additional 1286 configuration. */ 1287 __IOM uint32_t M1_TIMING; /*!< Timing configuration register for memory address window 1. */ 1288 __IOM uint32_t M1_RFMT; /*!< Read transfer format configuration for memory address window 1289 1. Configure the bus width of each transfer phase individually, 1290 and configure the length or presence of the command prefix, 1291 command suffix and dummy/turnaround transfer phases. Only 1292 24-bit addresses are supported. The reset value of the 1293 M1_RFMT register is configured to support a basic 03h serial 1294 read transfer with no additional configuration. */ 1295 __IOM uint32_t M1_RCMD; /*!< Command constants used for reads from memory address window 1296 1. The reset value of the M1_RCMD register is configured 1297 to support a basic 03h serial read transfer with no additional 1298 configuration. */ 1299 __IOM uint32_t M1_WFMT; /*!< Write transfer format configuration for memory address window 1300 1. Configure the bus width of each transfer phase individually, 1301 and configure the length or presence of the command prefix, 1302 command suffix and dummy/turnaround transfer phases. Only 1303 24-bit addresses are supported. The reset value of the 1304 M1_WFMT register is configured to support a basic 02h serial 1305 write transfer. However, writes to this window must first 1306 be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory 1307 is read-only by default. */ 1308 __IOM uint32_t M1_WCMD; /*!< Command constants used for writes to memory address window 1. 1309 The reset value of the M1_WCMD register is configured to 1310 support a basic 02h serial write transfer with no additional 1311 configuration. */ 1312 __IOM uint32_t ATRANS0; /*!< Configure address translation for XIP virtual addresses 0x000000 1313 through 0x3fffff (a 4 MiB window starting at +0 MiB). Address 1314 translation allows a program image to be executed in place 1315 at multiple physical flash addresses (for example, a double-buffered 1316 flash image for over-the-air updates), without the overhead 1317 of position-independent code. At reset, the address translation 1318 registers are initialised to an identity mapping, so that 1319 they can be ignored if address translation is not required. 1320 Note that the XIP cache is fully virtually addressed, so 1321 a cache flush is required after changing the address translation. */ 1322 __IOM uint32_t ATRANS1; /*!< Configure address translation for XIP virtual addresses 0x400000 1323 through 0x7fffff (a 4 MiB window starting at +4 MiB). Address 1324 translation allows a program image to be executed in place 1325 at multiple physical flash addresses (for example, a double-buffered 1326 flash image for over-the-air updates), without the overhead 1327 of position-independent code. At reset, the address translation 1328 registers are initialised to an identity mapping, so that 1329 they can be ignored if address translation is not required. 1330 Note that the XIP cache is fully virtually addressed, so 1331 a cache flush is required after changing the address translation. */ 1332 __IOM uint32_t ATRANS2; /*!< Configure address translation for XIP virtual addresses 0x800000 1333 through 0xbfffff (a 4 MiB window starting at +8 MiB). Address 1334 translation allows a program image to be executed in place 1335 at multiple physical flash addresses (for example, a double-buffered 1336 flash image for over-the-air updates), without the overhead 1337 of position-independent code. At reset, the address translation 1338 registers are initialised to an identity mapping, so that 1339 they can be ignored if address translation is not required. 1340 Note that the XIP cache is fully virtually addressed, so 1341 a cache flush is required after changing the address translation. */ 1342 __IOM uint32_t ATRANS3; /*!< Configure address translation for XIP virtual addresses 0xc00000 1343 through 0xffffff (a 4 MiB window starting at +12 MiB). 1344 Address translation allows a program image to be executed 1345 in place at multiple physical flash addresses (for example, 1346 a double-buffered flash image for over-the-air updates), 1347 without the overhead of position-independent code. At reset, 1348 the address translation registers are initialised to an 1349 identity mapping, so that they can be ignored if address 1350 translation is not required. Note that the XIP cache is 1351 fully virtually addressed, so a cache flush is required 1352 after changing the address translation. */ 1353 __IOM uint32_t ATRANS4; /*!< Configure address translation for XIP virtual addresses 0x1000000 1354 through 0x13fffff (a 4 MiB window starting at +16 MiB). 1355 Address translation allows a program image to be executed 1356 in place at multiple physical flash addresses (for example, 1357 a double-buffered flash image for over-the-air updates), 1358 without the overhead of position-independent code. At reset, 1359 the address translation registers are initialised to an 1360 identity mapping, so that they can be ignored if address 1361 translation is not required. Note that the XIP cache is 1362 fully virtually addressed, so a cache flush is required 1363 after changing the address translation. */ 1364 __IOM uint32_t ATRANS5; /*!< Configure address translation for XIP virtual addresses 0x1400000 1365 through 0x17fffff (a 4 MiB window starting at +20 MiB). 1366 Address translation allows a program image to be executed 1367 in place at multiple physical flash addresses (for example, 1368 a double-buffered flash image for over-the-air updates), 1369 without the overhead of position-independent code. At reset, 1370 the address translation registers are initialised to an 1371 identity mapping, so that they can be ignored if address 1372 translation is not required. Note that the XIP cache is 1373 fully virtually addressed, so a cache flush is required 1374 after changing the address translation. */ 1375 __IOM uint32_t ATRANS6; /*!< Configure address translation for XIP virtual addresses 0x1800000 1376 through 0x1bfffff (a 4 MiB window starting at +24 MiB). 1377 Address translation allows a program image to be executed 1378 in place at multiple physical flash addresses (for example, 1379 a double-buffered flash image for over-the-air updates), 1380 without the overhead of position-independent code. At reset, 1381 the address translation registers are initialised to an 1382 identity mapping, so that they can be ignored if address 1383 translation is not required. Note that the XIP cache is 1384 fully virtually addressed, so a cache flush is required 1385 after changing the address translation. */ 1386 __IOM uint32_t ATRANS7; /*!< Configure address translation for XIP virtual addresses 0x1c00000 1387 through 0x1ffffff (a 4 MiB window starting at +28 MiB). 1388 Address translation allows a program image to be executed 1389 in place at multiple physical flash addresses (for example, 1390 a double-buffered flash image for over-the-air updates), 1391 without the overhead of position-independent code. At reset, 1392 the address translation registers are initialised to an 1393 identity mapping, so that they can be ignored if address 1394 translation is not required. Note that the XIP cache is 1395 fully virtually addressed, so a cache flush is required 1396 after changing the address translation. */ 1397 } QMI_Type; /*!< Size = 84 (0x54) */ 1398 1399 1400 1401 /* =========================================================================================================================== */ 1402 /* ================ XIP_CTRL ================ */ 1403 /* =========================================================================================================================== */ 1404 1405 1406 /** 1407 * @brief QSPI flash execute-in-place block (XIP_CTRL) 1408 */ 1409 1410 typedef struct { /*!< XIP_CTRL Structure */ 1411 __IOM uint32_t CTRL; /*!< Cache control register. Read-only from a Non-secure context. */ 1412 __IM uint32_t RESERVED; 1413 __IOM uint32_t STAT; /*!< STAT */ 1414 __IOM uint32_t CTR_HIT; /*!< Cache Hit counter */ 1415 __IOM uint32_t CTR_ACC; /*!< Cache Access counter */ 1416 __IOM uint32_t STREAM_ADDR; /*!< FIFO stream address */ 1417 __IOM uint32_t STREAM_CTR; /*!< FIFO stream control */ 1418 __IOM uint32_t STREAM_FIFO; /*!< FIFO stream data */ 1419 } XIP_CTRL_Type; /*!< Size = 32 (0x20) */ 1420 1421 1422 1423 /* =========================================================================================================================== */ 1424 /* ================ XIP_AUX ================ */ 1425 /* =========================================================================================================================== */ 1426 1427 1428 /** 1429 * @brief Auxiliary DMA access to XIP FIFOs, via fast AHB bus access (XIP_AUX) 1430 */ 1431 1432 typedef struct { /*!< XIP_AUX Structure */ 1433 __IOM uint32_t STREAM; /*!< Read the XIP stream FIFO (fast bus access to XIP_CTRL_STREAM_FIFO) */ 1434 __IOM uint32_t QMI_DIRECT_TX; /*!< Write to the QMI direct-mode TX FIFO (fast bus access to QMI_DIRECT_TX) */ 1435 __IOM uint32_t QMI_DIRECT_RX; /*!< Read from the QMI direct-mode RX FIFO (fast bus access to QMI_DIRECT_RX) */ 1436 } XIP_AUX_Type; /*!< Size = 12 (0xc) */ 1437 1438 1439 1440 /* =========================================================================================================================== */ 1441 /* ================ SYSCFG ================ */ 1442 /* =========================================================================================================================== */ 1443 1444 1445 /** 1446 * @brief Register block for various chip control signals (SYSCFG) 1447 */ 1448 1449 typedef struct { /*!< SYSCFG Structure */ 1450 __IOM uint32_t PROC_CONFIG; /*!< Configuration for processors */ 1451 __IOM uint32_t PROC_IN_SYNC_BYPASS; /*!< For each bit, if 1, bypass the input synchronizer between that 1452 GPIO and the GPIO input register in the SIO. The input 1453 synchronizers should generally be unbypassed, to avoid 1454 injecting metastabilities into processors. If you're feeling 1455 brave, you can bypass to save two cycles of input latency. 1456 This register applies to GPIO 0...31. */ 1457 __IOM uint32_t PROC_IN_SYNC_BYPASS_HI; /*!< For each bit, if 1, bypass the input synchronizer between that 1458 GPIO and the GPIO input register in the SIO. The input 1459 synchronizers should generally be unbypassed, to avoid 1460 injecting metastabilities into processors. If you're feeling 1461 brave, you can bypass to save two cycles of input latency. 1462 This register applies to GPIO 32...47. USB GPIO 56..57 1463 QSPI GPIO 58..63 */ 1464 __IOM uint32_t DBGFORCE; /*!< Directly control the chip SWD debug port */ 1465 __IOM uint32_t MEMPOWERDOWN; /*!< Control PD pins to memories. Set high to put memories to a low 1466 power state. In this state the memories will retain contents 1467 but not be accessible Use with caution */ 1468 __IOM uint32_t AUXCTRL; /*!< Auxiliary system control register */ 1469 } SYSCFG_Type; /*!< Size = 24 (0x18) */ 1470 1471 1472 1473 /* =========================================================================================================================== */ 1474 /* ================ XOSC ================ */ 1475 /* =========================================================================================================================== */ 1476 1477 1478 /** 1479 * @brief Controls the crystal oscillator (XOSC) 1480 */ 1481 1482 typedef struct { /*!< XOSC Structure */ 1483 __IOM uint32_t CTRL; /*!< Crystal Oscillator Control */ 1484 __IOM uint32_t STATUS; /*!< Crystal Oscillator Status */ 1485 __IOM uint32_t DORMANT; /*!< Crystal Oscillator pause control */ 1486 __IOM uint32_t STARTUP; /*!< Controls the startup delay */ 1487 __IOM uint32_t COUNT; /*!< A down counter running at the xosc frequency which counts to 1488 zero and stops. Can be used for short software pauses when 1489 setting up time sensitive hardware. To start the counter, 1490 write a non-zero value. Reads will return 1 while the count 1491 is running and 0 when it has finished. Minimum count value 1492 is 4. Count values <4 will be treated as count value =4. 1493 Note that synchronisation to the register clock domain 1494 costs 2 register clock cycles and the counter cannot compensate 1495 for that. */ 1496 } XOSC_Type; /*!< Size = 20 (0x14) */ 1497 1498 1499 1500 /* =========================================================================================================================== */ 1501 /* ================ PLL_SYS ================ */ 1502 /* =========================================================================================================================== */ 1503 1504 1505 /** 1506 * @brief PLL_SYS (PLL_SYS) 1507 */ 1508 1509 typedef struct { /*!< PLL_SYS Structure */ 1510 __IOM uint32_t CS; /*!< Control and Status GENERAL CONSTRAINTS: Reference clock frequency 1511 min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO 1512 frequency min=750MHz, max=1600MHz */ 1513 __IOM uint32_t PWR; /*!< Controls the PLL power modes. */ 1514 __IOM uint32_t FBDIV_INT; /*!< Feedback divisor (note: this PLL does not support fractional 1515 division) */ 1516 __IOM uint32_t PRIM; /*!< Controls the PLL post dividers for the primary output (note: 1517 this PLL does not have a secondary output) the primary 1518 output is driven from VCO divided by postdiv1*postdiv2 */ 1519 __IOM uint32_t INTR; /*!< Raw Interrupts */ 1520 __IOM uint32_t INTE; /*!< Interrupt Enable */ 1521 __IOM uint32_t INTF; /*!< Interrupt Force */ 1522 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 1523 } PLL_SYS_Type; /*!< Size = 32 (0x20) */ 1524 1525 1526 1527 /* =========================================================================================================================== */ 1528 /* ================ ACCESSCTRL ================ */ 1529 /* =========================================================================================================================== */ 1530 1531 1532 /** 1533 * @brief Hardware access control registers (ACCESSCTRL) 1534 */ 1535 1536 typedef struct { /*!< ACCESSCTRL Structure */ 1537 __IOM uint32_t LOCK; /*!< Once a LOCK bit is written to 1, ACCESSCTRL silently ignores 1538 writes from that master. LOCK is writable only by a Secure, 1539 Privileged processor or debugger. LOCK bits are only writable 1540 when their value is zero. Once set, they can never be cleared, 1541 except by a full reset of ACCESSCTRL Setting the LOCK bit 1542 does not affect whether an access raises a bus error. Unprivileged 1543 writes, or writes from the DMA, will continue to raise 1544 bus errors. All other accesses will continue not to. */ 1545 __IOM uint32_t FORCE_CORE_NS; /*!< Force core 1's bus accesses to always be Non-secure, no matter 1546 the core's internal state. Useful for schemes where one 1547 core is designated as the Non-secure core, since some peripherals 1548 may filter individual registers internally based on security 1549 state but not on master ID. */ 1550 __IOM uint32_t CFGRESET; /*!< Write 1 to reset all ACCESSCTRL configuration, except for the 1551 LOCK and FORCE_CORE_NS registers. This bit is used in the 1552 RP2350 bootrom to quickly restore ACCESSCTRL to a known 1553 state during the boot path. Note that, like all registers 1554 in ACCESSCTRL, this register is not writable when the writer's 1555 corresponding LOCK bit is set, therefore a master which 1556 has been locked out of ACCESSCTRL can not use the CFGRESET 1557 register to disturb its contents. */ 1558 __IOM uint32_t GPIO_NSMASK0; /*!< Control whether GPIO0...31 are accessible to Non-secure code. 1559 Writable only by a Secure, Privileged processor or debugger. 1560 0 -> Secure access only 1 -> Secure + Non-secure access */ 1561 __IOM uint32_t GPIO_NSMASK1; /*!< Control whether GPIO32..47 are accessible to Non-secure code, 1562 and whether QSPI and USB bitbang are accessible through 1563 the Non-secure SIO. Writable only by a Secure, Privileged 1564 processor or debugger. */ 1565 __IOM uint32_t ROM; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1566 ROM, and at what security/privilege levels they can do 1567 so. Defaults to fully open access. This register is writable 1568 only from a Secure, Privileged processor or debugger, with 1569 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1570 when the NSP bit is set. */ 1571 __IOM uint32_t XIP_MAIN; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1572 XIP_MAIN, and at what security/privilege levels they can 1573 do so. Defaults to fully open access. This register is 1574 writable only from a Secure, Privileged processor or debugger, 1575 with the exception of the NSU bit, which becomes Non-secure-Privileged-wr 1576 table when the NSP bit is set. */ 1577 __IOM uint32_t SRAM0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1578 SRAM0, and at what security/privilege levels they can do 1579 so. Defaults to fully open access. This register is writable 1580 only from a Secure, Privileged processor or debugger, with 1581 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1582 when the NSP bit is set. */ 1583 __IOM uint32_t SRAM1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1584 SRAM1, and at what security/privilege levels they can do 1585 so. Defaults to fully open access. This register is writable 1586 only from a Secure, Privileged processor or debugger, with 1587 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1588 when the NSP bit is set. */ 1589 __IOM uint32_t SRAM2; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1590 SRAM2, and at what security/privilege levels they can do 1591 so. Defaults to fully open access. This register is writable 1592 only from a Secure, Privileged processor or debugger, with 1593 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1594 when the NSP bit is set. */ 1595 __IOM uint32_t SRAM3; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1596 SRAM3, and at what security/privilege levels they can do 1597 so. Defaults to fully open access. This register is writable 1598 only from a Secure, Privileged processor or debugger, with 1599 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1600 when the NSP bit is set. */ 1601 __IOM uint32_t SRAM4; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1602 SRAM4, and at what security/privilege levels they can do 1603 so. Defaults to fully open access. This register is writable 1604 only from a Secure, Privileged processor or debugger, with 1605 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1606 when the NSP bit is set. */ 1607 __IOM uint32_t SRAM5; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1608 SRAM5, and at what security/privilege levels they can do 1609 so. Defaults to fully open access. This register is writable 1610 only from a Secure, Privileged processor or debugger, with 1611 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1612 when the NSP bit is set. */ 1613 __IOM uint32_t SRAM6; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1614 SRAM6, and at what security/privilege levels they can do 1615 so. Defaults to fully open access. This register is writable 1616 only from a Secure, Privileged processor or debugger, with 1617 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1618 when the NSP bit is set. */ 1619 __IOM uint32_t SRAM7; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1620 SRAM7, and at what security/privilege levels they can do 1621 so. Defaults to fully open access. This register is writable 1622 only from a Secure, Privileged processor or debugger, with 1623 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1624 when the NSP bit is set. */ 1625 __IOM uint32_t SRAM8; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1626 SRAM8, and at what security/privilege levels they can do 1627 so. Defaults to fully open access. This register is writable 1628 only from a Secure, Privileged processor or debugger, with 1629 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1630 when the NSP bit is set. */ 1631 __IOM uint32_t SRAM9; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1632 SRAM9, and at what security/privilege levels they can do 1633 so. Defaults to fully open access. This register is writable 1634 only from a Secure, Privileged processor or debugger, with 1635 the exception of the NSU bit, which becomes Non-secure-Privileged-writabl 1636 when the NSP bit is set. */ 1637 __IOM uint32_t DMA; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1638 DMA, and at what security/privilege levels they can do 1639 so. Defaults to Secure access from any master. This register 1640 is writable only from a Secure, Privileged processor or 1641 debugger, with the exception of the NSU bit, which becomes 1642 Non-secure-Privileged-writable when the NSP bit is set. */ 1643 __IOM uint32_t USBCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1644 USBCTRL, and at what security/privilege levels they can 1645 do so. Defaults to Secure access from any master. This 1646 register is writable only from a Secure, Privileged processor 1647 or debugger, with the exception of the NSU bit, which becomes 1648 Non-secure-Privileged-writable when the NSP bit is set. */ 1649 __IOM uint32_t PIO0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1650 PIO0, and at what security/privilege levels they can do 1651 so. Defaults to Secure access from any master. This register 1652 is writable only from a Secure, Privileged processor or 1653 debugger, with the exception of the NSU bit, which becomes 1654 Non-secure-Privileged-writable when the NSP bit is set. */ 1655 __IOM uint32_t PIO1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1656 PIO1, and at what security/privilege levels they can do 1657 so. Defaults to Secure access from any master. This register 1658 is writable only from a Secure, Privileged processor or 1659 debugger, with the exception of the NSU bit, which becomes 1660 Non-secure-Privileged-writable when the NSP bit is set. */ 1661 __IOM uint32_t PIO2; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1662 PIO2, and at what security/privilege levels they can do 1663 so. Defaults to Secure access from any master. This register 1664 is writable only from a Secure, Privileged processor or 1665 debugger, with the exception of the NSU bit, which becomes 1666 Non-secure-Privileged-writable when the NSP bit is set. */ 1667 __IOM uint32_t CORESIGHT_TRACE; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1668 CORESIGHT_TRACE, and at what security/privilege levels 1669 they can do so. Defaults to Secure, Privileged processor 1670 or debug access only. This register is writable only from 1671 a Secure, Privileged processor or debugger, with the exception 1672 of the NSU bit, which becomes Non-secure-Privileged-writable 1673 when the NSP bit is set. */ 1674 __IOM uint32_t CORESIGHT_PERIPH; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1675 CORESIGHT_PERIPH, and at what security/privilege levels 1676 they can do so. Defaults to Secure, Privileged processor 1677 or debug access only. This register is writable only from 1678 a Secure, Privileged processor or debugger, with the exception 1679 of the NSU bit, which becomes Non-secure-Privileged-writable 1680 when the NSP bit is set. */ 1681 __IOM uint32_t SYSINFO; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1682 SYSINFO, and at what security/privilege levels they can 1683 do so. Defaults to fully open access. This register is 1684 writable only from a Secure, Privileged processor or debugger, 1685 with the exception of the NSU bit, which becomes Non-secure-Privileged-wr 1686 table when the NSP bit is set. */ 1687 __IOM uint32_t RESETS; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1688 RESETS, and at what security/privilege levels they can 1689 do so. Defaults to Secure access from any master. This 1690 register is writable only from a Secure, Privileged processor 1691 or debugger, with the exception of the NSU bit, which becomes 1692 Non-secure-Privileged-writable when the NSP bit is set. */ 1693 __IOM uint32_t IO_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1694 IO_BANK0, and at what security/privilege levels they can 1695 do so. Defaults to Secure access from any master. This 1696 register is writable only from a Secure, Privileged processor 1697 or debugger, with the exception of the NSU bit, which becomes 1698 Non-secure-Privileged-writable when the NSP bit is set. */ 1699 __IOM uint32_t IO_BANK1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1700 IO_BANK1, and at what security/privilege levels they can 1701 do so. Defaults to Secure access from any master. This 1702 register is writable only from a Secure, Privileged processor 1703 or debugger, with the exception of the NSU bit, which becomes 1704 Non-secure-Privileged-writable when the NSP bit is set. */ 1705 __IOM uint32_t PADS_BANK0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1706 PADS_BANK0, and at what security/privilege levels they 1707 can do so. Defaults to Secure access from any master. This 1708 register is writable only from a Secure, Privileged processor 1709 or debugger, with the exception of the NSU bit, which becomes 1710 Non-secure-Privileged-writable when the NSP bit is set. */ 1711 __IOM uint32_t PADS_QSPI; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1712 PADS_QSPI, and at what security/privilege levels they can 1713 do so. Defaults to Secure access from any master. This 1714 register is writable only from a Secure, Privileged processor 1715 or debugger, with the exception of the NSU bit, which becomes 1716 Non-secure-Privileged-writable when the NSP bit is set. */ 1717 __IOM uint32_t BUSCTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1718 BUSCTRL, and at what security/privilege levels they can 1719 do so. Defaults to Secure access from any master. This 1720 register is writable only from a Secure, Privileged processor 1721 or debugger, with the exception of the NSU bit, which becomes 1722 Non-secure-Privileged-writable when the NSP bit is set. */ 1723 __IOM uint32_t ADC0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1724 ADC0, and at what security/privilege levels they can do 1725 so. Defaults to Secure access from any master. This register 1726 is writable only from a Secure, Privileged processor or 1727 debugger, with the exception of the NSU bit, which becomes 1728 Non-secure-Privileged-writable when the NSP bit is set. */ 1729 __IOM uint32_t HSTX; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1730 HSTX, and at what security/privilege levels they can do 1731 so. Defaults to Secure access from any master. This register 1732 is writable only from a Secure, Privileged processor or 1733 debugger, with the exception of the NSU bit, which becomes 1734 Non-secure-Privileged-writable when the NSP bit is set. */ 1735 __IOM uint32_t I2C0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1736 I2C0, and at what security/privilege levels they can do 1737 so. Defaults to Secure access from any master. This register 1738 is writable only from a Secure, Privileged processor or 1739 debugger, with the exception of the NSU bit, which becomes 1740 Non-secure-Privileged-writable when the NSP bit is set. */ 1741 __IOM uint32_t I2C1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1742 I2C1, and at what security/privilege levels they can do 1743 so. Defaults to Secure access from any master. This register 1744 is writable only from a Secure, Privileged processor or 1745 debugger, with the exception of the NSU bit, which becomes 1746 Non-secure-Privileged-writable when the NSP bit is set. */ 1747 __IOM uint32_t PWM; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1748 PWM, and at what security/privilege levels they can do 1749 so. Defaults to Secure access from any master. This register 1750 is writable only from a Secure, Privileged processor or 1751 debugger, with the exception of the NSU bit, which becomes 1752 Non-secure-Privileged-writable when the NSP bit is set. */ 1753 __IOM uint32_t SPI0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1754 SPI0, and at what security/privilege levels they can do 1755 so. Defaults to Secure access from any master. This register 1756 is writable only from a Secure, Privileged processor or 1757 debugger, with the exception of the NSU bit, which becomes 1758 Non-secure-Privileged-writable when the NSP bit is set. */ 1759 __IOM uint32_t SPI1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1760 SPI1, and at what security/privilege levels they can do 1761 so. Defaults to Secure access from any master. This register 1762 is writable only from a Secure, Privileged processor or 1763 debugger, with the exception of the NSU bit, which becomes 1764 Non-secure-Privileged-writable when the NSP bit is set. */ 1765 __IOM uint32_t TIMER0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1766 TIMER0, and at what security/privilege levels they can 1767 do so. Defaults to Secure access from any master. This 1768 register is writable only from a Secure, Privileged processor 1769 or debugger, with the exception of the NSU bit, which becomes 1770 Non-secure-Privileged-writable when the NSP bit is set. */ 1771 __IOM uint32_t TIMER1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1772 TIMER1, and at what security/privilege levels they can 1773 do so. Defaults to Secure access from any master. This 1774 register is writable only from a Secure, Privileged processor 1775 or debugger, with the exception of the NSU bit, which becomes 1776 Non-secure-Privileged-writable when the NSP bit is set. */ 1777 __IOM uint32_t UART0; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1778 UART0, and at what security/privilege levels they can do 1779 so. Defaults to Secure access from any master. This register 1780 is writable only from a Secure, Privileged processor or 1781 debugger, with the exception of the NSU bit, which becomes 1782 Non-secure-Privileged-writable when the NSP bit is set. */ 1783 __IOM uint32_t UART1; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1784 UART1, and at what security/privilege levels they can do 1785 so. Defaults to Secure access from any master. This register 1786 is writable only from a Secure, Privileged processor or 1787 debugger, with the exception of the NSU bit, which becomes 1788 Non-secure-Privileged-writable when the NSP bit is set. */ 1789 __IOM uint32_t OTP; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1790 OTP, and at what security/privilege levels they can do 1791 so. Defaults to Secure access from any master. This register 1792 is writable only from a Secure, Privileged processor or 1793 debugger, with the exception of the NSU bit, which becomes 1794 Non-secure-Privileged-writable when the NSP bit is set. */ 1795 __IOM uint32_t TBMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1796 TBMAN, and at what security/privilege levels they can do 1797 so. Defaults to Secure access from any master. This register 1798 is writable only from a Secure, Privileged processor or 1799 debugger, with the exception of the NSU bit, which becomes 1800 Non-secure-Privileged-writable when the NSP bit is set. */ 1801 __IOM uint32_t POWMAN; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1802 POWMAN, and at what security/privilege levels they can 1803 do so. Defaults to Secure, Privileged processor or debug 1804 access only. This register is writable only from a Secure, 1805 Privileged processor or debugger, with the exception of 1806 the NSU bit, which becomes Non-secure-Privileged-writable 1807 when the NSP bit is set. */ 1808 __IOM uint32_t TRNG; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1809 TRNG, and at what security/privilege levels they can do 1810 so. Defaults to Secure, Privileged processor or debug access 1811 only. This register is writable only from a Secure, Privileged 1812 processor or debugger, with the exception of the NSU bit, 1813 which becomes Non-secure-Privileged-writable when the NSP 1814 bit is set. */ 1815 __IOM uint32_t SHA256; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1816 SHA256, and at what security/privilege levels they can 1817 do so. Defaults to Secure, Privileged access only. This 1818 register is writable only from a Secure, Privileged processor 1819 or debugger, with the exception of the NSU bit, which becomes 1820 Non-secure-Privileged-writable when the NSP bit is set. */ 1821 __IOM uint32_t SYSCFG; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1822 SYSCFG, and at what security/privilege levels they can 1823 do so. Defaults to Secure, Privileged processor or debug 1824 access only. This register is writable only from a Secure, 1825 Privileged processor or debugger, with the exception of 1826 the NSU bit, which becomes Non-secure-Privileged-writable 1827 when the NSP bit is set. */ 1828 __IOM uint32_t CLOCKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1829 CLOCKS, and at what security/privilege levels they can 1830 do so. Defaults to Secure, Privileged processor or debug 1831 access only. This register is writable only from a Secure, 1832 Privileged processor or debugger, with the exception of 1833 the NSU bit, which becomes Non-secure-Privileged-writable 1834 when the NSP bit is set. */ 1835 __IOM uint32_t XOSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1836 XOSC, and at what security/privilege levels they can do 1837 so. Defaults to Secure, Privileged processor or debug access 1838 only. This register is writable only from a Secure, Privileged 1839 processor or debugger, with the exception of the NSU bit, 1840 which becomes Non-secure-Privileged-writable when the NSP 1841 bit is set. */ 1842 __IOM uint32_t ROSC; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1843 ROSC, and at what security/privilege levels they can do 1844 so. Defaults to Secure, Privileged processor or debug access 1845 only. This register is writable only from a Secure, Privileged 1846 processor or debugger, with the exception of the NSU bit, 1847 which becomes Non-secure-Privileged-writable when the NSP 1848 bit is set. */ 1849 __IOM uint32_t PLL_SYS; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1850 PLL_SYS, and at what security/privilege levels they can 1851 do so. Defaults to Secure, Privileged processor or debug 1852 access only. This register is writable only from a Secure, 1853 Privileged processor or debugger, with the exception of 1854 the NSU bit, which becomes Non-secure-Privileged-writable 1855 when the NSP bit is set. */ 1856 __IOM uint32_t PLL_USB; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1857 PLL_USB, and at what security/privilege levels they can 1858 do so. Defaults to Secure, Privileged processor or debug 1859 access only. This register is writable only from a Secure, 1860 Privileged processor or debugger, with the exception of 1861 the NSU bit, which becomes Non-secure-Privileged-writable 1862 when the NSP bit is set. */ 1863 __IOM uint32_t TICKS; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1864 TICKS, and at what security/privilege levels they can do 1865 so. Defaults to Secure, Privileged processor or debug access 1866 only. This register is writable only from a Secure, Privileged 1867 processor or debugger, with the exception of the NSU bit, 1868 which becomes Non-secure-Privileged-writable when the NSP 1869 bit is set. */ 1870 __IOM uint32_t WATCHDOG; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1871 WATCHDOG, and at what security/privilege levels they can 1872 do so. Defaults to Secure, Privileged processor or debug 1873 access only. This register is writable only from a Secure, 1874 Privileged processor or debugger, with the exception of 1875 the NSU bit, which becomes Non-secure-Privileged-writable 1876 when the NSP bit is set. */ 1877 __IOM uint32_t RSM; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1878 RSM, and at what security/privilege levels they can do 1879 so. Defaults to Secure, Privileged processor or debug access 1880 only. This register is writable only from a Secure, Privileged 1881 processor or debugger, with the exception of the NSU bit, 1882 which becomes Non-secure-Privileged-writable when the NSP 1883 bit is set. */ 1884 __IOM uint32_t XIP_CTRL; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1885 XIP_CTRL, and at what security/privilege levels they can 1886 do so. Defaults to Secure, Privileged processor or debug 1887 access only. This register is writable only from a Secure, 1888 Privileged processor or debugger, with the exception of 1889 the NSU bit, which becomes Non-secure-Privileged-writable 1890 when the NSP bit is set. */ 1891 __IOM uint32_t XIP_QMI; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1892 XIP_QMI, and at what security/privilege levels they can 1893 do so. Defaults to Secure, Privileged processor or debug 1894 access only. This register is writable only from a Secure, 1895 Privileged processor or debugger, with the exception of 1896 the NSU bit, which becomes Non-secure-Privileged-writable 1897 when the NSP bit is set. */ 1898 __IOM uint32_t XIP_AUX; /*!< Control whether debugger, DMA, core 0 and core 1 can access 1899 XIP_AUX, and at what security/privilege levels they can 1900 do so. Defaults to Secure, Privileged access only. This 1901 register is writable only from a Secure, Privileged processor 1902 or debugger, with the exception of the NSU bit, which becomes 1903 Non-secure-Privileged-writable when the NSP bit is set. */ 1904 } ACCESSCTRL_Type; /*!< Size = 236 (0xec) */ 1905 1906 1907 1908 /* =========================================================================================================================== */ 1909 /* ================ UART0 ================ */ 1910 /* =========================================================================================================================== */ 1911 1912 1913 /** 1914 * @brief UART0 (UART0) 1915 */ 1916 1917 typedef struct { /*!< UART0 Structure */ 1918 __IOM uint32_t UARTDR; /*!< Data Register, UARTDR */ 1919 __IOM uint32_t UARTRSR; /*!< Receive Status Register/Error Clear Register, UARTRSR/UARTECR */ 1920 __IM uint32_t RESERVED[4]; 1921 __IOM uint32_t UARTFR; /*!< Flag Register, UARTFR */ 1922 __IM uint32_t RESERVED1; 1923 __IOM uint32_t UARTILPR; /*!< IrDA Low-Power Counter Register, UARTILPR */ 1924 __IOM uint32_t UARTIBRD; /*!< Integer Baud Rate Register, UARTIBRD */ 1925 __IOM uint32_t UARTFBRD; /*!< Fractional Baud Rate Register, UARTFBRD */ 1926 __IOM uint32_t UARTLCR_H; /*!< Line Control Register, UARTLCR_H */ 1927 __IOM uint32_t UARTCR; /*!< Control Register, UARTCR */ 1928 __IOM uint32_t UARTIFLS; /*!< Interrupt FIFO Level Select Register, UARTIFLS */ 1929 __IOM uint32_t UARTIMSC; /*!< Interrupt Mask Set/Clear Register, UARTIMSC */ 1930 __IOM uint32_t UARTRIS; /*!< Raw Interrupt Status Register, UARTRIS */ 1931 __IOM uint32_t UARTMIS; /*!< Masked Interrupt Status Register, UARTMIS */ 1932 __IOM uint32_t UARTICR; /*!< Interrupt Clear Register, UARTICR */ 1933 __IOM uint32_t UARTDMACR; /*!< DMA Control Register, UARTDMACR */ 1934 __IM uint32_t RESERVED2[997]; 1935 __IOM uint32_t UARTPERIPHID0; /*!< UARTPeriphID0 Register */ 1936 __IOM uint32_t UARTPERIPHID1; /*!< UARTPeriphID1 Register */ 1937 __IOM uint32_t UARTPERIPHID2; /*!< UARTPeriphID2 Register */ 1938 __IOM uint32_t UARTPERIPHID3; /*!< UARTPeriphID3 Register */ 1939 __IOM uint32_t UARTPCELLID0; /*!< UARTPCellID0 Register */ 1940 __IOM uint32_t UARTPCELLID1; /*!< UARTPCellID1 Register */ 1941 __IOM uint32_t UARTPCELLID2; /*!< UARTPCellID2 Register */ 1942 __IOM uint32_t UARTPCELLID3; /*!< UARTPCellID3 Register */ 1943 } UART0_Type; /*!< Size = 4096 (0x1000) */ 1944 1945 1946 1947 /* =========================================================================================================================== */ 1948 /* ================ ROSC ================ */ 1949 /* =========================================================================================================================== */ 1950 1951 1952 /** 1953 * @brief ROSC (ROSC) 1954 */ 1955 1956 typedef struct { /*!< ROSC Structure */ 1957 __IOM uint32_t CTRL; /*!< Ring Oscillator control */ 1958 __IOM uint32_t FREQA; /*!< The FREQA & FREQB registers control the frequency by controlling 1959 the drive strength of each stage The drive strength has 1960 4 levels determined by the number of bits set Increasing 1961 the number of bits set increases the drive strength and 1962 increases the oscillation frequency 0 bits set is the default 1963 drive strength 1 bit set doubles the drive strength 2 bits 1964 set triples drive strength 3 bits set quadruples drive 1965 strength For frequency randomisation set both DS0_RANDOM=1 1966 & DS1_RANDOM=1 */ 1967 __IOM uint32_t FREQB; /*!< For a detailed description see freqa register */ 1968 __IOM uint32_t RANDOM; /*!< Loads a value to the LFSR randomiser */ 1969 __IOM uint32_t DORMANT; /*!< Ring Oscillator pause control */ 1970 __IOM uint32_t DIV; /*!< Controls the output divider */ 1971 __IOM uint32_t PHASE; /*!< Controls the phase shifted output */ 1972 __IOM uint32_t STATUS; /*!< Ring Oscillator Status */ 1973 __IOM uint32_t RANDOMBIT; /*!< This just reads the state of the oscillator output so randomness 1974 is compromised if the ring oscillator is stopped or run 1975 at a harmonic of the bus frequency */ 1976 __IOM uint32_t COUNT; /*!< A down counter running at the ROSC frequency which counts to 1977 zero and stops. To start the counter write a non-zero value. 1978 Can be used for short software pauses when setting up time 1979 sensitive hardware. */ 1980 } ROSC_Type; /*!< Size = 40 (0x28) */ 1981 1982 1983 1984 /* =========================================================================================================================== */ 1985 /* ================ POWMAN ================ */ 1986 /* =========================================================================================================================== */ 1987 1988 1989 /** 1990 * @brief Controls vreg, bor, lposc, chip resets & xosc startup, powman and provides scratch register for general use and for bootcode use (POWMAN) 1991 */ 1992 1993 typedef struct { /*!< POWMAN Structure */ 1994 __IOM uint32_t BADPASSWD; /*!< Indicates a bad password has been used */ 1995 __IOM uint32_t VREG_CTRL; /*!< Voltage Regulator Control */ 1996 __IOM uint32_t VREG_STS; /*!< Voltage Regulator Status */ 1997 __IOM uint32_t VREG; /*!< Voltage Regulator Settings */ 1998 __IOM uint32_t VREG_LP_ENTRY; /*!< Voltage Regulator Low Power Entry Settings */ 1999 __IOM uint32_t VREG_LP_EXIT; /*!< Voltage Regulator Low Power Exit Settings */ 2000 __IOM uint32_t BOD_CTRL; /*!< Brown-out Detection Control */ 2001 __IOM uint32_t BOD; /*!< Brown-out Detection Settings */ 2002 __IOM uint32_t BOD_LP_ENTRY; /*!< Brown-out Detection Low Power Entry Settings */ 2003 __IOM uint32_t BOD_LP_EXIT; /*!< Brown-out Detection Low Power Exit Settings */ 2004 __IOM uint32_t LPOSC; /*!< Low power oscillator control register. */ 2005 __IOM uint32_t CHIP_RESET; /*!< Chip reset control and status */ 2006 __IOM uint32_t WDSEL; /*!< Allows a watchdog reset to reset the internal state of powman 2007 in addition to the power-on state machine (PSM). Note that 2008 powman ignores watchdog resets that do not select at least 2009 the CLOCKS stage or earlier stages in the PSM. If using 2010 these bits, it's recommended to set PSM_WDSEL to all-ones 2011 in addition to the desired bits in this register. Failing 2012 to select CLOCKS or earlier will result in the POWMAN_WDSEL 2013 register having no effect. */ 2014 __IOM uint32_t SEQ_CFG; /*!< For configuration of the power sequencer Writes are ignored 2015 while POWMAN_STATE_CHANGING=1 */ 2016 __IOM uint32_t STATE; /*!< This register controls the power state of the 4 power domains. 2017 The current power state is indicated in POWMAN_STATE_CURRENT 2018 which is read-only. To change the state, write to POWMAN_STATE_REQ. 2019 The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds 2020 to the power states defined in the datasheet: bit 3 = SWCORE 2021 bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered 2022 up 1 = powered down When POWMAN_STATE_REQ is written, the 2023 POWMAN_STATE_WAITING flag is set while the Power Manager 2024 determines what is required. If an invalid transition is 2025 requested the Power Manager will still register the request 2026 in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ 2027 flag. It will then implement the power-up requests and 2028 ignore the power down requests. To do nothing would risk 2029 entering an unrecoverable lock-up state. Invalid requests 2030 are: any combination of power up and power down requests 2031 any request that results in swcore boing powered and xip 2032 unpowered If the request is to power down the switched-core 2033 domain then POWMAN_STATE_WAITING stays active until the 2034 processors halt. During this time the POWMAN_STATE_REQ 2035 field can be re-written to change or cancel the request. 2036 When the power state transition begins the POWMAN_STATE_WAITING_flag 2037 is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN 2038 register writes are ignored until the transition completes. */ 2039 __IOM uint32_t POW_FASTDIV; /*!< POW_FASTDIV */ 2040 __IOM uint32_t POW_DELAY; /*!< power state machine delays */ 2041 __IOM uint32_t EXT_CTRL0; /*!< Configures a gpio as a power mode aware control output */ 2042 __IOM uint32_t EXT_CTRL1; /*!< Configures a gpio as a power mode aware control output */ 2043 __IOM uint32_t EXT_TIME_REF; /*!< Select a GPIO to use as a time reference, the source can be 2044 used to drive the low power clock at 32kHz, or to provide 2045 a 1ms tick to the timer, or provide a 1Hz tick to the timer. 2046 The tick selection is controlled by the POWMAN_TIMER register. */ 2047 __IOM uint32_t LPOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock 2048 frequency when running off the LPOSC. */ 2049 __IOM uint32_t LPOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock 2050 frequency when running off the LPOSC. */ 2051 __IOM uint32_t XOSC_FREQ_KHZ_INT; /*!< Informs the AON Timer of the integer component of the clock 2052 frequency when running off the XOSC. */ 2053 __IOM uint32_t XOSC_FREQ_KHZ_FRAC; /*!< Informs the AON Timer of the fractional component of the clock 2054 frequency when running off the XOSC. */ 2055 __IOM uint32_t SET_TIME_63TO48; /*!< SET_TIME_63TO48 */ 2056 __IOM uint32_t SET_TIME_47TO32; /*!< SET_TIME_47TO32 */ 2057 __IOM uint32_t SET_TIME_31TO16; /*!< SET_TIME_31TO16 */ 2058 __IOM uint32_t SET_TIME_15TO0; /*!< SET_TIME_15TO0 */ 2059 __IOM uint32_t READ_TIME_UPPER; /*!< READ_TIME_UPPER */ 2060 __IOM uint32_t READ_TIME_LOWER; /*!< READ_TIME_LOWER */ 2061 __IOM uint32_t ALARM_TIME_63TO48; /*!< ALARM_TIME_63TO48 */ 2062 __IOM uint32_t ALARM_TIME_47TO32; /*!< ALARM_TIME_47TO32 */ 2063 __IOM uint32_t ALARM_TIME_31TO16; /*!< ALARM_TIME_31TO16 */ 2064 __IOM uint32_t ALARM_TIME_15TO0; /*!< ALARM_TIME_15TO0 */ 2065 __IOM uint32_t TIMER; /*!< TIMER */ 2066 __IOM uint32_t PWRUP0; /*!< 4 GPIO powerup events can be configured to wake the chip up 2067 from a low power state. The pwrups are level/edge sensitive 2068 and can be set to trigger on a high/rising or low/falling 2069 event The number of gpios available depends on the package 2070 option. An invalid selection will be ignored source = 0 2071 selects gpio0 . . source = 47 selects gpio47 source = 48 2072 selects qspi_ss source = 49 selects qspi_sd0 source = 50 2073 selects qspi_sd1 source = 51 selects qspi_sd2 source = 2074 52 selects qspi_sd3 source = 53 selects qspi_sclk level 2075 = 0 triggers the pwrup when the source is low level = 1 2076 triggers the pwrup when the source is high */ 2077 __IOM uint32_t PWRUP1; /*!< 4 GPIO powerup events can be configured to wake the chip up 2078 from a low power state. The pwrups are level/edge sensitive 2079 and can be set to trigger on a high/rising or low/falling 2080 event The number of gpios available depends on the package 2081 option. An invalid selection will be ignored source = 0 2082 selects gpio0 . . source = 47 selects gpio47 source = 48 2083 selects qspi_ss source = 49 selects qspi_sd0 source = 50 2084 selects qspi_sd1 source = 51 selects qspi_sd2 source = 2085 52 selects qspi_sd3 source = 53 selects qspi_sclk level 2086 = 0 triggers the pwrup when the source is low level = 1 2087 triggers the pwrup when the source is high */ 2088 __IOM uint32_t PWRUP2; /*!< 4 GPIO powerup events can be configured to wake the chip up 2089 from a low power state. The pwrups are level/edge sensitive 2090 and can be set to trigger on a high/rising or low/falling 2091 event The number of gpios available depends on the package 2092 option. An invalid selection will be ignored source = 0 2093 selects gpio0 . . source = 47 selects gpio47 source = 48 2094 selects qspi_ss source = 49 selects qspi_sd0 source = 50 2095 selects qspi_sd1 source = 51 selects qspi_sd2 source = 2096 52 selects qspi_sd3 source = 53 selects qspi_sclk level 2097 = 0 triggers the pwrup when the source is low level = 1 2098 triggers the pwrup when the source is high */ 2099 __IOM uint32_t PWRUP3; /*!< 4 GPIO powerup events can be configured to wake the chip up 2100 from a low power state. The pwrups are level/edge sensitive 2101 and can be set to trigger on a high/rising or low/falling 2102 event The number of gpios available depends on the package 2103 option. An invalid selection will be ignored source = 0 2104 selects gpio0 . . source = 47 selects gpio47 source = 48 2105 selects qspi_ss source = 49 selects qspi_sd0 source = 50 2106 selects qspi_sd1 source = 51 selects qspi_sd2 source = 2107 52 selects qspi_sd3 source = 53 selects qspi_sclk level 2108 = 0 triggers the pwrup when the source is low level = 1 2109 triggers the pwrup when the source is high */ 2110 __IOM uint32_t CURRENT_PWRUP_REQ; /*!< Indicates current powerup request state pwrup events can be 2111 cleared by removing the enable from the pwrup register. 2112 The alarm pwrup req can be cleared by clearing timer.alarm_enab 2113 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 2114 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 2115 6 = alarm_pwrup */ 2116 __IOM uint32_t LAST_SWCORE_PWRUP; /*!< Indicates which pwrup source triggered the last switched-core 2117 power up 0 = chip reset, for the source of the last reset 2118 see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 2119 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup */ 2120 __IOM uint32_t DBG_PWRCFG; /*!< DBG_PWRCFG */ 2121 __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore the BOOT0..3 registers following 2122 the next RSM reset (e.g. the next core power down/up). 2123 If an early boot stage has soft-locked some OTP pages in 2124 order to protect their contents from later stages, there 2125 is a risk that Secure code running at a later stage can 2126 unlock the pages by powering the core up and down. This 2127 register can be used to ensure that the bootloader runs 2128 as normal on the next power up, preventing Secure code 2129 at a later stage from accessing OTP in its unlocked state. 2130 Should be used in conjunction with the OTP BOOTDIS register. */ 2131 __IOM uint32_t DBGCONFIG; /*!< DBGCONFIG */ 2132 __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists in low power mode */ 2133 __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists in low power mode */ 2134 __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists in low power mode */ 2135 __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists in low power mode */ 2136 __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists in low power mode */ 2137 __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists in low power mode */ 2138 __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists in low power mode */ 2139 __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists in low power mode */ 2140 __IOM uint32_t BOOT0; /*!< Scratch register. Information persists in low power mode */ 2141 __IOM uint32_t BOOT1; /*!< Scratch register. Information persists in low power mode */ 2142 __IOM uint32_t BOOT2; /*!< Scratch register. Information persists in low power mode */ 2143 __IOM uint32_t BOOT3; /*!< Scratch register. Information persists in low power mode */ 2144 __IOM uint32_t INTR; /*!< Raw Interrupts */ 2145 __IOM uint32_t INTE; /*!< Interrupt Enable */ 2146 __IOM uint32_t INTF; /*!< Interrupt Force */ 2147 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 2148 } POWMAN_Type; /*!< Size = 240 (0xf0) */ 2149 2150 2151 2152 /* =========================================================================================================================== */ 2153 /* ================ WATCHDOG ================ */ 2154 /* =========================================================================================================================== */ 2155 2156 2157 /** 2158 * @brief WATCHDOG (WATCHDOG) 2159 */ 2160 2161 typedef struct { /*!< WATCHDOG Structure */ 2162 __IOM uint32_t CTRL; /*!< Watchdog control The rst_wdsel register determines which subsystems 2163 are reset when the watchdog is triggered. The watchdog 2164 can be triggered in software. */ 2165 __IOM uint32_t LOAD; /*!< Load the watchdog timer. The maximum setting is 0xffffff which 2166 corresponds to approximately 16 seconds. */ 2167 __IOM uint32_t REASON; /*!< Logs the reason for the last reset. Both bits are zero for the 2168 case of a hardware reset. Additionally, as of RP2350, a 2169 debugger warm reset of either core (SYSRESETREQ or hartreset) 2170 will also clear the watchdog reason register, so that software 2171 loaded under the debugger following a watchdog timeout 2172 will not continue to see the timeout condition. */ 2173 __IOM uint32_t SCRATCH0; /*!< Scratch register. Information persists through soft reset of 2174 the chip. */ 2175 __IOM uint32_t SCRATCH1; /*!< Scratch register. Information persists through soft reset of 2176 the chip. */ 2177 __IOM uint32_t SCRATCH2; /*!< Scratch register. Information persists through soft reset of 2178 the chip. */ 2179 __IOM uint32_t SCRATCH3; /*!< Scratch register. Information persists through soft reset of 2180 the chip. */ 2181 __IOM uint32_t SCRATCH4; /*!< Scratch register. Information persists through soft reset of 2182 the chip. */ 2183 __IOM uint32_t SCRATCH5; /*!< Scratch register. Information persists through soft reset of 2184 the chip. */ 2185 __IOM uint32_t SCRATCH6; /*!< Scratch register. Information persists through soft reset of 2186 the chip. */ 2187 __IOM uint32_t SCRATCH7; /*!< Scratch register. Information persists through soft reset of 2188 the chip. */ 2189 } WATCHDOG_Type; /*!< Size = 44 (0x2c) */ 2190 2191 2192 2193 /* =========================================================================================================================== */ 2194 /* ================ DMA ================ */ 2195 /* =========================================================================================================================== */ 2196 2197 2198 /** 2199 * @brief DMA with separate read and write masters (DMA) 2200 */ 2201 2202 typedef struct { /*!< DMA Structure */ 2203 __IOM uint32_t CH0_READ_ADDR; /*!< DMA Channel 0 Read Address pointer */ 2204 __IOM uint32_t CH0_WRITE_ADDR; /*!< DMA Channel 0 Write Address pointer */ 2205 __IOM uint32_t CH0_TRANS_COUNT; /*!< DMA Channel 0 Transfer Count */ 2206 __IOM uint32_t CH0_CTRL_TRIG; /*!< DMA Channel 0 Control and Status */ 2207 __IOM uint32_t CH0_AL1_CTRL; /*!< Alias for channel 0 CTRL register */ 2208 __IOM uint32_t CH0_AL1_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ 2209 __IOM uint32_t CH0_AL1_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ 2210 __IOM uint32_t CH0_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 0 TRANS_COUNT register This is a trigger register 2211 (0xc). Writing a nonzero value will reload the channel 2212 counter and start the channel. */ 2213 __IOM uint32_t CH0_AL2_CTRL; /*!< Alias for channel 0 CTRL register */ 2214 __IOM uint32_t CH0_AL2_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ 2215 __IOM uint32_t CH0_AL2_READ_ADDR; /*!< Alias for channel 0 READ_ADDR register */ 2216 __IOM uint32_t CH0_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 0 WRITE_ADDR register This is a trigger register 2217 (0xc). Writing a nonzero value will reload the channel 2218 counter and start the channel. */ 2219 __IOM uint32_t CH0_AL3_CTRL; /*!< Alias for channel 0 CTRL register */ 2220 __IOM uint32_t CH0_AL3_WRITE_ADDR; /*!< Alias for channel 0 WRITE_ADDR register */ 2221 __IOM uint32_t CH0_AL3_TRANS_COUNT; /*!< Alias for channel 0 TRANS_COUNT register */ 2222 __IOM uint32_t CH0_AL3_READ_ADDR_TRIG; /*!< Alias for channel 0 READ_ADDR register This is a trigger register 2223 (0xc). Writing a nonzero value will reload the channel 2224 counter and start the channel. */ 2225 __IOM uint32_t CH1_READ_ADDR; /*!< DMA Channel 1 Read Address pointer */ 2226 __IOM uint32_t CH1_WRITE_ADDR; /*!< DMA Channel 1 Write Address pointer */ 2227 __IOM uint32_t CH1_TRANS_COUNT; /*!< DMA Channel 1 Transfer Count */ 2228 __IOM uint32_t CH1_CTRL_TRIG; /*!< DMA Channel 1 Control and Status */ 2229 __IOM uint32_t CH1_AL1_CTRL; /*!< Alias for channel 1 CTRL register */ 2230 __IOM uint32_t CH1_AL1_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ 2231 __IOM uint32_t CH1_AL1_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ 2232 __IOM uint32_t CH1_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 1 TRANS_COUNT register This is a trigger register 2233 (0xc). Writing a nonzero value will reload the channel 2234 counter and start the channel. */ 2235 __IOM uint32_t CH1_AL2_CTRL; /*!< Alias for channel 1 CTRL register */ 2236 __IOM uint32_t CH1_AL2_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ 2237 __IOM uint32_t CH1_AL2_READ_ADDR; /*!< Alias for channel 1 READ_ADDR register */ 2238 __IOM uint32_t CH1_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 1 WRITE_ADDR register This is a trigger register 2239 (0xc). Writing a nonzero value will reload the channel 2240 counter and start the channel. */ 2241 __IOM uint32_t CH1_AL3_CTRL; /*!< Alias for channel 1 CTRL register */ 2242 __IOM uint32_t CH1_AL3_WRITE_ADDR; /*!< Alias for channel 1 WRITE_ADDR register */ 2243 __IOM uint32_t CH1_AL3_TRANS_COUNT; /*!< Alias for channel 1 TRANS_COUNT register */ 2244 __IOM uint32_t CH1_AL3_READ_ADDR_TRIG; /*!< Alias for channel 1 READ_ADDR register This is a trigger register 2245 (0xc). Writing a nonzero value will reload the channel 2246 counter and start the channel. */ 2247 __IOM uint32_t CH2_READ_ADDR; /*!< DMA Channel 2 Read Address pointer */ 2248 __IOM uint32_t CH2_WRITE_ADDR; /*!< DMA Channel 2 Write Address pointer */ 2249 __IOM uint32_t CH2_TRANS_COUNT; /*!< DMA Channel 2 Transfer Count */ 2250 __IOM uint32_t CH2_CTRL_TRIG; /*!< DMA Channel 2 Control and Status */ 2251 __IOM uint32_t CH2_AL1_CTRL; /*!< Alias for channel 2 CTRL register */ 2252 __IOM uint32_t CH2_AL1_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ 2253 __IOM uint32_t CH2_AL1_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ 2254 __IOM uint32_t CH2_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 2 TRANS_COUNT register This is a trigger register 2255 (0xc). Writing a nonzero value will reload the channel 2256 counter and start the channel. */ 2257 __IOM uint32_t CH2_AL2_CTRL; /*!< Alias for channel 2 CTRL register */ 2258 __IOM uint32_t CH2_AL2_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ 2259 __IOM uint32_t CH2_AL2_READ_ADDR; /*!< Alias for channel 2 READ_ADDR register */ 2260 __IOM uint32_t CH2_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 2 WRITE_ADDR register This is a trigger register 2261 (0xc). Writing a nonzero value will reload the channel 2262 counter and start the channel. */ 2263 __IOM uint32_t CH2_AL3_CTRL; /*!< Alias for channel 2 CTRL register */ 2264 __IOM uint32_t CH2_AL3_WRITE_ADDR; /*!< Alias for channel 2 WRITE_ADDR register */ 2265 __IOM uint32_t CH2_AL3_TRANS_COUNT; /*!< Alias for channel 2 TRANS_COUNT register */ 2266 __IOM uint32_t CH2_AL3_READ_ADDR_TRIG; /*!< Alias for channel 2 READ_ADDR register This is a trigger register 2267 (0xc). Writing a nonzero value will reload the channel 2268 counter and start the channel. */ 2269 __IOM uint32_t CH3_READ_ADDR; /*!< DMA Channel 3 Read Address pointer */ 2270 __IOM uint32_t CH3_WRITE_ADDR; /*!< DMA Channel 3 Write Address pointer */ 2271 __IOM uint32_t CH3_TRANS_COUNT; /*!< DMA Channel 3 Transfer Count */ 2272 __IOM uint32_t CH3_CTRL_TRIG; /*!< DMA Channel 3 Control and Status */ 2273 __IOM uint32_t CH3_AL1_CTRL; /*!< Alias for channel 3 CTRL register */ 2274 __IOM uint32_t CH3_AL1_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ 2275 __IOM uint32_t CH3_AL1_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ 2276 __IOM uint32_t CH3_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 3 TRANS_COUNT register This is a trigger register 2277 (0xc). Writing a nonzero value will reload the channel 2278 counter and start the channel. */ 2279 __IOM uint32_t CH3_AL2_CTRL; /*!< Alias for channel 3 CTRL register */ 2280 __IOM uint32_t CH3_AL2_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ 2281 __IOM uint32_t CH3_AL2_READ_ADDR; /*!< Alias for channel 3 READ_ADDR register */ 2282 __IOM uint32_t CH3_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 3 WRITE_ADDR register This is a trigger register 2283 (0xc). Writing a nonzero value will reload the channel 2284 counter and start the channel. */ 2285 __IOM uint32_t CH3_AL3_CTRL; /*!< Alias for channel 3 CTRL register */ 2286 __IOM uint32_t CH3_AL3_WRITE_ADDR; /*!< Alias for channel 3 WRITE_ADDR register */ 2287 __IOM uint32_t CH3_AL3_TRANS_COUNT; /*!< Alias for channel 3 TRANS_COUNT register */ 2288 __IOM uint32_t CH3_AL3_READ_ADDR_TRIG; /*!< Alias for channel 3 READ_ADDR register This is a trigger register 2289 (0xc). Writing a nonzero value will reload the channel 2290 counter and start the channel. */ 2291 __IOM uint32_t CH4_READ_ADDR; /*!< DMA Channel 4 Read Address pointer */ 2292 __IOM uint32_t CH4_WRITE_ADDR; /*!< DMA Channel 4 Write Address pointer */ 2293 __IOM uint32_t CH4_TRANS_COUNT; /*!< DMA Channel 4 Transfer Count */ 2294 __IOM uint32_t CH4_CTRL_TRIG; /*!< DMA Channel 4 Control and Status */ 2295 __IOM uint32_t CH4_AL1_CTRL; /*!< Alias for channel 4 CTRL register */ 2296 __IOM uint32_t CH4_AL1_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ 2297 __IOM uint32_t CH4_AL1_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ 2298 __IOM uint32_t CH4_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 4 TRANS_COUNT register This is a trigger register 2299 (0xc). Writing a nonzero value will reload the channel 2300 counter and start the channel. */ 2301 __IOM uint32_t CH4_AL2_CTRL; /*!< Alias for channel 4 CTRL register */ 2302 __IOM uint32_t CH4_AL2_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ 2303 __IOM uint32_t CH4_AL2_READ_ADDR; /*!< Alias for channel 4 READ_ADDR register */ 2304 __IOM uint32_t CH4_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 4 WRITE_ADDR register This is a trigger register 2305 (0xc). Writing a nonzero value will reload the channel 2306 counter and start the channel. */ 2307 __IOM uint32_t CH4_AL3_CTRL; /*!< Alias for channel 4 CTRL register */ 2308 __IOM uint32_t CH4_AL3_WRITE_ADDR; /*!< Alias for channel 4 WRITE_ADDR register */ 2309 __IOM uint32_t CH4_AL3_TRANS_COUNT; /*!< Alias for channel 4 TRANS_COUNT register */ 2310 __IOM uint32_t CH4_AL3_READ_ADDR_TRIG; /*!< Alias for channel 4 READ_ADDR register This is a trigger register 2311 (0xc). Writing a nonzero value will reload the channel 2312 counter and start the channel. */ 2313 __IOM uint32_t CH5_READ_ADDR; /*!< DMA Channel 5 Read Address pointer */ 2314 __IOM uint32_t CH5_WRITE_ADDR; /*!< DMA Channel 5 Write Address pointer */ 2315 __IOM uint32_t CH5_TRANS_COUNT; /*!< DMA Channel 5 Transfer Count */ 2316 __IOM uint32_t CH5_CTRL_TRIG; /*!< DMA Channel 5 Control and Status */ 2317 __IOM uint32_t CH5_AL1_CTRL; /*!< Alias for channel 5 CTRL register */ 2318 __IOM uint32_t CH5_AL1_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ 2319 __IOM uint32_t CH5_AL1_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ 2320 __IOM uint32_t CH5_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 5 TRANS_COUNT register This is a trigger register 2321 (0xc). Writing a nonzero value will reload the channel 2322 counter and start the channel. */ 2323 __IOM uint32_t CH5_AL2_CTRL; /*!< Alias for channel 5 CTRL register */ 2324 __IOM uint32_t CH5_AL2_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ 2325 __IOM uint32_t CH5_AL2_READ_ADDR; /*!< Alias for channel 5 READ_ADDR register */ 2326 __IOM uint32_t CH5_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 5 WRITE_ADDR register This is a trigger register 2327 (0xc). Writing a nonzero value will reload the channel 2328 counter and start the channel. */ 2329 __IOM uint32_t CH5_AL3_CTRL; /*!< Alias for channel 5 CTRL register */ 2330 __IOM uint32_t CH5_AL3_WRITE_ADDR; /*!< Alias for channel 5 WRITE_ADDR register */ 2331 __IOM uint32_t CH5_AL3_TRANS_COUNT; /*!< Alias for channel 5 TRANS_COUNT register */ 2332 __IOM uint32_t CH5_AL3_READ_ADDR_TRIG; /*!< Alias for channel 5 READ_ADDR register This is a trigger register 2333 (0xc). Writing a nonzero value will reload the channel 2334 counter and start the channel. */ 2335 __IOM uint32_t CH6_READ_ADDR; /*!< DMA Channel 6 Read Address pointer */ 2336 __IOM uint32_t CH6_WRITE_ADDR; /*!< DMA Channel 6 Write Address pointer */ 2337 __IOM uint32_t CH6_TRANS_COUNT; /*!< DMA Channel 6 Transfer Count */ 2338 __IOM uint32_t CH6_CTRL_TRIG; /*!< DMA Channel 6 Control and Status */ 2339 __IOM uint32_t CH6_AL1_CTRL; /*!< Alias for channel 6 CTRL register */ 2340 __IOM uint32_t CH6_AL1_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ 2341 __IOM uint32_t CH6_AL1_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ 2342 __IOM uint32_t CH6_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 6 TRANS_COUNT register This is a trigger register 2343 (0xc). Writing a nonzero value will reload the channel 2344 counter and start the channel. */ 2345 __IOM uint32_t CH6_AL2_CTRL; /*!< Alias for channel 6 CTRL register */ 2346 __IOM uint32_t CH6_AL2_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ 2347 __IOM uint32_t CH6_AL2_READ_ADDR; /*!< Alias for channel 6 READ_ADDR register */ 2348 __IOM uint32_t CH6_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 6 WRITE_ADDR register This is a trigger register 2349 (0xc). Writing a nonzero value will reload the channel 2350 counter and start the channel. */ 2351 __IOM uint32_t CH6_AL3_CTRL; /*!< Alias for channel 6 CTRL register */ 2352 __IOM uint32_t CH6_AL3_WRITE_ADDR; /*!< Alias for channel 6 WRITE_ADDR register */ 2353 __IOM uint32_t CH6_AL3_TRANS_COUNT; /*!< Alias for channel 6 TRANS_COUNT register */ 2354 __IOM uint32_t CH6_AL3_READ_ADDR_TRIG; /*!< Alias for channel 6 READ_ADDR register This is a trigger register 2355 (0xc). Writing a nonzero value will reload the channel 2356 counter and start the channel. */ 2357 __IOM uint32_t CH7_READ_ADDR; /*!< DMA Channel 7 Read Address pointer */ 2358 __IOM uint32_t CH7_WRITE_ADDR; /*!< DMA Channel 7 Write Address pointer */ 2359 __IOM uint32_t CH7_TRANS_COUNT; /*!< DMA Channel 7 Transfer Count */ 2360 __IOM uint32_t CH7_CTRL_TRIG; /*!< DMA Channel 7 Control and Status */ 2361 __IOM uint32_t CH7_AL1_CTRL; /*!< Alias for channel 7 CTRL register */ 2362 __IOM uint32_t CH7_AL1_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ 2363 __IOM uint32_t CH7_AL1_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ 2364 __IOM uint32_t CH7_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 7 TRANS_COUNT register This is a trigger register 2365 (0xc). Writing a nonzero value will reload the channel 2366 counter and start the channel. */ 2367 __IOM uint32_t CH7_AL2_CTRL; /*!< Alias for channel 7 CTRL register */ 2368 __IOM uint32_t CH7_AL2_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ 2369 __IOM uint32_t CH7_AL2_READ_ADDR; /*!< Alias for channel 7 READ_ADDR register */ 2370 __IOM uint32_t CH7_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 7 WRITE_ADDR register This is a trigger register 2371 (0xc). Writing a nonzero value will reload the channel 2372 counter and start the channel. */ 2373 __IOM uint32_t CH7_AL3_CTRL; /*!< Alias for channel 7 CTRL register */ 2374 __IOM uint32_t CH7_AL3_WRITE_ADDR; /*!< Alias for channel 7 WRITE_ADDR register */ 2375 __IOM uint32_t CH7_AL3_TRANS_COUNT; /*!< Alias for channel 7 TRANS_COUNT register */ 2376 __IOM uint32_t CH7_AL3_READ_ADDR_TRIG; /*!< Alias for channel 7 READ_ADDR register This is a trigger register 2377 (0xc). Writing a nonzero value will reload the channel 2378 counter and start the channel. */ 2379 __IOM uint32_t CH8_READ_ADDR; /*!< DMA Channel 8 Read Address pointer */ 2380 __IOM uint32_t CH8_WRITE_ADDR; /*!< DMA Channel 8 Write Address pointer */ 2381 __IOM uint32_t CH8_TRANS_COUNT; /*!< DMA Channel 8 Transfer Count */ 2382 __IOM uint32_t CH8_CTRL_TRIG; /*!< DMA Channel 8 Control and Status */ 2383 __IOM uint32_t CH8_AL1_CTRL; /*!< Alias for channel 8 CTRL register */ 2384 __IOM uint32_t CH8_AL1_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ 2385 __IOM uint32_t CH8_AL1_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ 2386 __IOM uint32_t CH8_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 8 TRANS_COUNT register This is a trigger register 2387 (0xc). Writing a nonzero value will reload the channel 2388 counter and start the channel. */ 2389 __IOM uint32_t CH8_AL2_CTRL; /*!< Alias for channel 8 CTRL register */ 2390 __IOM uint32_t CH8_AL2_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ 2391 __IOM uint32_t CH8_AL2_READ_ADDR; /*!< Alias for channel 8 READ_ADDR register */ 2392 __IOM uint32_t CH8_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 8 WRITE_ADDR register This is a trigger register 2393 (0xc). Writing a nonzero value will reload the channel 2394 counter and start the channel. */ 2395 __IOM uint32_t CH8_AL3_CTRL; /*!< Alias for channel 8 CTRL register */ 2396 __IOM uint32_t CH8_AL3_WRITE_ADDR; /*!< Alias for channel 8 WRITE_ADDR register */ 2397 __IOM uint32_t CH8_AL3_TRANS_COUNT; /*!< Alias for channel 8 TRANS_COUNT register */ 2398 __IOM uint32_t CH8_AL3_READ_ADDR_TRIG; /*!< Alias for channel 8 READ_ADDR register This is a trigger register 2399 (0xc). Writing a nonzero value will reload the channel 2400 counter and start the channel. */ 2401 __IOM uint32_t CH9_READ_ADDR; /*!< DMA Channel 9 Read Address pointer */ 2402 __IOM uint32_t CH9_WRITE_ADDR; /*!< DMA Channel 9 Write Address pointer */ 2403 __IOM uint32_t CH9_TRANS_COUNT; /*!< DMA Channel 9 Transfer Count */ 2404 __IOM uint32_t CH9_CTRL_TRIG; /*!< DMA Channel 9 Control and Status */ 2405 __IOM uint32_t CH9_AL1_CTRL; /*!< Alias for channel 9 CTRL register */ 2406 __IOM uint32_t CH9_AL1_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ 2407 __IOM uint32_t CH9_AL1_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ 2408 __IOM uint32_t CH9_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 9 TRANS_COUNT register This is a trigger register 2409 (0xc). Writing a nonzero value will reload the channel 2410 counter and start the channel. */ 2411 __IOM uint32_t CH9_AL2_CTRL; /*!< Alias for channel 9 CTRL register */ 2412 __IOM uint32_t CH9_AL2_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ 2413 __IOM uint32_t CH9_AL2_READ_ADDR; /*!< Alias for channel 9 READ_ADDR register */ 2414 __IOM uint32_t CH9_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 9 WRITE_ADDR register This is a trigger register 2415 (0xc). Writing a nonzero value will reload the channel 2416 counter and start the channel. */ 2417 __IOM uint32_t CH9_AL3_CTRL; /*!< Alias for channel 9 CTRL register */ 2418 __IOM uint32_t CH9_AL3_WRITE_ADDR; /*!< Alias for channel 9 WRITE_ADDR register */ 2419 __IOM uint32_t CH9_AL3_TRANS_COUNT; /*!< Alias for channel 9 TRANS_COUNT register */ 2420 __IOM uint32_t CH9_AL3_READ_ADDR_TRIG; /*!< Alias for channel 9 READ_ADDR register This is a trigger register 2421 (0xc). Writing a nonzero value will reload the channel 2422 counter and start the channel. */ 2423 __IOM uint32_t CH10_READ_ADDR; /*!< DMA Channel 10 Read Address pointer */ 2424 __IOM uint32_t CH10_WRITE_ADDR; /*!< DMA Channel 10 Write Address pointer */ 2425 __IOM uint32_t CH10_TRANS_COUNT; /*!< DMA Channel 10 Transfer Count */ 2426 __IOM uint32_t CH10_CTRL_TRIG; /*!< DMA Channel 10 Control and Status */ 2427 __IOM uint32_t CH10_AL1_CTRL; /*!< Alias for channel 10 CTRL register */ 2428 __IOM uint32_t CH10_AL1_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ 2429 __IOM uint32_t CH10_AL1_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ 2430 __IOM uint32_t CH10_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 10 TRANS_COUNT register This is a trigger 2431 register (0xc). Writing a nonzero value will reload the 2432 channel counter and start the channel. */ 2433 __IOM uint32_t CH10_AL2_CTRL; /*!< Alias for channel 10 CTRL register */ 2434 __IOM uint32_t CH10_AL2_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ 2435 __IOM uint32_t CH10_AL2_READ_ADDR; /*!< Alias for channel 10 READ_ADDR register */ 2436 __IOM uint32_t CH10_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 10 WRITE_ADDR register This is a trigger register 2437 (0xc). Writing a nonzero value will reload the channel 2438 counter and start the channel. */ 2439 __IOM uint32_t CH10_AL3_CTRL; /*!< Alias for channel 10 CTRL register */ 2440 __IOM uint32_t CH10_AL3_WRITE_ADDR; /*!< Alias for channel 10 WRITE_ADDR register */ 2441 __IOM uint32_t CH10_AL3_TRANS_COUNT; /*!< Alias for channel 10 TRANS_COUNT register */ 2442 __IOM uint32_t CH10_AL3_READ_ADDR_TRIG; /*!< Alias for channel 10 READ_ADDR register This is a trigger register 2443 (0xc). Writing a nonzero value will reload the channel 2444 counter and start the channel. */ 2445 __IOM uint32_t CH11_READ_ADDR; /*!< DMA Channel 11 Read Address pointer */ 2446 __IOM uint32_t CH11_WRITE_ADDR; /*!< DMA Channel 11 Write Address pointer */ 2447 __IOM uint32_t CH11_TRANS_COUNT; /*!< DMA Channel 11 Transfer Count */ 2448 __IOM uint32_t CH11_CTRL_TRIG; /*!< DMA Channel 11 Control and Status */ 2449 __IOM uint32_t CH11_AL1_CTRL; /*!< Alias for channel 11 CTRL register */ 2450 __IOM uint32_t CH11_AL1_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ 2451 __IOM uint32_t CH11_AL1_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ 2452 __IOM uint32_t CH11_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 11 TRANS_COUNT register This is a trigger 2453 register (0xc). Writing a nonzero value will reload the 2454 channel counter and start the channel. */ 2455 __IOM uint32_t CH11_AL2_CTRL; /*!< Alias for channel 11 CTRL register */ 2456 __IOM uint32_t CH11_AL2_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ 2457 __IOM uint32_t CH11_AL2_READ_ADDR; /*!< Alias for channel 11 READ_ADDR register */ 2458 __IOM uint32_t CH11_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 11 WRITE_ADDR register This is a trigger register 2459 (0xc). Writing a nonzero value will reload the channel 2460 counter and start the channel. */ 2461 __IOM uint32_t CH11_AL3_CTRL; /*!< Alias for channel 11 CTRL register */ 2462 __IOM uint32_t CH11_AL3_WRITE_ADDR; /*!< Alias for channel 11 WRITE_ADDR register */ 2463 __IOM uint32_t CH11_AL3_TRANS_COUNT; /*!< Alias for channel 11 TRANS_COUNT register */ 2464 __IOM uint32_t CH11_AL3_READ_ADDR_TRIG; /*!< Alias for channel 11 READ_ADDR register This is a trigger register 2465 (0xc). Writing a nonzero value will reload the channel 2466 counter and start the channel. */ 2467 __IOM uint32_t CH12_READ_ADDR; /*!< DMA Channel 12 Read Address pointer */ 2468 __IOM uint32_t CH12_WRITE_ADDR; /*!< DMA Channel 12 Write Address pointer */ 2469 __IOM uint32_t CH12_TRANS_COUNT; /*!< DMA Channel 12 Transfer Count */ 2470 __IOM uint32_t CH12_CTRL_TRIG; /*!< DMA Channel 12 Control and Status */ 2471 __IOM uint32_t CH12_AL1_CTRL; /*!< Alias for channel 12 CTRL register */ 2472 __IOM uint32_t CH12_AL1_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ 2473 __IOM uint32_t CH12_AL1_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ 2474 __IOM uint32_t CH12_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 12 TRANS_COUNT register This is a trigger 2475 register (0xc). Writing a nonzero value will reload the 2476 channel counter and start the channel. */ 2477 __IOM uint32_t CH12_AL2_CTRL; /*!< Alias for channel 12 CTRL register */ 2478 __IOM uint32_t CH12_AL2_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ 2479 __IOM uint32_t CH12_AL2_READ_ADDR; /*!< Alias for channel 12 READ_ADDR register */ 2480 __IOM uint32_t CH12_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 12 WRITE_ADDR register This is a trigger register 2481 (0xc). Writing a nonzero value will reload the channel 2482 counter and start the channel. */ 2483 __IOM uint32_t CH12_AL3_CTRL; /*!< Alias for channel 12 CTRL register */ 2484 __IOM uint32_t CH12_AL3_WRITE_ADDR; /*!< Alias for channel 12 WRITE_ADDR register */ 2485 __IOM uint32_t CH12_AL3_TRANS_COUNT; /*!< Alias for channel 12 TRANS_COUNT register */ 2486 __IOM uint32_t CH12_AL3_READ_ADDR_TRIG; /*!< Alias for channel 12 READ_ADDR register This is a trigger register 2487 (0xc). Writing a nonzero value will reload the channel 2488 counter and start the channel. */ 2489 __IOM uint32_t CH13_READ_ADDR; /*!< DMA Channel 13 Read Address pointer */ 2490 __IOM uint32_t CH13_WRITE_ADDR; /*!< DMA Channel 13 Write Address pointer */ 2491 __IOM uint32_t CH13_TRANS_COUNT; /*!< DMA Channel 13 Transfer Count */ 2492 __IOM uint32_t CH13_CTRL_TRIG; /*!< DMA Channel 13 Control and Status */ 2493 __IOM uint32_t CH13_AL1_CTRL; /*!< Alias for channel 13 CTRL register */ 2494 __IOM uint32_t CH13_AL1_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ 2495 __IOM uint32_t CH13_AL1_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ 2496 __IOM uint32_t CH13_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 13 TRANS_COUNT register This is a trigger 2497 register (0xc). Writing a nonzero value will reload the 2498 channel counter and start the channel. */ 2499 __IOM uint32_t CH13_AL2_CTRL; /*!< Alias for channel 13 CTRL register */ 2500 __IOM uint32_t CH13_AL2_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ 2501 __IOM uint32_t CH13_AL2_READ_ADDR; /*!< Alias for channel 13 READ_ADDR register */ 2502 __IOM uint32_t CH13_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 13 WRITE_ADDR register This is a trigger register 2503 (0xc). Writing a nonzero value will reload the channel 2504 counter and start the channel. */ 2505 __IOM uint32_t CH13_AL3_CTRL; /*!< Alias for channel 13 CTRL register */ 2506 __IOM uint32_t CH13_AL3_WRITE_ADDR; /*!< Alias for channel 13 WRITE_ADDR register */ 2507 __IOM uint32_t CH13_AL3_TRANS_COUNT; /*!< Alias for channel 13 TRANS_COUNT register */ 2508 __IOM uint32_t CH13_AL3_READ_ADDR_TRIG; /*!< Alias for channel 13 READ_ADDR register This is a trigger register 2509 (0xc). Writing a nonzero value will reload the channel 2510 counter and start the channel. */ 2511 __IOM uint32_t CH14_READ_ADDR; /*!< DMA Channel 14 Read Address pointer */ 2512 __IOM uint32_t CH14_WRITE_ADDR; /*!< DMA Channel 14 Write Address pointer */ 2513 __IOM uint32_t CH14_TRANS_COUNT; /*!< DMA Channel 14 Transfer Count */ 2514 __IOM uint32_t CH14_CTRL_TRIG; /*!< DMA Channel 14 Control and Status */ 2515 __IOM uint32_t CH14_AL1_CTRL; /*!< Alias for channel 14 CTRL register */ 2516 __IOM uint32_t CH14_AL1_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ 2517 __IOM uint32_t CH14_AL1_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ 2518 __IOM uint32_t CH14_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 14 TRANS_COUNT register This is a trigger 2519 register (0xc). Writing a nonzero value will reload the 2520 channel counter and start the channel. */ 2521 __IOM uint32_t CH14_AL2_CTRL; /*!< Alias for channel 14 CTRL register */ 2522 __IOM uint32_t CH14_AL2_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ 2523 __IOM uint32_t CH14_AL2_READ_ADDR; /*!< Alias for channel 14 READ_ADDR register */ 2524 __IOM uint32_t CH14_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 14 WRITE_ADDR register This is a trigger register 2525 (0xc). Writing a nonzero value will reload the channel 2526 counter and start the channel. */ 2527 __IOM uint32_t CH14_AL3_CTRL; /*!< Alias for channel 14 CTRL register */ 2528 __IOM uint32_t CH14_AL3_WRITE_ADDR; /*!< Alias for channel 14 WRITE_ADDR register */ 2529 __IOM uint32_t CH14_AL3_TRANS_COUNT; /*!< Alias for channel 14 TRANS_COUNT register */ 2530 __IOM uint32_t CH14_AL3_READ_ADDR_TRIG; /*!< Alias for channel 14 READ_ADDR register This is a trigger register 2531 (0xc). Writing a nonzero value will reload the channel 2532 counter and start the channel. */ 2533 __IOM uint32_t CH15_READ_ADDR; /*!< DMA Channel 15 Read Address pointer */ 2534 __IOM uint32_t CH15_WRITE_ADDR; /*!< DMA Channel 15 Write Address pointer */ 2535 __IOM uint32_t CH15_TRANS_COUNT; /*!< DMA Channel 15 Transfer Count */ 2536 __IOM uint32_t CH15_CTRL_TRIG; /*!< DMA Channel 15 Control and Status */ 2537 __IOM uint32_t CH15_AL1_CTRL; /*!< Alias for channel 15 CTRL register */ 2538 __IOM uint32_t CH15_AL1_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ 2539 __IOM uint32_t CH15_AL1_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ 2540 __IOM uint32_t CH15_AL1_TRANS_COUNT_TRIG; /*!< Alias for channel 15 TRANS_COUNT register This is a trigger 2541 register (0xc). Writing a nonzero value will reload the 2542 channel counter and start the channel. */ 2543 __IOM uint32_t CH15_AL2_CTRL; /*!< Alias for channel 15 CTRL register */ 2544 __IOM uint32_t CH15_AL2_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ 2545 __IOM uint32_t CH15_AL2_READ_ADDR; /*!< Alias for channel 15 READ_ADDR register */ 2546 __IOM uint32_t CH15_AL2_WRITE_ADDR_TRIG; /*!< Alias for channel 15 WRITE_ADDR register This is a trigger register 2547 (0xc). Writing a nonzero value will reload the channel 2548 counter and start the channel. */ 2549 __IOM uint32_t CH15_AL3_CTRL; /*!< Alias for channel 15 CTRL register */ 2550 __IOM uint32_t CH15_AL3_WRITE_ADDR; /*!< Alias for channel 15 WRITE_ADDR register */ 2551 __IOM uint32_t CH15_AL3_TRANS_COUNT; /*!< Alias for channel 15 TRANS_COUNT register */ 2552 __IOM uint32_t CH15_AL3_READ_ADDR_TRIG; /*!< Alias for channel 15 READ_ADDR register This is a trigger register 2553 (0xc). Writing a nonzero value will reload the channel 2554 counter and start the channel. */ 2555 __IOM uint32_t INTR; /*!< Interrupt Status (raw) */ 2556 __IOM uint32_t INTE0; /*!< Interrupt Enables for IRQ 0 */ 2557 __IOM uint32_t INTF0; /*!< Force Interrupts */ 2558 __IOM uint32_t INTS0; /*!< Interrupt Status for IRQ 0 */ 2559 __IOM uint32_t INTR1; /*!< Interrupt Status (raw) */ 2560 __IOM uint32_t INTE1; /*!< Interrupt Enables for IRQ 1 */ 2561 __IOM uint32_t INTF1; /*!< Force Interrupts */ 2562 __IOM uint32_t INTS1; /*!< Interrupt Status for IRQ 1 */ 2563 __IOM uint32_t INTR2; /*!< Interrupt Status (raw) */ 2564 __IOM uint32_t INTE2; /*!< Interrupt Enables for IRQ 2 */ 2565 __IOM uint32_t INTF2; /*!< Force Interrupts */ 2566 __IOM uint32_t INTS2; /*!< Interrupt Status for IRQ 2 */ 2567 __IOM uint32_t INTR3; /*!< Interrupt Status (raw) */ 2568 __IOM uint32_t INTE3; /*!< Interrupt Enables for IRQ 3 */ 2569 __IOM uint32_t INTF3; /*!< Force Interrupts */ 2570 __IOM uint32_t INTS3; /*!< Interrupt Status for IRQ 3 */ 2571 __IOM uint32_t TIMER0; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ 2572 assertions at a rate set by ((X/Y) * sys_clk). This equation 2573 is evaluated every sys_clk cycles and therefore can only 2574 generate TREQs at a rate of 1 per sys_clk (i.e. permanent 2575 TREQ) or less. */ 2576 __IOM uint32_t TIMER1; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ 2577 assertions at a rate set by ((X/Y) * sys_clk). This equation 2578 is evaluated every sys_clk cycles and therefore can only 2579 generate TREQs at a rate of 1 per sys_clk (i.e. permanent 2580 TREQ) or less. */ 2581 __IOM uint32_t TIMER2; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ 2582 assertions at a rate set by ((X/Y) * sys_clk). This equation 2583 is evaluated every sys_clk cycles and therefore can only 2584 generate TREQs at a rate of 1 per sys_clk (i.e. permanent 2585 TREQ) or less. */ 2586 __IOM uint32_t TIMER3; /*!< Pacing (X/Y) fractional timer The pacing timer produces TREQ 2587 assertions at a rate set by ((X/Y) * sys_clk). This equation 2588 is evaluated every sys_clk cycles and therefore can only 2589 generate TREQs at a rate of 1 per sys_clk (i.e. permanent 2590 TREQ) or less. */ 2591 __IOM uint32_t MULTI_CHAN_TRIGGER; /*!< Trigger one or more channels simultaneously */ 2592 __IOM uint32_t SNIFF_CTRL; /*!< Sniffer Control */ 2593 __IOM uint32_t SNIFF_DATA; /*!< Data accumulator for sniff hardware */ 2594 __IM uint32_t RESERVED; 2595 __IOM uint32_t FIFO_LEVELS; /*!< Debug RAF, WAF, TDF levels */ 2596 __IOM uint32_t CHAN_ABORT; /*!< Abort an in-progress transfer sequence on one or more channels */ 2597 __IOM uint32_t N_CHANNELS; /*!< The number of channels this DMA instance is equipped with. This 2598 DMA supports up to 16 hardware channels, but can be configured 2599 with as few as one, to minimise silicon area. */ 2600 __IM uint32_t RESERVED1[5]; 2601 __IOM uint32_t SECCFG_CH0; /*!< Security configuration for channel 0. Control whether this channel 2602 performs Secure/Non-secure and Privileged/Unprivileged 2603 bus accesses. If this channel generates bus accesses of 2604 some security level, an access of at least that level (in 2605 the order S+P > S+U > NS+P > NS+U) is required to program, 2606 trigger, abort, check the status of, interrupt on or acknowledge 2607 the interrupt of this channel. This register automatically 2608 locks down (becomes read-only) once software starts to 2609 configure the channel. This register is world-readable, 2610 but is writable only from a Secure, Privileged context. */ 2611 __IOM uint32_t SECCFG_CH1; /*!< Security configuration for channel 1. Control whether this channel 2612 performs Secure/Non-secure and Privileged/Unprivileged 2613 bus accesses. If this channel generates bus accesses of 2614 some security level, an access of at least that level (in 2615 the order S+P > S+U > NS+P > NS+U) is required to program, 2616 trigger, abort, check the status of, interrupt on or acknowledge 2617 the interrupt of this channel. This register automatically 2618 locks down (becomes read-only) once software starts to 2619 configure the channel. This register is world-readable, 2620 but is writable only from a Secure, Privileged context. */ 2621 __IOM uint32_t SECCFG_CH2; /*!< Security configuration for channel 2. Control whether this channel 2622 performs Secure/Non-secure and Privileged/Unprivileged 2623 bus accesses. If this channel generates bus accesses of 2624 some security level, an access of at least that level (in 2625 the order S+P > S+U > NS+P > NS+U) is required to program, 2626 trigger, abort, check the status of, interrupt on or acknowledge 2627 the interrupt of this channel. This register automatically 2628 locks down (becomes read-only) once software starts to 2629 configure the channel. This register is world-readable, 2630 but is writable only from a Secure, Privileged context. */ 2631 __IOM uint32_t SECCFG_CH3; /*!< Security configuration for channel 3. Control whether this channel 2632 performs Secure/Non-secure and Privileged/Unprivileged 2633 bus accesses. If this channel generates bus accesses of 2634 some security level, an access of at least that level (in 2635 the order S+P > S+U > NS+P > NS+U) is required to program, 2636 trigger, abort, check the status of, interrupt on or acknowledge 2637 the interrupt of this channel. This register automatically 2638 locks down (becomes read-only) once software starts to 2639 configure the channel. This register is world-readable, 2640 but is writable only from a Secure, Privileged context. */ 2641 __IOM uint32_t SECCFG_CH4; /*!< Security configuration for channel 4. Control whether this channel 2642 performs Secure/Non-secure and Privileged/Unprivileged 2643 bus accesses. If this channel generates bus accesses of 2644 some security level, an access of at least that level (in 2645 the order S+P > S+U > NS+P > NS+U) is required to program, 2646 trigger, abort, check the status of, interrupt on or acknowledge 2647 the interrupt of this channel. This register automatically 2648 locks down (becomes read-only) once software starts to 2649 configure the channel. This register is world-readable, 2650 but is writable only from a Secure, Privileged context. */ 2651 __IOM uint32_t SECCFG_CH5; /*!< Security configuration for channel 5. Control whether this channel 2652 performs Secure/Non-secure and Privileged/Unprivileged 2653 bus accesses. If this channel generates bus accesses of 2654 some security level, an access of at least that level (in 2655 the order S+P > S+U > NS+P > NS+U) is required to program, 2656 trigger, abort, check the status of, interrupt on or acknowledge 2657 the interrupt of this channel. This register automatically 2658 locks down (becomes read-only) once software starts to 2659 configure the channel. This register is world-readable, 2660 but is writable only from a Secure, Privileged context. */ 2661 __IOM uint32_t SECCFG_CH6; /*!< Security configuration for channel 6. Control whether this channel 2662 performs Secure/Non-secure and Privileged/Unprivileged 2663 bus accesses. If this channel generates bus accesses of 2664 some security level, an access of at least that level (in 2665 the order S+P > S+U > NS+P > NS+U) is required to program, 2666 trigger, abort, check the status of, interrupt on or acknowledge 2667 the interrupt of this channel. This register automatically 2668 locks down (becomes read-only) once software starts to 2669 configure the channel. This register is world-readable, 2670 but is writable only from a Secure, Privileged context. */ 2671 __IOM uint32_t SECCFG_CH7; /*!< Security configuration for channel 7. Control whether this channel 2672 performs Secure/Non-secure and Privileged/Unprivileged 2673 bus accesses. If this channel generates bus accesses of 2674 some security level, an access of at least that level (in 2675 the order S+P > S+U > NS+P > NS+U) is required to program, 2676 trigger, abort, check the status of, interrupt on or acknowledge 2677 the interrupt of this channel. This register automatically 2678 locks down (becomes read-only) once software starts to 2679 configure the channel. This register is world-readable, 2680 but is writable only from a Secure, Privileged context. */ 2681 __IOM uint32_t SECCFG_CH8; /*!< Security configuration for channel 8. Control whether this channel 2682 performs Secure/Non-secure and Privileged/Unprivileged 2683 bus accesses. If this channel generates bus accesses of 2684 some security level, an access of at least that level (in 2685 the order S+P > S+U > NS+P > NS+U) is required to program, 2686 trigger, abort, check the status of, interrupt on or acknowledge 2687 the interrupt of this channel. This register automatically 2688 locks down (becomes read-only) once software starts to 2689 configure the channel. This register is world-readable, 2690 but is writable only from a Secure, Privileged context. */ 2691 __IOM uint32_t SECCFG_CH9; /*!< Security configuration for channel 9. Control whether this channel 2692 performs Secure/Non-secure and Privileged/Unprivileged 2693 bus accesses. If this channel generates bus accesses of 2694 some security level, an access of at least that level (in 2695 the order S+P > S+U > NS+P > NS+U) is required to program, 2696 trigger, abort, check the status of, interrupt on or acknowledge 2697 the interrupt of this channel. This register automatically 2698 locks down (becomes read-only) once software starts to 2699 configure the channel. This register is world-readable, 2700 but is writable only from a Secure, Privileged context. */ 2701 __IOM uint32_t SECCFG_CH10; /*!< Security configuration for channel 10. Control whether this 2702 channel performs Secure/Non-secure and Privileged/Unprivileged 2703 bus accesses. If this channel generates bus accesses of 2704 some security level, an access of at least that level (in 2705 the order S+P > S+U > NS+P > NS+U) is required to program, 2706 trigger, abort, check the status of, interrupt on or acknowledge 2707 the interrupt of this channel. This register automatically 2708 locks down (becomes read-only) once software starts to 2709 configure the channel. This register is world-readable, 2710 but is writable only from a Secure, Privileged context. */ 2711 __IOM uint32_t SECCFG_CH11; /*!< Security configuration for channel 11. Control whether this 2712 channel performs Secure/Non-secure and Privileged/Unprivileged 2713 bus accesses. If this channel generates bus accesses of 2714 some security level, an access of at least that level (in 2715 the order S+P > S+U > NS+P > NS+U) is required to program, 2716 trigger, abort, check the status of, interrupt on or acknowledge 2717 the interrupt of this channel. This register automatically 2718 locks down (becomes read-only) once software starts to 2719 configure the channel. This register is world-readable, 2720 but is writable only from a Secure, Privileged context. */ 2721 __IOM uint32_t SECCFG_CH12; /*!< Security configuration for channel 12. Control whether this 2722 channel performs Secure/Non-secure and Privileged/Unprivileged 2723 bus accesses. If this channel generates bus accesses of 2724 some security level, an access of at least that level (in 2725 the order S+P > S+U > NS+P > NS+U) is required to program, 2726 trigger, abort, check the status of, interrupt on or acknowledge 2727 the interrupt of this channel. This register automatically 2728 locks down (becomes read-only) once software starts to 2729 configure the channel. This register is world-readable, 2730 but is writable only from a Secure, Privileged context. */ 2731 __IOM uint32_t SECCFG_CH13; /*!< Security configuration for channel 13. Control whether this 2732 channel performs Secure/Non-secure and Privileged/Unprivileged 2733 bus accesses. If this channel generates bus accesses of 2734 some security level, an access of at least that level (in 2735 the order S+P > S+U > NS+P > NS+U) is required to program, 2736 trigger, abort, check the status of, interrupt on or acknowledge 2737 the interrupt of this channel. This register automatically 2738 locks down (becomes read-only) once software starts to 2739 configure the channel. This register is world-readable, 2740 but is writable only from a Secure, Privileged context. */ 2741 __IOM uint32_t SECCFG_CH14; /*!< Security configuration for channel 14. Control whether this 2742 channel performs Secure/Non-secure and Privileged/Unprivileged 2743 bus accesses. If this channel generates bus accesses of 2744 some security level, an access of at least that level (in 2745 the order S+P > S+U > NS+P > NS+U) is required to program, 2746 trigger, abort, check the status of, interrupt on or acknowledge 2747 the interrupt of this channel. This register automatically 2748 locks down (becomes read-only) once software starts to 2749 configure the channel. This register is world-readable, 2750 but is writable only from a Secure, Privileged context. */ 2751 __IOM uint32_t SECCFG_CH15; /*!< Security configuration for channel 15. Control whether this 2752 channel performs Secure/Non-secure and Privileged/Unprivileged 2753 bus accesses. If this channel generates bus accesses of 2754 some security level, an access of at least that level (in 2755 the order S+P > S+U > NS+P > NS+U) is required to program, 2756 trigger, abort, check the status of, interrupt on or acknowledge 2757 the interrupt of this channel. This register automatically 2758 locks down (becomes read-only) once software starts to 2759 configure the channel. This register is world-readable, 2760 but is writable only from a Secure, Privileged context. */ 2761 __IOM uint32_t SECCFG_IRQ0; /*!< Security configuration for IRQ 0. Control whether the IRQ permits 2762 configuration by Non-secure/Unprivileged contexts, and 2763 whether it can observe Secure/Privileged channel interrupt 2764 flags. */ 2765 __IOM uint32_t SECCFG_IRQ1; /*!< Security configuration for IRQ 1. Control whether the IRQ permits 2766 configuration by Non-secure/Unprivileged contexts, and 2767 whether it can observe Secure/Privileged channel interrupt 2768 flags. */ 2769 __IOM uint32_t SECCFG_IRQ2; /*!< Security configuration for IRQ 2. Control whether the IRQ permits 2770 configuration by Non-secure/Unprivileged contexts, and 2771 whether it can observe Secure/Privileged channel interrupt 2772 flags. */ 2773 __IOM uint32_t SECCFG_IRQ3; /*!< Security configuration for IRQ 3. Control whether the IRQ permits 2774 configuration by Non-secure/Unprivileged contexts, and 2775 whether it can observe Secure/Privileged channel interrupt 2776 flags. */ 2777 __IOM uint32_t SECCFG_MISC; /*!< Miscellaneous security configuration */ 2778 __IM uint32_t RESERVED2[11]; 2779 __IOM uint32_t MPU_CTRL; /*!< Control register for DMA MPU. Accessible only from a Privileged 2780 context. */ 2781 __IOM uint32_t MPU_BAR0; /*!< Base address register for MPU region 0. Writable only from a 2782 Secure, Privileged context. */ 2783 __IOM uint32_t MPU_LAR0; /*!< Limit address register for MPU region 0. Writable only from 2784 a Secure, Privileged context, with the exception of the 2785 P bit. */ 2786 __IOM uint32_t MPU_BAR1; /*!< Base address register for MPU region 1. Writable only from a 2787 Secure, Privileged context. */ 2788 __IOM uint32_t MPU_LAR1; /*!< Limit address register for MPU region 1. Writable only from 2789 a Secure, Privileged context, with the exception of the 2790 P bit. */ 2791 __IOM uint32_t MPU_BAR2; /*!< Base address register for MPU region 2. Writable only from a 2792 Secure, Privileged context. */ 2793 __IOM uint32_t MPU_LAR2; /*!< Limit address register for MPU region 2. Writable only from 2794 a Secure, Privileged context, with the exception of the 2795 P bit. */ 2796 __IOM uint32_t MPU_BAR3; /*!< Base address register for MPU region 3. Writable only from a 2797 Secure, Privileged context. */ 2798 __IOM uint32_t MPU_LAR3; /*!< Limit address register for MPU region 3. Writable only from 2799 a Secure, Privileged context, with the exception of the 2800 P bit. */ 2801 __IOM uint32_t MPU_BAR4; /*!< Base address register for MPU region 4. Writable only from a 2802 Secure, Privileged context. */ 2803 __IOM uint32_t MPU_LAR4; /*!< Limit address register for MPU region 4. Writable only from 2804 a Secure, Privileged context, with the exception of the 2805 P bit. */ 2806 __IOM uint32_t MPU_BAR5; /*!< Base address register for MPU region 5. Writable only from a 2807 Secure, Privileged context. */ 2808 __IOM uint32_t MPU_LAR5; /*!< Limit address register for MPU region 5. Writable only from 2809 a Secure, Privileged context, with the exception of the 2810 P bit. */ 2811 __IOM uint32_t MPU_BAR6; /*!< Base address register for MPU region 6. Writable only from a 2812 Secure, Privileged context. */ 2813 __IOM uint32_t MPU_LAR6; /*!< Limit address register for MPU region 6. Writable only from 2814 a Secure, Privileged context, with the exception of the 2815 P bit. */ 2816 __IOM uint32_t MPU_BAR7; /*!< Base address register for MPU region 7. Writable only from a 2817 Secure, Privileged context. */ 2818 __IOM uint32_t MPU_LAR7; /*!< Limit address register for MPU region 7. Writable only from 2819 a Secure, Privileged context, with the exception of the 2820 P bit. */ 2821 __IM uint32_t RESERVED3[175]; 2822 __IOM uint32_t CH0_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2823 expects it can perform on the peripheral without overflow/underflow. 2824 Write any value: clears the counter, and cause channel 2825 to re-initiate DREQ handshake. */ 2826 __IOM uint32_t CH0_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2827 of the next transfer */ 2828 __IM uint32_t RESERVED4[14]; 2829 __IOM uint32_t CH1_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2830 expects it can perform on the peripheral without overflow/underflow. 2831 Write any value: clears the counter, and cause channel 2832 to re-initiate DREQ handshake. */ 2833 __IOM uint32_t CH1_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2834 of the next transfer */ 2835 __IM uint32_t RESERVED5[14]; 2836 __IOM uint32_t CH2_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2837 expects it can perform on the peripheral without overflow/underflow. 2838 Write any value: clears the counter, and cause channel 2839 to re-initiate DREQ handshake. */ 2840 __IOM uint32_t CH2_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2841 of the next transfer */ 2842 __IM uint32_t RESERVED6[14]; 2843 __IOM uint32_t CH3_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2844 expects it can perform on the peripheral without overflow/underflow. 2845 Write any value: clears the counter, and cause channel 2846 to re-initiate DREQ handshake. */ 2847 __IOM uint32_t CH3_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2848 of the next transfer */ 2849 __IM uint32_t RESERVED7[14]; 2850 __IOM uint32_t CH4_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2851 expects it can perform on the peripheral without overflow/underflow. 2852 Write any value: clears the counter, and cause channel 2853 to re-initiate DREQ handshake. */ 2854 __IOM uint32_t CH4_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2855 of the next transfer */ 2856 __IM uint32_t RESERVED8[14]; 2857 __IOM uint32_t CH5_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2858 expects it can perform on the peripheral without overflow/underflow. 2859 Write any value: clears the counter, and cause channel 2860 to re-initiate DREQ handshake. */ 2861 __IOM uint32_t CH5_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2862 of the next transfer */ 2863 __IM uint32_t RESERVED9[14]; 2864 __IOM uint32_t CH6_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2865 expects it can perform on the peripheral without overflow/underflow. 2866 Write any value: clears the counter, and cause channel 2867 to re-initiate DREQ handshake. */ 2868 __IOM uint32_t CH6_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2869 of the next transfer */ 2870 __IM uint32_t RESERVED10[14]; 2871 __IOM uint32_t CH7_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2872 expects it can perform on the peripheral without overflow/underflow. 2873 Write any value: clears the counter, and cause channel 2874 to re-initiate DREQ handshake. */ 2875 __IOM uint32_t CH7_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2876 of the next transfer */ 2877 __IM uint32_t RESERVED11[14]; 2878 __IOM uint32_t CH8_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2879 expects it can perform on the peripheral without overflow/underflow. 2880 Write any value: clears the counter, and cause channel 2881 to re-initiate DREQ handshake. */ 2882 __IOM uint32_t CH8_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2883 of the next transfer */ 2884 __IM uint32_t RESERVED12[14]; 2885 __IOM uint32_t CH9_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2886 expects it can perform on the peripheral without overflow/underflow. 2887 Write any value: clears the counter, and cause channel 2888 to re-initiate DREQ handshake. */ 2889 __IOM uint32_t CH9_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2890 of the next transfer */ 2891 __IM uint32_t RESERVED13[14]; 2892 __IOM uint32_t CH10_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2893 expects it can perform on the peripheral without overflow/underflow. 2894 Write any value: clears the counter, and cause channel 2895 to re-initiate DREQ handshake. */ 2896 __IOM uint32_t CH10_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2897 of the next transfer */ 2898 __IM uint32_t RESERVED14[14]; 2899 __IOM uint32_t CH11_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2900 expects it can perform on the peripheral without overflow/underflow. 2901 Write any value: clears the counter, and cause channel 2902 to re-initiate DREQ handshake. */ 2903 __IOM uint32_t CH11_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2904 of the next transfer */ 2905 __IM uint32_t RESERVED15[14]; 2906 __IOM uint32_t CH12_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2907 expects it can perform on the peripheral without overflow/underflow. 2908 Write any value: clears the counter, and cause channel 2909 to re-initiate DREQ handshake. */ 2910 __IOM uint32_t CH12_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2911 of the next transfer */ 2912 __IM uint32_t RESERVED16[14]; 2913 __IOM uint32_t CH13_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2914 expects it can perform on the peripheral without overflow/underflow. 2915 Write any value: clears the counter, and cause channel 2916 to re-initiate DREQ handshake. */ 2917 __IOM uint32_t CH13_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2918 of the next transfer */ 2919 __IM uint32_t RESERVED17[14]; 2920 __IOM uint32_t CH14_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2921 expects it can perform on the peripheral without overflow/underflow. 2922 Write any value: clears the counter, and cause channel 2923 to re-initiate DREQ handshake. */ 2924 __IOM uint32_t CH14_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2925 of the next transfer */ 2926 __IM uint32_t RESERVED18[14]; 2927 __IOM uint32_t CH15_DBG_CTDREQ; /*!< Read: get channel DREQ counter (i.e. how many accesses the DMA 2928 expects it can perform on the peripheral without overflow/underflow. 2929 Write any value: clears the counter, and cause channel 2930 to re-initiate DREQ handshake. */ 2931 __IOM uint32_t CH15_DBG_TCR; /*!< Read to get channel TRANS_COUNT reload value, i.e. the length 2932 of the next transfer */ 2933 } DMA_Type; /*!< Size = 3016 (0xbc8) */ 2934 2935 2936 2937 /* =========================================================================================================================== */ 2938 /* ================ TIMER0 ================ */ 2939 /* =========================================================================================================================== */ 2940 2941 2942 /** 2943 * @brief Controls time and alarms 2944 2945 time is a 64 bit value indicating the time since power-on 2946 2947 timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr 2948 2949 An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq The timer can be locked to prevent writing (TIMER0) 2950 */ 2951 2952 typedef struct { /*!< TIMER0 Structure */ 2953 __IOM uint32_t TIMEHW; /*!< Write to bits 63:32 of time always write timelw before timehw */ 2954 __IOM uint32_t TIMELW; /*!< Write to bits 31:0 of time writes do not get copied to time 2955 until timehw is written */ 2956 __IOM uint32_t TIMEHR; /*!< Read from bits 63:32 of time always read timelr before timehr */ 2957 __IOM uint32_t TIMELR; /*!< Read from bits 31:0 of time */ 2958 __IOM uint32_t ALARM0; /*!< Arm alarm 0, and configure the time it will fire. Once armed, 2959 the alarm fires when TIMER_ALARM0 == TIMELR. The alarm 2960 will disarm itself once it fires, and can be disarmed early 2961 using the ARMED status register. */ 2962 __IOM uint32_t ALARM1; /*!< Arm alarm 1, and configure the time it will fire. Once armed, 2963 the alarm fires when TIMER_ALARM1 == TIMELR. The alarm 2964 will disarm itself once it fires, and can be disarmed early 2965 using the ARMED status register. */ 2966 __IOM uint32_t ALARM2; /*!< Arm alarm 2, and configure the time it will fire. Once armed, 2967 the alarm fires when TIMER_ALARM2 == TIMELR. The alarm 2968 will disarm itself once it fires, and can be disarmed early 2969 using the ARMED status register. */ 2970 __IOM uint32_t ALARM3; /*!< Arm alarm 3, and configure the time it will fire. Once armed, 2971 the alarm fires when TIMER_ALARM3 == TIMELR. The alarm 2972 will disarm itself once it fires, and can be disarmed early 2973 using the ARMED status register. */ 2974 __IOM uint32_t ARMED; /*!< Indicates the armed/disarmed status of each alarm. A write to 2975 the corresponding ALARMx register arms the alarm. Alarms 2976 automatically disarm upon firing, but writing ones here 2977 will disarm immediately without waiting to fire. */ 2978 __IOM uint32_t TIMERAWH; /*!< Raw read from bits 63:32 of time (no side effects) */ 2979 __IOM uint32_t TIMERAWL; /*!< Raw read from bits 31:0 of time (no side effects) */ 2980 __IOM uint32_t DBGPAUSE; /*!< Set bits high to enable pause when the corresponding debug ports 2981 are active */ 2982 __IOM uint32_t PAUSE; /*!< Set high to pause the timer */ 2983 __IOM uint32_t LOCKED; /*!< Set locked bit to disable write access to timer Once set, cannot 2984 be cleared (without a reset) */ 2985 __IOM uint32_t SOURCE; /*!< Selects the source for the timer. Defaults to the normal tick 2986 configured in the ticks block (typically configured to 2987 1 microsecond). Writing to 1 will ignore the tick and count 2988 clk_sys cycles instead. */ 2989 __IOM uint32_t INTR; /*!< Raw Interrupts */ 2990 __IOM uint32_t INTE; /*!< Interrupt Enable */ 2991 __IOM uint32_t INTF; /*!< Interrupt Force */ 2992 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 2993 } TIMER0_Type; /*!< Size = 76 (0x4c) */ 2994 2995 2996 2997 /* =========================================================================================================================== */ 2998 /* ================ PWM ================ */ 2999 /* =========================================================================================================================== */ 3000 3001 3002 /** 3003 * @brief Simple PWM (PWM) 3004 */ 3005 3006 typedef struct { /*!< PWM Structure */ 3007 __IOM uint32_t CH0_CSR; /*!< Control and status register */ 3008 __IOM uint32_t CH0_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3009 rate is system clock frequency divided by this number. 3010 Fractional division uses simple 1st-order sigma-delta. */ 3011 __IOM uint32_t CH0_CTR; /*!< Direct access to the PWM counter */ 3012 __IOM uint32_t CH0_CC; /*!< Counter compare values */ 3013 __IOM uint32_t CH0_TOP; /*!< Counter wrap value */ 3014 __IOM uint32_t CH1_CSR; /*!< Control and status register */ 3015 __IOM uint32_t CH1_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3016 rate is system clock frequency divided by this number. 3017 Fractional division uses simple 1st-order sigma-delta. */ 3018 __IOM uint32_t CH1_CTR; /*!< Direct access to the PWM counter */ 3019 __IOM uint32_t CH1_CC; /*!< Counter compare values */ 3020 __IOM uint32_t CH1_TOP; /*!< Counter wrap value */ 3021 __IOM uint32_t CH2_CSR; /*!< Control and status register */ 3022 __IOM uint32_t CH2_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3023 rate is system clock frequency divided by this number. 3024 Fractional division uses simple 1st-order sigma-delta. */ 3025 __IOM uint32_t CH2_CTR; /*!< Direct access to the PWM counter */ 3026 __IOM uint32_t CH2_CC; /*!< Counter compare values */ 3027 __IOM uint32_t CH2_TOP; /*!< Counter wrap value */ 3028 __IOM uint32_t CH3_CSR; /*!< Control and status register */ 3029 __IOM uint32_t CH3_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3030 rate is system clock frequency divided by this number. 3031 Fractional division uses simple 1st-order sigma-delta. */ 3032 __IOM uint32_t CH3_CTR; /*!< Direct access to the PWM counter */ 3033 __IOM uint32_t CH3_CC; /*!< Counter compare values */ 3034 __IOM uint32_t CH3_TOP; /*!< Counter wrap value */ 3035 __IOM uint32_t CH4_CSR; /*!< Control and status register */ 3036 __IOM uint32_t CH4_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3037 rate is system clock frequency divided by this number. 3038 Fractional division uses simple 1st-order sigma-delta. */ 3039 __IOM uint32_t CH4_CTR; /*!< Direct access to the PWM counter */ 3040 __IOM uint32_t CH4_CC; /*!< Counter compare values */ 3041 __IOM uint32_t CH4_TOP; /*!< Counter wrap value */ 3042 __IOM uint32_t CH5_CSR; /*!< Control and status register */ 3043 __IOM uint32_t CH5_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3044 rate is system clock frequency divided by this number. 3045 Fractional division uses simple 1st-order sigma-delta. */ 3046 __IOM uint32_t CH5_CTR; /*!< Direct access to the PWM counter */ 3047 __IOM uint32_t CH5_CC; /*!< Counter compare values */ 3048 __IOM uint32_t CH5_TOP; /*!< Counter wrap value */ 3049 __IOM uint32_t CH6_CSR; /*!< Control and status register */ 3050 __IOM uint32_t CH6_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3051 rate is system clock frequency divided by this number. 3052 Fractional division uses simple 1st-order sigma-delta. */ 3053 __IOM uint32_t CH6_CTR; /*!< Direct access to the PWM counter */ 3054 __IOM uint32_t CH6_CC; /*!< Counter compare values */ 3055 __IOM uint32_t CH6_TOP; /*!< Counter wrap value */ 3056 __IOM uint32_t CH7_CSR; /*!< Control and status register */ 3057 __IOM uint32_t CH7_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3058 rate is system clock frequency divided by this number. 3059 Fractional division uses simple 1st-order sigma-delta. */ 3060 __IOM uint32_t CH7_CTR; /*!< Direct access to the PWM counter */ 3061 __IOM uint32_t CH7_CC; /*!< Counter compare values */ 3062 __IOM uint32_t CH7_TOP; /*!< Counter wrap value */ 3063 __IOM uint32_t CH8_CSR; /*!< Control and status register */ 3064 __IOM uint32_t CH8_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3065 rate is system clock frequency divided by this number. 3066 Fractional division uses simple 1st-order sigma-delta. */ 3067 __IOM uint32_t CH8_CTR; /*!< Direct access to the PWM counter */ 3068 __IOM uint32_t CH8_CC; /*!< Counter compare values */ 3069 __IOM uint32_t CH8_TOP; /*!< Counter wrap value */ 3070 __IOM uint32_t CH9_CSR; /*!< Control and status register */ 3071 __IOM uint32_t CH9_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3072 rate is system clock frequency divided by this number. 3073 Fractional division uses simple 1st-order sigma-delta. */ 3074 __IOM uint32_t CH9_CTR; /*!< Direct access to the PWM counter */ 3075 __IOM uint32_t CH9_CC; /*!< Counter compare values */ 3076 __IOM uint32_t CH9_TOP; /*!< Counter wrap value */ 3077 __IOM uint32_t CH10_CSR; /*!< Control and status register */ 3078 __IOM uint32_t CH10_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3079 rate is system clock frequency divided by this number. 3080 Fractional division uses simple 1st-order sigma-delta. */ 3081 __IOM uint32_t CH10_CTR; /*!< Direct access to the PWM counter */ 3082 __IOM uint32_t CH10_CC; /*!< Counter compare values */ 3083 __IOM uint32_t CH10_TOP; /*!< Counter wrap value */ 3084 __IOM uint32_t CH11_CSR; /*!< Control and status register */ 3085 __IOM uint32_t CH11_DIV; /*!< INT and FRAC form a fixed-point fractional number. Counting 3086 rate is system clock frequency divided by this number. 3087 Fractional division uses simple 1st-order sigma-delta. */ 3088 __IOM uint32_t CH11_CTR; /*!< Direct access to the PWM counter */ 3089 __IOM uint32_t CH11_CC; /*!< Counter compare values */ 3090 __IOM uint32_t CH11_TOP; /*!< Counter wrap value */ 3091 __IOM uint32_t EN; /*!< This register aliases the CSR_EN bits for all channels. Writing 3092 to this register allows multiple channels to be enabled 3093 or disabled simultaneously, so they can run in perfect 3094 sync. For each channel, there is only one physical EN register 3095 bit, which can be accessed through here or CHx_CSR. */ 3096 __IOM uint32_t INTR; /*!< Raw Interrupts */ 3097 __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ 3098 __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ 3099 __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ 3100 __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ 3101 __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ 3102 __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ 3103 } PWM_Type; /*!< Size = 272 (0x110) */ 3104 3105 3106 3107 /* =========================================================================================================================== */ 3108 /* ================ ADC ================ */ 3109 /* =========================================================================================================================== */ 3110 3111 3112 /** 3113 * @brief Control and data interface to SAR ADC (ADC) 3114 */ 3115 3116 typedef struct { /*!< ADC Structure */ 3117 __IOM uint32_t CS; /*!< ADC Control and Status */ 3118 __IOM uint32_t RESULT; /*!< Result of most recent ADC conversion */ 3119 __IOM uint32_t FCS; /*!< FIFO control and status */ 3120 __IOM uint32_t FIFO; /*!< Conversion result FIFO */ 3121 __IOM uint32_t DIV; /*!< Clock divider. If non-zero, CS_START_MANY will start conversions 3122 at regular intervals rather than back-to-back. The divider 3123 is reset when either of these fields are written. Total 3124 period is 1 + INT + FRAC / 256 */ 3125 __IOM uint32_t INTR; /*!< Raw Interrupts */ 3126 __IOM uint32_t INTE; /*!< Interrupt Enable */ 3127 __IOM uint32_t INTF; /*!< Interrupt Force */ 3128 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 3129 } ADC_Type; /*!< Size = 36 (0x24) */ 3130 3131 3132 3133 /* =========================================================================================================================== */ 3134 /* ================ I2C0 ================ */ 3135 /* =========================================================================================================================== */ 3136 3137 3138 /** 3139 * @brief DW_apb_i2c address block 3140 3141 List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): 3142 3143 IC_ULTRA_FAST_MODE ................ 0x0 3144 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 3145 IC_UFM_SCL_LOW_COUNT .............. 0x0008 3146 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 3147 IC_TX_TL .......................... 0x0 3148 IC_TX_CMD_BLOCK ................... 0x1 3149 IC_HAS_DMA ........................ 0x1 3150 IC_HAS_ASYNC_FIFO ................. 0x0 3151 IC_SMBUS_ARP ...................... 0x0 3152 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 3153 IC_INTR_IO ........................ 0x1 3154 IC_MASTER_MODE .................... 0x1 3155 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 3156 IC_INTR_POL ....................... 0x1 3157 IC_OPTIONAL_SAR ................... 0x0 3158 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 3159 IC_DEFAULT_SLAVE_ADDR ............. 0x055 3160 IC_DEFAULT_HS_SPKLEN .............. 0x1 3161 IC_FS_SCL_HIGH_COUNT .............. 0x0006 3162 IC_HS_SCL_LOW_COUNT ............... 0x0008 3163 IC_DEVICE_ID_VALUE ................ 0x0 3164 IC_10BITADDR_MASTER ............... 0x0 3165 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 3166 IC_DEFAULT_FS_SPKLEN .............. 0x7 3167 IC_ADD_ENCODED_PARAMS ............. 0x0 3168 IC_DEFAULT_SDA_HOLD ............... 0x000001 3169 IC_DEFAULT_SDA_SETUP .............. 0x64 3170 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 3171 IC_CLOCK_PERIOD ................... 100 3172 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 3173 IC_RESTART_EN ..................... 0x1 3174 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 3175 IC_BUS_CLEAR_FEATURE .............. 0x0 3176 IC_CAP_LOADING .................... 100 3177 IC_FS_SCL_LOW_COUNT ............... 0x000d 3178 APB_DATA_WIDTH .................... 32 3179 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff 3180 IC_SLV_DATA_NACK_ONLY ............. 0x1 3181 IC_10BITADDR_SLAVE ................ 0x0 3182 IC_CLK_TYPE ....................... 0x0 3183 IC_SMBUS_UDID_MSB ................. 0x0 3184 IC_SMBUS_SUSPEND_ALERT ............ 0x0 3185 IC_HS_SCL_HIGH_COUNT .............. 0x0006 3186 IC_SLV_RESTART_DET_EN ............. 0x1 3187 IC_SMBUS .......................... 0x0 3188 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 3189 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 3190 IC_USE_COUNTS ..................... 0x0 3191 IC_RX_BUFFER_DEPTH ................ 16 3192 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff 3193 IC_RX_FULL_HLD_BUS_EN ............. 0x1 3194 IC_SLAVE_DISABLE .................. 0x1 3195 IC_RX_TL .......................... 0x0 3196 IC_DEVICE_ID ...................... 0x0 3197 IC_HC_COUNT_VALUES ................ 0x0 3198 I2C_DYNAMIC_TAR_UPDATE ............ 0 3199 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff 3200 IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff 3201 IC_HS_MASTER_CODE ................. 0x1 3202 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff 3203 IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff 3204 IC_SS_SCL_HIGH_COUNT .............. 0x0028 3205 IC_SS_SCL_LOW_COUNT ............... 0x002f 3206 IC_MAX_SPEED_MODE ................. 0x2 3207 IC_STAT_FOR_CLK_STRETCH ........... 0x0 3208 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 3209 IC_DEFAULT_UFM_SPKLEN ............. 0x1 3210 IC_TX_BUFFER_DEPTH ................ 16 (I2C0) 3211 */ 3212 3213 typedef struct { /*!< I2C0 Structure */ 3214 __IOM uint32_t IC_CON; /*!< I2C Control Register. This register can be written only when 3215 the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] 3216 register being set to 0. Writes at other times have no 3217 effect. Read/Write Access: - bit 10 is read only. - bit 3218 11 is read only - bit 16 is read only - bit 17 is read 3219 only - bits 18 and 19 are read only. */ 3220 __IOM uint32_t IC_TAR; /*!< I2C Target Address Register This register is 12 bits wide, and 3221 bits 31:12 are reserved. This register can be written to 3222 only when IC_ENABLE[0] is set to 0. Note: If the software 3223 or application is aware that the DW_apb_i2c is not using 3224 the TAR address for the pending commands in the Tx FIFO, 3225 then it is possible to update the TAR address even while 3226 the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not 3227 necessary to perform any write to this register if DW_apb_i2c 3228 is enabled as an I2C slave only. */ 3229 __IOM uint32_t IC_SAR; /*!< I2C Slave Address Register */ 3230 __IM uint32_t RESERVED; 3231 __IOM uint32_t IC_DATA_CMD; /*!< I2C Rx/Tx Data Buffer and Command Register; this is the register 3232 the CPU writes to when filling the TX FIFO and the CPU 3233 reads from when retrieving bytes from RX FIFO. The size 3234 of the register changes as follows: Write: - 11 bits when 3235 IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 3236 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 3237 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order 3238 for the DW_apb_i2c to continue acknowledging reads, a read 3239 command should be written for every byte that is to be 3240 received; otherwise the DW_apb_i2c will stop acknowledging. */ 3241 __IOM uint32_t IC_SS_SCL_HCNT; /*!< Standard Speed I2C Clock SCL High Count Register */ 3242 __IOM uint32_t IC_SS_SCL_LCNT; /*!< Standard Speed I2C Clock SCL Low Count Register */ 3243 __IOM uint32_t IC_FS_SCL_HCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ 3244 __IOM uint32_t IC_FS_SCL_LCNT; /*!< Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ 3245 __IM uint32_t RESERVED1[2]; 3246 __IOM uint32_t IC_INTR_STAT; /*!< I2C Interrupt Status Register Each bit in this register has 3247 a corresponding mask bit in the IC_INTR_MASK register. 3248 These bits are cleared by reading the matching interrupt 3249 clear register. The unmasked raw versions of these bits 3250 are available in the IC_RAW_INTR_STAT register. */ 3251 __IOM uint32_t IC_INTR_MASK; /*!< I2C Interrupt Mask Register. These bits mask their corresponding 3252 interrupt status bits. This register is active low; a value 3253 of 0 masks the interrupt, whereas a value of 1 unmasks 3254 the interrupt. */ 3255 __IOM uint32_t IC_RAW_INTR_STAT; /*!< I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, 3256 these bits are not masked so they always show the true 3257 status of the DW_apb_i2c. */ 3258 __IOM uint32_t IC_RX_TL; /*!< I2C Receive FIFO Threshold Register */ 3259 __IOM uint32_t IC_TX_TL; /*!< I2C Transmit FIFO Threshold Register */ 3260 __IOM uint32_t IC_CLR_INTR; /*!< Clear Combined and Individual Interrupt Register */ 3261 __IOM uint32_t IC_CLR_RX_UNDER; /*!< Clear RX_UNDER Interrupt Register */ 3262 __IOM uint32_t IC_CLR_RX_OVER; /*!< Clear RX_OVER Interrupt Register */ 3263 __IOM uint32_t IC_CLR_TX_OVER; /*!< Clear TX_OVER Interrupt Register */ 3264 __IOM uint32_t IC_CLR_RD_REQ; /*!< Clear RD_REQ Interrupt Register */ 3265 __IOM uint32_t IC_CLR_TX_ABRT; /*!< Clear TX_ABRT Interrupt Register */ 3266 __IOM uint32_t IC_CLR_RX_DONE; /*!< Clear RX_DONE Interrupt Register */ 3267 __IOM uint32_t IC_CLR_ACTIVITY; /*!< Clear ACTIVITY Interrupt Register */ 3268 __IOM uint32_t IC_CLR_STOP_DET; /*!< Clear STOP_DET Interrupt Register */ 3269 __IOM uint32_t IC_CLR_START_DET; /*!< Clear START_DET Interrupt Register */ 3270 __IOM uint32_t IC_CLR_GEN_CALL; /*!< Clear GEN_CALL Interrupt Register */ 3271 __IOM uint32_t IC_ENABLE; /*!< I2C Enable Register */ 3272 __IOM uint32_t IC_STATUS; /*!< I2C Status Register This is a read-only register used to indicate 3273 the current transfer status and FIFO status. The status 3274 register may be read at any time. None of the bits in this 3275 register request an interrupt. When the I2C is disabled 3276 by writing 0 in bit 0 of the IC_ENABLE register: - Bits 3277 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When 3278 the master or slave state machines goes to idle and ic_en=0: 3279 - Bits 5 and 6 are set to 0 */ 3280 __IOM uint32_t IC_TXFLR; /*!< I2C Transmit FIFO Level Register This register contains the 3281 number of valid data entries in the transmit FIFO buffer. 3282 It is cleared whenever: - The I2C is disabled - There is 3283 a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT 3284 register - The slave bulk transmit mode is aborted The 3285 register increments whenever data is placed into the transmit 3286 FIFO and decrements when data is taken from the transmit 3287 FIFO. */ 3288 __IOM uint32_t IC_RXFLR; /*!< I2C Receive FIFO Level Register This register contains the number 3289 of valid data entries in the receive FIFO buffer. It is 3290 cleared whenever: - The I2C is disabled - Whenever there 3291 is a transmit abort caused by any of the events tracked 3292 in IC_TX_ABRT_SOURCE The register increments whenever data 3293 is placed into the receive FIFO and decrements when data 3294 is taken from the receive FIFO. */ 3295 __IOM uint32_t IC_SDA_HOLD; /*!< I2C SDA Hold Time Length Register The bits [15:0] of this register 3296 are used to control the hold time of SDA during transmit 3297 in both slave and master mode (after SCL goes from HIGH 3298 to LOW). The bits [23:16] of this register are used to 3299 extend the SDA transition (if any) whenever SCL is HIGH 3300 in the receiver in either master or slave mode. Writes 3301 to this register succeed only when IC_ENABLE[0]=0. The 3302 values in this register are in units of ic_clk period. 3303 The value programmed in IC_SDA_TX_HOLD must be greater 3304 than the minimum hold time in each mode (one cycle in master 3305 mode, seven cycles in slave mode) for the value to be implemented. 3306 The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) 3307 cannot exceed at any time the duration of the low part 3308 of scl. Therefore the programmed value cannot be larger 3309 than N_SCL_LOW-2, where N_SCL_LOW is the duration of the 3310 low part of the scl period measured in ic_clk cycles. */ 3311 __IOM uint32_t IC_TX_ABRT_SOURCE; /*!< I2C Transmit Abort Source Register This register has 32 bits 3312 that indicate the source of the TX_ABRT bit. Except for 3313 Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT 3314 register or the IC_CLR_INTR register is read. To clear 3315 Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed 3316 first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL 3317 bit must be cleared (IC_TAR[11]), or the GC_OR_START bit 3318 must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT 3319 is fixed, then this bit can be cleared in the same manner 3320 as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT 3321 is not fixed before attempting to clear this bit, Bit 9 3322 clears for one cycle and is then re-asserted. */ 3323 __IOM uint32_t IC_SLV_DATA_NACK_ONLY; /*!< Generate Slave Data NACK Register The register is used to generate 3324 a NACK for the data part of a transfer when DW_apb_i2c 3325 is acting as a slave-receiver. This register only exists 3326 when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When 3327 this parameter disabled, this register does not exist and 3328 writing to the register's address has no effect. A write 3329 can occur on this register if both of the following conditions 3330 are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - 3331 Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] 3332 is a register read-back location for the internal slv_activity 3333 signal; the user should poll this before writing the ic_slv_data_nack_onl 3334 bit. */ 3335 __IOM uint32_t IC_DMA_CR; /*!< DMA Control Register The register is used to enable the DMA 3336 Controller interface operation. There is a separate bit 3337 for transmit and receive. This can be programmed regardless 3338 of the state of IC_ENABLE. */ 3339 __IOM uint32_t IC_DMA_TDLR; /*!< DMA Transmit Data Level Register */ 3340 __IOM uint32_t IC_DMA_RDLR; /*!< I2C Receive Data Level Register */ 3341 __IOM uint32_t IC_SDA_SETUP; /*!< I2C SDA Setup Register This register controls the amount of 3342 time delay (in terms of number of ic_clk clock periods) 3343 introduced in the rising edge of SCL - relative to SDA 3344 changing - when DW_apb_i2c services a read request in a 3345 slave-transmitter operation. The relevant I2C requirement 3346 is tSU:DAT (note 4) as detailed in the I2C Bus Specification. 3347 This register must be programmed with a value equal to 3348 or greater than 2. Writes to this register succeed only 3349 when IC_ENABLE[0] = 0. Note: The length of setup time is 3350 calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], 3351 so if the user requires 10 ic_clk periods of setup time, 3352 they should program a value of 11. The IC_SDA_SETUP register 3353 is only used by the DW_apb_i2c when operating as a slave 3354 transmitter. */ 3355 __IOM uint32_t IC_ACK_GENERAL_CALL; /*!< I2C ACK General Call Register The register controls whether 3356 DW_apb_i2c responds with a ACK or NACK when it receives 3357 an I2C General Call address. This register is applicable 3358 only when the DW_apb_i2c is in slave mode. */ 3359 __IOM uint32_t IC_ENABLE_STATUS; /*!< I2C Enable Status Register The register is used to report the 3360 DW_apb_i2c hardware status when the IC_ENABLE[0] register 3361 is set from 1 to 0; that is, when DW_apb_i2c is disabled. 3362 If IC_ENABLE[0] has been set to 1, bits 2:1 are forced 3363 to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been 3364 set to 0, bits 2:1 is only be valid as soon as bit 0 is 3365 read as '0'. Note: When IC_ENABLE[0] has been set to 0, 3366 a delay occurs for bit 0 to be read as 0 because disabling 3367 the DW_apb_i2c depends on I2C bus activities. */ 3368 __IOM uint32_t IC_FS_SPKLEN; /*!< I2C SS, FS or FM+ spike suppression limit This register is used 3369 to store the duration, measured in ic_clk cycles, of the 3370 longest spike that is filtered out by the spike suppression 3371 logic when the component is operating in SS, FS or FM+ 3372 modes. The relevant I2C requirement is tSP (table 4) as 3373 detailed in the I2C Bus Specification. This register must 3374 be programmed with a minimum value of 1. */ 3375 __IM uint32_t RESERVED2; 3376 __IOM uint32_t IC_CLR_RESTART_DET; /*!< Clear RESTART_DET Interrupt Register */ 3377 __IM uint32_t RESERVED3[18]; 3378 __IOM uint32_t IC_COMP_PARAM_1; /*!< Component Parameter Register 1 Note This register is not implemented 3379 and therefore reads as 0. If it was implemented it would 3380 be a constant read-only register that contains encoded 3381 information about the component's parameter settings. Fields 3382 shown below are the settings for those parameters */ 3383 __IOM uint32_t IC_COMP_VERSION; /*!< I2C Component Version Register */ 3384 __IOM uint32_t IC_COMP_TYPE; /*!< I2C Component Type Register */ 3385 } I2C0_Type; /*!< Size = 256 (0x100) */ 3386 3387 3388 3389 /* =========================================================================================================================== */ 3390 /* ================ SPI0 ================ */ 3391 /* =========================================================================================================================== */ 3392 3393 3394 /** 3395 * @brief SPI0 (SPI0) 3396 */ 3397 3398 typedef struct { /*!< SPI0 Structure */ 3399 __IOM uint32_t SSPCR0; /*!< Control register 0, SSPCR0 on page 3-4 */ 3400 __IOM uint32_t SSPCR1; /*!< Control register 1, SSPCR1 on page 3-5 */ 3401 __IOM uint32_t SSPDR; /*!< Data register, SSPDR on page 3-6 */ 3402 __IOM uint32_t SSPSR; /*!< Status register, SSPSR on page 3-7 */ 3403 __IOM uint32_t SSPCPSR; /*!< Clock prescale register, SSPCPSR on page 3-8 */ 3404 __IOM uint32_t SSPIMSC; /*!< Interrupt mask set or clear register, SSPIMSC on page 3-9 */ 3405 __IOM uint32_t SSPRIS; /*!< Raw interrupt status register, SSPRIS on page 3-10 */ 3406 __IOM uint32_t SSPMIS; /*!< Masked interrupt status register, SSPMIS on page 3-11 */ 3407 __IOM uint32_t SSPICR; /*!< Interrupt clear register, SSPICR on page 3-11 */ 3408 __IOM uint32_t SSPDMACR; /*!< DMA control register, SSPDMACR on page 3-12 */ 3409 __IM uint32_t RESERVED[1006]; 3410 __IOM uint32_t SSPPERIPHID0; /*!< Peripheral identification registers, SSPPeriphID0-3 on page 3411 3-13 */ 3412 __IOM uint32_t SSPPERIPHID1; /*!< Peripheral identification registers, SSPPeriphID0-3 on page 3413 3-13 */ 3414 __IOM uint32_t SSPPERIPHID2; /*!< Peripheral identification registers, SSPPeriphID0-3 on page 3415 3-13 */ 3416 __IOM uint32_t SSPPERIPHID3; /*!< Peripheral identification registers, SSPPeriphID0-3 on page 3417 3-13 */ 3418 __IOM uint32_t SSPPCELLID0; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ 3419 __IOM uint32_t SSPPCELLID1; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ 3420 __IOM uint32_t SSPPCELLID2; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ 3421 __IOM uint32_t SSPPCELLID3; /*!< PrimeCell identification registers, SSPPCellID0-3 on page 3-16 */ 3422 } SPI0_Type; /*!< Size = 4096 (0x1000) */ 3423 3424 3425 3426 /* =========================================================================================================================== */ 3427 /* ================ PIO0 ================ */ 3428 /* =========================================================================================================================== */ 3429 3430 3431 /** 3432 * @brief Programmable IO block (PIO0) 3433 */ 3434 3435 typedef struct { /*!< PIO0 Structure */ 3436 __IOM uint32_t CTRL; /*!< PIO control register */ 3437 __IOM uint32_t FSTAT; /*!< FIFO status register */ 3438 __IOM uint32_t FDEBUG; /*!< FIFO debug register */ 3439 __IOM uint32_t FLEVEL; /*!< FIFO levels */ 3440 __IOM uint32_t TXF0; /*!< Direct write access to the TX FIFO for this state machine. Each 3441 write pushes one word to the FIFO. Attempting to write 3442 to a full FIFO has no effect on the FIFO state or contents, 3443 and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ 3444 __IOM uint32_t TXF1; /*!< Direct write access to the TX FIFO for this state machine. Each 3445 write pushes one word to the FIFO. Attempting to write 3446 to a full FIFO has no effect on the FIFO state or contents, 3447 and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ 3448 __IOM uint32_t TXF2; /*!< Direct write access to the TX FIFO for this state machine. Each 3449 write pushes one word to the FIFO. Attempting to write 3450 to a full FIFO has no effect on the FIFO state or contents, 3451 and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ 3452 __IOM uint32_t TXF3; /*!< Direct write access to the TX FIFO for this state machine. Each 3453 write pushes one word to the FIFO. Attempting to write 3454 to a full FIFO has no effect on the FIFO state or contents, 3455 and sets the sticky FDEBUG_TXOVER error flag for this FIFO. */ 3456 __IOM uint32_t RXF0; /*!< Direct read access to the RX FIFO for this state machine. Each 3457 read pops one word from the FIFO. Attempting to read from 3458 an empty FIFO has no effect on the FIFO state, and sets 3459 the sticky FDEBUG_RXUNDER error flag for this FIFO. The 3460 data returned to the system on a read from an empty FIFO 3461 is undefined. */ 3462 __IOM uint32_t RXF1; /*!< Direct read access to the RX FIFO for this state machine. Each 3463 read pops one word from the FIFO. Attempting to read from 3464 an empty FIFO has no effect on the FIFO state, and sets 3465 the sticky FDEBUG_RXUNDER error flag for this FIFO. The 3466 data returned to the system on a read from an empty FIFO 3467 is undefined. */ 3468 __IOM uint32_t RXF2; /*!< Direct read access to the RX FIFO for this state machine. Each 3469 read pops one word from the FIFO. Attempting to read from 3470 an empty FIFO has no effect on the FIFO state, and sets 3471 the sticky FDEBUG_RXUNDER error flag for this FIFO. The 3472 data returned to the system on a read from an empty FIFO 3473 is undefined. */ 3474 __IOM uint32_t RXF3; /*!< Direct read access to the RX FIFO for this state machine. Each 3475 read pops one word from the FIFO. Attempting to read from 3476 an empty FIFO has no effect on the FIFO state, and sets 3477 the sticky FDEBUG_RXUNDER error flag for this FIFO. The 3478 data returned to the system on a read from an empty FIFO 3479 is undefined. */ 3480 __IOM uint32_t IRQ; /*!< State machine IRQ flags register. Write 1 to clear. There are 3481 eight state machine IRQ flags, which can be set, cleared, 3482 and waited on by the state machines. There's no fixed association 3483 between flags and state machines -- any state machine can 3484 use any flag. Any of the eight flags can be used for timing 3485 synchronisation between state machines, using IRQ and WAIT 3486 instructions. Any combination of the eight flags can also 3487 routed out to either of the two system-level interrupt 3488 requests, alongside FIFO status interrupts -- see e.g. 3489 IRQ0_INTE. */ 3490 __IOM uint32_t IRQ_FORCE; /*!< Writing a 1 to each of these bits will forcibly assert the corresponding 3491 IRQ. Note this is different to the INTF register: writing 3492 here affects PIO internal state. INTF just asserts the 3493 processor-facing IRQ signal for testing ISRs, and is not 3494 visible to the state machines. */ 3495 __IOM uint32_t INPUT_SYNC_BYPASS; /*!< There is a 2-flipflop synchronizer on each GPIO input, which 3496 protects PIO logic from metastabilities. This increases 3497 input delay, and for fast synchronous IO (e.g. SPI) these 3498 synchronizers may need to be bypassed. Each bit in this 3499 register corresponds to one GPIO. 0 -> input is synchronized 3500 (default) 1 -> synchronizer is bypassed If in doubt, leave 3501 this register as all zeroes. */ 3502 __IOM uint32_t DBG_PADOUT; /*!< Read to sample the pad output values PIO is currently driving 3503 to the GPIOs. On RP2040 there are 30 GPIOs, so the two 3504 most significant bits are hardwired to 0. */ 3505 __IOM uint32_t DBG_PADOE; /*!< Read to sample the pad output enables (direction) PIO is currently 3506 driving to the GPIOs. On RP2040 there are 30 GPIOs, so 3507 the two most significant bits are hardwired to 0. */ 3508 __IOM uint32_t DBG_CFGINFO; /*!< The PIO hardware has some free parameters that may vary between 3509 chip products. These should be provided in the chip datasheet, 3510 but are also exposed here. */ 3511 __IOM uint32_t INSTR_MEM0; /*!< Write-only access to instruction memory location 0 */ 3512 __IOM uint32_t INSTR_MEM1; /*!< Write-only access to instruction memory location 1 */ 3513 __IOM uint32_t INSTR_MEM2; /*!< Write-only access to instruction memory location 2 */ 3514 __IOM uint32_t INSTR_MEM3; /*!< Write-only access to instruction memory location 3 */ 3515 __IOM uint32_t INSTR_MEM4; /*!< Write-only access to instruction memory location 4 */ 3516 __IOM uint32_t INSTR_MEM5; /*!< Write-only access to instruction memory location 5 */ 3517 __IOM uint32_t INSTR_MEM6; /*!< Write-only access to instruction memory location 6 */ 3518 __IOM uint32_t INSTR_MEM7; /*!< Write-only access to instruction memory location 7 */ 3519 __IOM uint32_t INSTR_MEM8; /*!< Write-only access to instruction memory location 8 */ 3520 __IOM uint32_t INSTR_MEM9; /*!< Write-only access to instruction memory location 9 */ 3521 __IOM uint32_t INSTR_MEM10; /*!< Write-only access to instruction memory location 10 */ 3522 __IOM uint32_t INSTR_MEM11; /*!< Write-only access to instruction memory location 11 */ 3523 __IOM uint32_t INSTR_MEM12; /*!< Write-only access to instruction memory location 12 */ 3524 __IOM uint32_t INSTR_MEM13; /*!< Write-only access to instruction memory location 13 */ 3525 __IOM uint32_t INSTR_MEM14; /*!< Write-only access to instruction memory location 14 */ 3526 __IOM uint32_t INSTR_MEM15; /*!< Write-only access to instruction memory location 15 */ 3527 __IOM uint32_t INSTR_MEM16; /*!< Write-only access to instruction memory location 16 */ 3528 __IOM uint32_t INSTR_MEM17; /*!< Write-only access to instruction memory location 17 */ 3529 __IOM uint32_t INSTR_MEM18; /*!< Write-only access to instruction memory location 18 */ 3530 __IOM uint32_t INSTR_MEM19; /*!< Write-only access to instruction memory location 19 */ 3531 __IOM uint32_t INSTR_MEM20; /*!< Write-only access to instruction memory location 20 */ 3532 __IOM uint32_t INSTR_MEM21; /*!< Write-only access to instruction memory location 21 */ 3533 __IOM uint32_t INSTR_MEM22; /*!< Write-only access to instruction memory location 22 */ 3534 __IOM uint32_t INSTR_MEM23; /*!< Write-only access to instruction memory location 23 */ 3535 __IOM uint32_t INSTR_MEM24; /*!< Write-only access to instruction memory location 24 */ 3536 __IOM uint32_t INSTR_MEM25; /*!< Write-only access to instruction memory location 25 */ 3537 __IOM uint32_t INSTR_MEM26; /*!< Write-only access to instruction memory location 26 */ 3538 __IOM uint32_t INSTR_MEM27; /*!< Write-only access to instruction memory location 27 */ 3539 __IOM uint32_t INSTR_MEM28; /*!< Write-only access to instruction memory location 28 */ 3540 __IOM uint32_t INSTR_MEM29; /*!< Write-only access to instruction memory location 29 */ 3541 __IOM uint32_t INSTR_MEM30; /*!< Write-only access to instruction memory location 30 */ 3542 __IOM uint32_t INSTR_MEM31; /*!< Write-only access to instruction memory location 31 */ 3543 __IOM uint32_t SM0_CLKDIV; /*!< Clock divisor register for state machine 0 Frequency = clock 3544 freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ 3545 __IOM uint32_t SM0_EXECCTRL; /*!< Execution/behavioural settings for state machine 0 */ 3546 __IOM uint32_t SM0_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state 3547 machine 0 */ 3548 __IOM uint32_t SM0_ADDR; /*!< Current instruction address of state machine 0 */ 3549 __IOM uint32_t SM0_INSTR; /*!< Read to see the instruction currently addressed by state machine 3550 0's program counter Write to execute an instruction immediately 3551 (including jumps) and then resume execution. */ 3552 __IOM uint32_t SM0_PINCTRL; /*!< State machine pin control */ 3553 __IOM uint32_t SM1_CLKDIV; /*!< Clock divisor register for state machine 1 Frequency = clock 3554 freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ 3555 __IOM uint32_t SM1_EXECCTRL; /*!< Execution/behavioural settings for state machine 1 */ 3556 __IOM uint32_t SM1_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state 3557 machine 1 */ 3558 __IOM uint32_t SM1_ADDR; /*!< Current instruction address of state machine 1 */ 3559 __IOM uint32_t SM1_INSTR; /*!< Read to see the instruction currently addressed by state machine 3560 1's program counter Write to execute an instruction immediately 3561 (including jumps) and then resume execution. */ 3562 __IOM uint32_t SM1_PINCTRL; /*!< State machine pin control */ 3563 __IOM uint32_t SM2_CLKDIV; /*!< Clock divisor register for state machine 2 Frequency = clock 3564 freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ 3565 __IOM uint32_t SM2_EXECCTRL; /*!< Execution/behavioural settings for state machine 2 */ 3566 __IOM uint32_t SM2_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state 3567 machine 2 */ 3568 __IOM uint32_t SM2_ADDR; /*!< Current instruction address of state machine 2 */ 3569 __IOM uint32_t SM2_INSTR; /*!< Read to see the instruction currently addressed by state machine 3570 2's program counter Write to execute an instruction immediately 3571 (including jumps) and then resume execution. */ 3572 __IOM uint32_t SM2_PINCTRL; /*!< State machine pin control */ 3573 __IOM uint32_t SM3_CLKDIV; /*!< Clock divisor register for state machine 3 Frequency = clock 3574 freq / (CLKDIV_INT + CLKDIV_FRAC / 256) */ 3575 __IOM uint32_t SM3_EXECCTRL; /*!< Execution/behavioural settings for state machine 3 */ 3576 __IOM uint32_t SM3_SHIFTCTRL; /*!< Control behaviour of the input/output shift registers for state 3577 machine 3 */ 3578 __IOM uint32_t SM3_ADDR; /*!< Current instruction address of state machine 3 */ 3579 __IOM uint32_t SM3_INSTR; /*!< Read to see the instruction currently addressed by state machine 3580 3's program counter Write to execute an instruction immediately 3581 (including jumps) and then resume execution. */ 3582 __IOM uint32_t SM3_PINCTRL; /*!< State machine pin control */ 3583 __IOM uint32_t RXF0_PUTGET0; /*!< Direct read/write access to entry 0 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3584 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3585 __IOM uint32_t RXF0_PUTGET1; /*!< Direct read/write access to entry 1 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3586 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3587 __IOM uint32_t RXF0_PUTGET2; /*!< Direct read/write access to entry 2 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3588 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3589 __IOM uint32_t RXF0_PUTGET3; /*!< Direct read/write access to entry 3 of SM0's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3590 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3591 __IOM uint32_t RXF1_PUTGET0; /*!< Direct read/write access to entry 0 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3592 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3593 __IOM uint32_t RXF1_PUTGET1; /*!< Direct read/write access to entry 1 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3594 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3595 __IOM uint32_t RXF1_PUTGET2; /*!< Direct read/write access to entry 2 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3596 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3597 __IOM uint32_t RXF1_PUTGET3; /*!< Direct read/write access to entry 3 of SM1's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3598 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3599 __IOM uint32_t RXF2_PUTGET0; /*!< Direct read/write access to entry 0 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3600 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3601 __IOM uint32_t RXF2_PUTGET1; /*!< Direct read/write access to entry 1 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3602 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3603 __IOM uint32_t RXF2_PUTGET2; /*!< Direct read/write access to entry 2 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3604 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3605 __IOM uint32_t RXF2_PUTGET3; /*!< Direct read/write access to entry 3 of SM2's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3606 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3607 __IOM uint32_t RXF3_PUTGET0; /*!< Direct read/write access to entry 0 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3608 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3609 __IOM uint32_t RXF3_PUTGET1; /*!< Direct read/write access to entry 1 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3610 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3611 __IOM uint32_t RXF3_PUTGET2; /*!< Direct read/write access to entry 2 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3612 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3613 __IOM uint32_t RXF3_PUTGET3; /*!< Direct read/write access to entry 3 of SM3's RX FIFO, if SHIFTCTRL_FJOIN_RX_PU 3614 xor SHIFTCTRL_FJOIN_RX_GET is set. */ 3615 __IOM uint32_t GPIOBASE; /*!< Relocate GPIO 0 (from PIO's point of view) in the system GPIO 3616 numbering, to access more than 32 GPIOs from PIO. Only 3617 the values 0 and 16 are supported (only bit 4 is writable). */ 3618 __IOM uint32_t INTR; /*!< Raw Interrupts */ 3619 __IOM uint32_t IRQ0_INTE; /*!< Interrupt Enable for irq0 */ 3620 __IOM uint32_t IRQ0_INTF; /*!< Interrupt Force for irq0 */ 3621 __IOM uint32_t IRQ0_INTS; /*!< Interrupt status after masking & forcing for irq0 */ 3622 __IOM uint32_t IRQ1_INTE; /*!< Interrupt Enable for irq1 */ 3623 __IOM uint32_t IRQ1_INTF; /*!< Interrupt Force for irq1 */ 3624 __IOM uint32_t IRQ1_INTS; /*!< Interrupt status after masking & forcing for irq1 */ 3625 } PIO0_Type; /*!< Size = 392 (0x188) */ 3626 3627 3628 3629 /* =========================================================================================================================== */ 3630 /* ================ BUSCTRL ================ */ 3631 /* =========================================================================================================================== */ 3632 3633 3634 /** 3635 * @brief Register block for busfabric control signals and performance counters (BUSCTRL) 3636 */ 3637 3638 typedef struct { /*!< BUSCTRL Structure */ 3639 __IOM uint32_t BUS_PRIORITY; /*!< Set the priority of each master for bus arbitration. */ 3640 __IOM uint32_t BUS_PRIORITY_ACK; /*!< Bus priority acknowledge */ 3641 __IOM uint32_t PERFCTR_EN; /*!< Enable the performance counters. If 0, the performance counters 3642 do not increment. This can be used to precisely start/stop 3643 event sampling around the profiled section of code. The 3644 performance counters are initially disabled, to save energy. */ 3645 __IOM uint32_t PERFCTR0; /*!< Bus fabric performance counter 0 */ 3646 __IOM uint32_t PERFSEL0; /*!< Bus fabric performance event select for PERFCTR0 */ 3647 __IOM uint32_t PERFCTR1; /*!< Bus fabric performance counter 1 */ 3648 __IOM uint32_t PERFSEL1; /*!< Bus fabric performance event select for PERFCTR1 */ 3649 __IOM uint32_t PERFCTR2; /*!< Bus fabric performance counter 2 */ 3650 __IOM uint32_t PERFSEL2; /*!< Bus fabric performance event select for PERFCTR2 */ 3651 __IOM uint32_t PERFCTR3; /*!< Bus fabric performance counter 3 */ 3652 __IOM uint32_t PERFSEL3; /*!< Bus fabric performance event select for PERFCTR3 */ 3653 } BUSCTRL_Type; /*!< Size = 44 (0x2c) */ 3654 3655 3656 3657 /* =========================================================================================================================== */ 3658 /* ================ SIO ================ */ 3659 /* =========================================================================================================================== */ 3660 3661 3662 /** 3663 * @brief Single-cycle IO block 3664 Provides core-local and inter-core hardware for the two processors, with single-cycle access. (SIO) 3665 */ 3666 3667 typedef struct { /*!< SIO Structure */ 3668 __IOM uint32_t CPUID; /*!< Processor core identifier */ 3669 __IOM uint32_t GPIO_IN; /*!< Input value for GPIO0...31. In the Non-secure SIO, Secure-only 3670 GPIOs (as per ACCESSCTRL) appear as zero. */ 3671 __IOM uint32_t GPIO_HI_IN; /*!< Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure 3672 SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero. */ 3673 __IM uint32_t RESERVED; 3674 __IOM uint32_t GPIO_OUT; /*!< GPIO0...31 output value */ 3675 __IOM uint32_t GPIO_HI_OUT; /*!< Output value for GPIO32...47, QSPI IOs and USB pins. Write to 3676 set output level (1/0 -> high/low). Reading back gives 3677 the last value written, NOT the input value from the pins. 3678 If core 0 and core 1 both write to GPIO_HI_OUT simultaneously 3679 (or to a SET/CLR/XOR alias), the result is as though the 3680 write from core 0 took place first, and the write from 3681 core 1 was then applied to that intermediate result. In 3682 the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) 3683 ignore writes, and their output status reads back as zero. 3684 This is also true for SET/CLR/XOR aliases of this register. */ 3685 __IOM uint32_t GPIO_OUT_SET; /*!< GPIO0...31 output value set */ 3686 __IOM uint32_t GPIO_HI_OUT_SET; /*!< Output value set for GPIO32..47, QSPI IOs and USB pins. Perform 3687 an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= 3688 wdata` */ 3689 __IOM uint32_t GPIO_OUT_CLR; /*!< GPIO0...31 output value clear */ 3690 __IOM uint32_t GPIO_HI_OUT_CLR; /*!< Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform 3691 an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= 3692 ~wdata` */ 3693 __IOM uint32_t GPIO_OUT_XOR; /*!< GPIO0...31 output value XOR */ 3694 __IOM uint32_t GPIO_HI_OUT_XOR; /*!< Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform 3695 an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT 3696 ^= wdata` */ 3697 __IOM uint32_t GPIO_OE; /*!< GPIO0...31 output enable */ 3698 __IOM uint32_t GPIO_HI_OE; /*!< Output enable value for GPIO32...47, QSPI IOs and USB pins. 3699 Write output enable (1/0 -> output/input). Reading back 3700 gives the last value written. If core 0 and core 1 both 3701 write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR 3702 alias), the result is as though the write from core 0 took 3703 place first, and the write from core 1 was then applied 3704 to that intermediate result. In the Non-secure SIO, Secure-only 3705 GPIOs (as per ACCESSCTRL) ignore writes, and their output 3706 status reads back as zero. This is also true for SET/CLR/XOR 3707 aliases of this register. */ 3708 __IOM uint32_t GPIO_OE_SET; /*!< GPIO0...31 output enable set */ 3709 __IOM uint32_t GPIO_HI_OE_SET; /*!< Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform 3710 an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` */ 3711 __IOM uint32_t GPIO_OE_CLR; /*!< GPIO0...31 output enable clear */ 3712 __IOM uint32_t GPIO_HI_OE_CLR; /*!< Output enable clear for GPIO32...47, QSPI IOs and USB pins. 3713 Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE 3714 &= ~wdata` */ 3715 __IOM uint32_t GPIO_OE_XOR; /*!< GPIO0...31 output enable XOR */ 3716 __IOM uint32_t GPIO_HI_OE_XOR; /*!< Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform 3717 an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= 3718 wdata` */ 3719 __IOM uint32_t FIFO_ST; /*!< Status register for inter-core FIFOs (mailboxes). There is one 3720 FIFO in the core 0 -> core 1 direction, and one core 1 3721 -> core 0. Both are 32 bits wide and 8 words deep. Core 3722 0 can see the read side of the 1->0 FIFO (RX), and the 3723 write side of 0->1 FIFO (TX). Core 1 can see the read side 3724 of the 0->1 FIFO (RX), and the write side of 1->0 FIFO 3725 (TX). The SIO IRQ for each core is the logical OR of the 3726 VLD, WOF and ROE fields of its FIFO_ST register. */ 3727 __IOM uint32_t FIFO_WR; /*!< Write access to this core's TX FIFO */ 3728 __IOM uint32_t FIFO_RD; /*!< Read access to this core's RX FIFO */ 3729 __IOM uint32_t SPINLOCK_ST; /*!< Spinlock state A bitmap containing the state of all 32 spinlocks 3730 (1=locked). Mainly intended for debugging. */ 3731 __IM uint32_t RESERVED1[8]; 3732 __IOM uint32_t INTERP0_ACCUM0; /*!< Read/write access to accumulator 0 */ 3733 __IOM uint32_t INTERP0_ACCUM1; /*!< Read/write access to accumulator 1 */ 3734 __IOM uint32_t INTERP0_BASE0; /*!< Read/write access to BASE0 register. */ 3735 __IOM uint32_t INTERP0_BASE1; /*!< Read/write access to BASE1 register. */ 3736 __IOM uint32_t INTERP0_BASE2; /*!< Read/write access to BASE2 register. */ 3737 __IOM uint32_t INTERP0_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to 3738 both accumulators (POP). */ 3739 __IOM uint32_t INTERP0_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to 3740 both accumulators (POP). */ 3741 __IOM uint32_t INTERP0_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both 3742 accumulators (POP). */ 3743 __IOM uint32_t INTERP0_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ 3744 __IOM uint32_t INTERP0_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ 3745 __IOM uint32_t INTERP0_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ 3746 __IOM uint32_t INTERP0_CTRL_LANE0; /*!< Control register for lane 0 */ 3747 __IOM uint32_t INTERP0_CTRL_LANE1; /*!< Control register for lane 1 */ 3748 __IOM uint32_t INTERP0_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields 3749 lane 0's raw shift and mask value (BASE0 not added). */ 3750 __IOM uint32_t INTERP0_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields 3751 lane 1's raw shift and mask value (BASE1 not added). */ 3752 __IOM uint32_t INTERP0_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 3753 simultaneously. Each half is sign-extended to 32 bits if 3754 that lane's SIGNED flag is set. */ 3755 __IOM uint32_t INTERP1_ACCUM0; /*!< Read/write access to accumulator 0 */ 3756 __IOM uint32_t INTERP1_ACCUM1; /*!< Read/write access to accumulator 1 */ 3757 __IOM uint32_t INTERP1_BASE0; /*!< Read/write access to BASE0 register. */ 3758 __IOM uint32_t INTERP1_BASE1; /*!< Read/write access to BASE1 register. */ 3759 __IOM uint32_t INTERP1_BASE2; /*!< Read/write access to BASE2 register. */ 3760 __IOM uint32_t INTERP1_POP_LANE0; /*!< Read LANE0 result, and simultaneously write lane results to 3761 both accumulators (POP). */ 3762 __IOM uint32_t INTERP1_POP_LANE1; /*!< Read LANE1 result, and simultaneously write lane results to 3763 both accumulators (POP). */ 3764 __IOM uint32_t INTERP1_POP_FULL; /*!< Read FULL result, and simultaneously write lane results to both 3765 accumulators (POP). */ 3766 __IOM uint32_t INTERP1_PEEK_LANE0; /*!< Read LANE0 result, without altering any internal state (PEEK). */ 3767 __IOM uint32_t INTERP1_PEEK_LANE1; /*!< Read LANE1 result, without altering any internal state (PEEK). */ 3768 __IOM uint32_t INTERP1_PEEK_FULL; /*!< Read FULL result, without altering any internal state (PEEK). */ 3769 __IOM uint32_t INTERP1_CTRL_LANE0; /*!< Control register for lane 0 */ 3770 __IOM uint32_t INTERP1_CTRL_LANE1; /*!< Control register for lane 1 */ 3771 __IOM uint32_t INTERP1_ACCUM0_ADD; /*!< Values written here are atomically added to ACCUM0 Reading yields 3772 lane 0's raw shift and mask value (BASE0 not added). */ 3773 __IOM uint32_t INTERP1_ACCUM1_ADD; /*!< Values written here are atomically added to ACCUM1 Reading yields 3774 lane 1's raw shift and mask value (BASE1 not added). */ 3775 __IOM uint32_t INTERP1_BASE_1AND0; /*!< On write, the lower 16 bits go to BASE0, upper bits to BASE1 3776 simultaneously. Each half is sign-extended to 32 bits if 3777 that lane's SIGNED flag is set. */ 3778 __IOM uint32_t SPINLOCK0; /*!< Reading from a spinlock address will: - Return 0 if lock is 3779 already locked - Otherwise return nonzero, and simultaneously 3780 claim the lock Writing (any value) releases the lock. If 3781 core 0 and core 1 attempt to claim the same lock simultaneously, 3782 core 0 wins. The value returned on success is 0x1 << lock 3783 number. */ 3784 __IOM uint32_t SPINLOCK1; /*!< Reading from a spinlock address will: - Return 0 if lock is 3785 already locked - Otherwise return nonzero, and simultaneously 3786 claim the lock Writing (any value) releases the lock. If 3787 core 0 and core 1 attempt to claim the same lock simultaneously, 3788 core 0 wins. The value returned on success is 0x1 << lock 3789 number. */ 3790 __IOM uint32_t SPINLOCK2; /*!< Reading from a spinlock address will: - Return 0 if lock is 3791 already locked - Otherwise return nonzero, and simultaneously 3792 claim the lock Writing (any value) releases the lock. If 3793 core 0 and core 1 attempt to claim the same lock simultaneously, 3794 core 0 wins. The value returned on success is 0x1 << lock 3795 number. */ 3796 __IOM uint32_t SPINLOCK3; /*!< Reading from a spinlock address will: - Return 0 if lock is 3797 already locked - Otherwise return nonzero, and simultaneously 3798 claim the lock Writing (any value) releases the lock. If 3799 core 0 and core 1 attempt to claim the same lock simultaneously, 3800 core 0 wins. The value returned on success is 0x1 << lock 3801 number. */ 3802 __IOM uint32_t SPINLOCK4; /*!< Reading from a spinlock address will: - Return 0 if lock is 3803 already locked - Otherwise return nonzero, and simultaneously 3804 claim the lock Writing (any value) releases the lock. If 3805 core 0 and core 1 attempt to claim the same lock simultaneously, 3806 core 0 wins. The value returned on success is 0x1 << lock 3807 number. */ 3808 __IOM uint32_t SPINLOCK5; /*!< Reading from a spinlock address will: - Return 0 if lock is 3809 already locked - Otherwise return nonzero, and simultaneously 3810 claim the lock Writing (any value) releases the lock. If 3811 core 0 and core 1 attempt to claim the same lock simultaneously, 3812 core 0 wins. The value returned on success is 0x1 << lock 3813 number. */ 3814 __IOM uint32_t SPINLOCK6; /*!< Reading from a spinlock address will: - Return 0 if lock is 3815 already locked - Otherwise return nonzero, and simultaneously 3816 claim the lock Writing (any value) releases the lock. If 3817 core 0 and core 1 attempt to claim the same lock simultaneously, 3818 core 0 wins. The value returned on success is 0x1 << lock 3819 number. */ 3820 __IOM uint32_t SPINLOCK7; /*!< Reading from a spinlock address will: - Return 0 if lock is 3821 already locked - Otherwise return nonzero, and simultaneously 3822 claim the lock Writing (any value) releases the lock. If 3823 core 0 and core 1 attempt to claim the same lock simultaneously, 3824 core 0 wins. The value returned on success is 0x1 << lock 3825 number. */ 3826 __IOM uint32_t SPINLOCK8; /*!< Reading from a spinlock address will: - Return 0 if lock is 3827 already locked - Otherwise return nonzero, and simultaneously 3828 claim the lock Writing (any value) releases the lock. If 3829 core 0 and core 1 attempt to claim the same lock simultaneously, 3830 core 0 wins. The value returned on success is 0x1 << lock 3831 number. */ 3832 __IOM uint32_t SPINLOCK9; /*!< Reading from a spinlock address will: - Return 0 if lock is 3833 already locked - Otherwise return nonzero, and simultaneously 3834 claim the lock Writing (any value) releases the lock. If 3835 core 0 and core 1 attempt to claim the same lock simultaneously, 3836 core 0 wins. The value returned on success is 0x1 << lock 3837 number. */ 3838 __IOM uint32_t SPINLOCK10; /*!< Reading from a spinlock address will: - Return 0 if lock is 3839 already locked - Otherwise return nonzero, and simultaneously 3840 claim the lock Writing (any value) releases the lock. If 3841 core 0 and core 1 attempt to claim the same lock simultaneously, 3842 core 0 wins. The value returned on success is 0x1 << lock 3843 number. */ 3844 __IOM uint32_t SPINLOCK11; /*!< Reading from a spinlock address will: - Return 0 if lock is 3845 already locked - Otherwise return nonzero, and simultaneously 3846 claim the lock Writing (any value) releases the lock. If 3847 core 0 and core 1 attempt to claim the same lock simultaneously, 3848 core 0 wins. The value returned on success is 0x1 << lock 3849 number. */ 3850 __IOM uint32_t SPINLOCK12; /*!< Reading from a spinlock address will: - Return 0 if lock is 3851 already locked - Otherwise return nonzero, and simultaneously 3852 claim the lock Writing (any value) releases the lock. If 3853 core 0 and core 1 attempt to claim the same lock simultaneously, 3854 core 0 wins. The value returned on success is 0x1 << lock 3855 number. */ 3856 __IOM uint32_t SPINLOCK13; /*!< Reading from a spinlock address will: - Return 0 if lock is 3857 already locked - Otherwise return nonzero, and simultaneously 3858 claim the lock Writing (any value) releases the lock. If 3859 core 0 and core 1 attempt to claim the same lock simultaneously, 3860 core 0 wins. The value returned on success is 0x1 << lock 3861 number. */ 3862 __IOM uint32_t SPINLOCK14; /*!< Reading from a spinlock address will: - Return 0 if lock is 3863 already locked - Otherwise return nonzero, and simultaneously 3864 claim the lock Writing (any value) releases the lock. If 3865 core 0 and core 1 attempt to claim the same lock simultaneously, 3866 core 0 wins. The value returned on success is 0x1 << lock 3867 number. */ 3868 __IOM uint32_t SPINLOCK15; /*!< Reading from a spinlock address will: - Return 0 if lock is 3869 already locked - Otherwise return nonzero, and simultaneously 3870 claim the lock Writing (any value) releases the lock. If 3871 core 0 and core 1 attempt to claim the same lock simultaneously, 3872 core 0 wins. The value returned on success is 0x1 << lock 3873 number. */ 3874 __IOM uint32_t SPINLOCK16; /*!< Reading from a spinlock address will: - Return 0 if lock is 3875 already locked - Otherwise return nonzero, and simultaneously 3876 claim the lock Writing (any value) releases the lock. If 3877 core 0 and core 1 attempt to claim the same lock simultaneously, 3878 core 0 wins. The value returned on success is 0x1 << lock 3879 number. */ 3880 __IOM uint32_t SPINLOCK17; /*!< Reading from a spinlock address will: - Return 0 if lock is 3881 already locked - Otherwise return nonzero, and simultaneously 3882 claim the lock Writing (any value) releases the lock. If 3883 core 0 and core 1 attempt to claim the same lock simultaneously, 3884 core 0 wins. The value returned on success is 0x1 << lock 3885 number. */ 3886 __IOM uint32_t SPINLOCK18; /*!< Reading from a spinlock address will: - Return 0 if lock is 3887 already locked - Otherwise return nonzero, and simultaneously 3888 claim the lock Writing (any value) releases the lock. If 3889 core 0 and core 1 attempt to claim the same lock simultaneously, 3890 core 0 wins. The value returned on success is 0x1 << lock 3891 number. */ 3892 __IOM uint32_t SPINLOCK19; /*!< Reading from a spinlock address will: - Return 0 if lock is 3893 already locked - Otherwise return nonzero, and simultaneously 3894 claim the lock Writing (any value) releases the lock. If 3895 core 0 and core 1 attempt to claim the same lock simultaneously, 3896 core 0 wins. The value returned on success is 0x1 << lock 3897 number. */ 3898 __IOM uint32_t SPINLOCK20; /*!< Reading from a spinlock address will: - Return 0 if lock is 3899 already locked - Otherwise return nonzero, and simultaneously 3900 claim the lock Writing (any value) releases the lock. If 3901 core 0 and core 1 attempt to claim the same lock simultaneously, 3902 core 0 wins. The value returned on success is 0x1 << lock 3903 number. */ 3904 __IOM uint32_t SPINLOCK21; /*!< Reading from a spinlock address will: - Return 0 if lock is 3905 already locked - Otherwise return nonzero, and simultaneously 3906 claim the lock Writing (any value) releases the lock. If 3907 core 0 and core 1 attempt to claim the same lock simultaneously, 3908 core 0 wins. The value returned on success is 0x1 << lock 3909 number. */ 3910 __IOM uint32_t SPINLOCK22; /*!< Reading from a spinlock address will: - Return 0 if lock is 3911 already locked - Otherwise return nonzero, and simultaneously 3912 claim the lock Writing (any value) releases the lock. If 3913 core 0 and core 1 attempt to claim the same lock simultaneously, 3914 core 0 wins. The value returned on success is 0x1 << lock 3915 number. */ 3916 __IOM uint32_t SPINLOCK23; /*!< Reading from a spinlock address will: - Return 0 if lock is 3917 already locked - Otherwise return nonzero, and simultaneously 3918 claim the lock Writing (any value) releases the lock. If 3919 core 0 and core 1 attempt to claim the same lock simultaneously, 3920 core 0 wins. The value returned on success is 0x1 << lock 3921 number. */ 3922 __IOM uint32_t SPINLOCK24; /*!< Reading from a spinlock address will: - Return 0 if lock is 3923 already locked - Otherwise return nonzero, and simultaneously 3924 claim the lock Writing (any value) releases the lock. If 3925 core 0 and core 1 attempt to claim the same lock simultaneously, 3926 core 0 wins. The value returned on success is 0x1 << lock 3927 number. */ 3928 __IOM uint32_t SPINLOCK25; /*!< Reading from a spinlock address will: - Return 0 if lock is 3929 already locked - Otherwise return nonzero, and simultaneously 3930 claim the lock Writing (any value) releases the lock. If 3931 core 0 and core 1 attempt to claim the same lock simultaneously, 3932 core 0 wins. The value returned on success is 0x1 << lock 3933 number. */ 3934 __IOM uint32_t SPINLOCK26; /*!< Reading from a spinlock address will: - Return 0 if lock is 3935 already locked - Otherwise return nonzero, and simultaneously 3936 claim the lock Writing (any value) releases the lock. If 3937 core 0 and core 1 attempt to claim the same lock simultaneously, 3938 core 0 wins. The value returned on success is 0x1 << lock 3939 number. */ 3940 __IOM uint32_t SPINLOCK27; /*!< Reading from a spinlock address will: - Return 0 if lock is 3941 already locked - Otherwise return nonzero, and simultaneously 3942 claim the lock Writing (any value) releases the lock. If 3943 core 0 and core 1 attempt to claim the same lock simultaneously, 3944 core 0 wins. The value returned on success is 0x1 << lock 3945 number. */ 3946 __IOM uint32_t SPINLOCK28; /*!< Reading from a spinlock address will: - Return 0 if lock is 3947 already locked - Otherwise return nonzero, and simultaneously 3948 claim the lock Writing (any value) releases the lock. If 3949 core 0 and core 1 attempt to claim the same lock simultaneously, 3950 core 0 wins. The value returned on success is 0x1 << lock 3951 number. */ 3952 __IOM uint32_t SPINLOCK29; /*!< Reading from a spinlock address will: - Return 0 if lock is 3953 already locked - Otherwise return nonzero, and simultaneously 3954 claim the lock Writing (any value) releases the lock. If 3955 core 0 and core 1 attempt to claim the same lock simultaneously, 3956 core 0 wins. The value returned on success is 0x1 << lock 3957 number. */ 3958 __IOM uint32_t SPINLOCK30; /*!< Reading from a spinlock address will: - Return 0 if lock is 3959 already locked - Otherwise return nonzero, and simultaneously 3960 claim the lock Writing (any value) releases the lock. If 3961 core 0 and core 1 attempt to claim the same lock simultaneously, 3962 core 0 wins. The value returned on success is 0x1 << lock 3963 number. */ 3964 __IOM uint32_t SPINLOCK31; /*!< Reading from a spinlock address will: - Return 0 if lock is 3965 already locked - Otherwise return nonzero, and simultaneously 3966 claim the lock Writing (any value) releases the lock. If 3967 core 0 and core 1 attempt to claim the same lock simultaneously, 3968 core 0 wins. The value returned on success is 0x1 << lock 3969 number. */ 3970 __IOM uint32_t DOORBELL_OUT_SET; /*!< Trigger a doorbell interrupt on the opposite core. Write 1 to 3971 a bit to set the corresponding bit in DOORBELL_IN on the 3972 opposite core. This raises the opposite core's doorbell 3973 interrupt. Read to get the status of the doorbells currently 3974 asserted on the opposite core. This is equivalent to that 3975 core reading its own DOORBELL_IN status. */ 3976 __IOM uint32_t DOORBELL_OUT_CLR; /*!< Clear doorbells which have been posted to the opposite core. 3977 This register is intended for debugging and initialisation 3978 purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears 3979 the corresponding bit in DOORBELL_IN on the opposite core. 3980 Clearing all bits will cause that core's doorbell interrupt 3981 to deassert. Since the usual order of events is for software 3982 to send events using DOORBELL_OUT_SET, and acknowledge 3983 incoming events by writing to DOORBELL_IN_CLR, this register 3984 should be used with caution to avoid race conditions. Reading 3985 returns the status of the doorbells currently asserted 3986 on the other core, i.e. is equivalent to that core reading 3987 its own DOORBELL_IN status. */ 3988 __IOM uint32_t DOORBELL_IN_SET; /*!< Write 1s to trigger doorbell interrupts on this core. Read to 3989 get status of doorbells currently asserted on this core. */ 3990 __IOM uint32_t DOORBELL_IN_CLR; /*!< Check and acknowledge doorbells posted to this core. This core's 3991 doorbell interrupt is asserted when any bit in this register 3992 is 1. Write 1 to each bit to clear that bit. The doorbell 3993 interrupt deasserts once all bits are cleared. Read to 3994 get status of doorbells currently asserted on this core. */ 3995 __IOM uint32_t PERI_NONSEC; /*!< Detach certain core-local peripherals from Secure SIO, and attach 3996 them to Non-secure SIO, so that Non-secure software can 3997 use them. Attempting to access one of these peripherals 3998 from the Secure SIO when it is attached to the Non-secure 3999 SIO, or vice versa, will generate a bus error. This register 4000 is per-core, and is only present on the Secure SIO. Most 4001 SIO hardware is duplicated across the Secure and Non-secure 4002 SIO, so is not listed in this register. */ 4003 __IM uint32_t RESERVED2[3]; 4004 __IOM uint32_t RISCV_SOFTIRQ; /*!< Control the assertion of the standard software interrupt (MIP.MSIP) 4005 on the RISC-V cores. Unlike the RISC-V timer, this interrupt 4006 is not routed to a normal system-level interrupt line, 4007 so can not be used by the Arm cores. It is safe for both 4008 cores to write to this register on the same cycle. The 4009 set/clear effect is accumulated across both cores, and 4010 then applied. If a flag is both set and cleared on the 4011 same cycle, only the set takes effect. */ 4012 __IOM uint32_t MTIME_CTRL; /*!< Control register for the RISC-V 64-bit Machine-mode timer. This 4013 timer is only present in the Secure SIO, so is only accessible 4014 to an Arm core in Secure mode or a RISC-V core in Machine 4015 mode. Note whilst this timer follows the RISC-V privileged 4016 specification, it is equally usable by the Arm cores. The 4017 interrupts are routed to normal system-level interrupt 4018 lines as well as to the MIP.MTIP inputs on the RISC-V cores. */ 4019 __IM uint32_t RESERVED3[2]; 4020 __IOM uint32_t MTIME; /*!< Read/write access to the high half of RISC-V Machine-mode timer. 4021 This register is shared between both cores. If both cores 4022 write on the same cycle, core 1 takes precedence. */ 4023 __IOM uint32_t MTIMEH; /*!< Read/write access to the high half of RISC-V Machine-mode timer. 4024 This register is shared between both cores. If both cores 4025 write on the same cycle, core 1 takes precedence. */ 4026 __IOM uint32_t MTIMECMP; /*!< Low half of RISC-V Machine-mode timer comparator. This register 4027 is core-local, i.e., each core gets a copy of this register, 4028 with the comparison result routed to its own interrupt 4029 line. The timer interrupt is asserted whenever MTIME is 4030 greater than or equal to MTIMECMP. This comparison is unsigned, 4031 and performed on the full 64-bit values. */ 4032 __IOM uint32_t MTIMECMPH; /*!< High half of RISC-V Machine-mode timer comparator. This register 4033 is core-local. The timer interrupt is asserted whenever 4034 MTIME is greater than or equal to MTIMECMP. This comparison 4035 is unsigned, and performed on the full 64-bit values. */ 4036 __IOM uint32_t TMDS_CTRL; /*!< Control register for TMDS encoder. */ 4037 __IOM uint32_t TMDS_WDATA; /*!< Write-only access to the TMDS colour data register. */ 4038 __IOM uint32_t TMDS_PEEK_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed 4039 into a 32-bit value (3x10-bit symbols). The PEEK alias 4040 does not shift the colour register when read, but still 4041 advances the running DC balance state of each encoder. 4042 This is useful for pixel doubling. */ 4043 __IOM uint32_t TMDS_POP_SINGLE; /*!< Get the encoding of one pixel's worth of colour data, packed 4044 into a 32-bit value. The packing is 5 chunks of 3 lanes 4045 times 2 bits (30 bits total). Each chunk contains two bits 4046 of a TMDS symbol per lane. This format is intended for 4047 shifting out with the HSTX peripheral on RP2350. The POP 4048 alias shifts the colour register when read, as well as 4049 advancing the running DC balance state of each encoder. */ 4050 __IOM uint32_t TMDS_PEEK_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. 4051 Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 4052 word. The PEEK alias does not shift the colour register 4053 when read, but still advances the lane 0 DC balance state. 4054 This is useful if all 3 lanes' worth of encode are to be 4055 read at once, rather than processing the entire scanline 4056 for one lane before moving to the next lane. */ 4057 __IOM uint32_t TMDS_POP_DOUBLE_L0; /*!< Get lane 0 of the encoding of two pixels' worth of colour data. 4058 Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 4059 word. The POP alias shifts the colour register when read, 4060 according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ 4061 __IOM uint32_t TMDS_PEEK_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. 4062 Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 4063 word. The PEEK alias does not shift the colour register 4064 when read, but still advances the lane 1 DC balance state. 4065 This is useful if all 3 lanes' worth of encode are to be 4066 read at once, rather than processing the entire scanline 4067 for one lane before moving to the next lane. */ 4068 __IOM uint32_t TMDS_POP_DOUBLE_L1; /*!< Get lane 1 of the encoding of two pixels' worth of colour data. 4069 Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 4070 word. The POP alias shifts the colour register when read, 4071 according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ 4072 __IOM uint32_t TMDS_PEEK_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. 4073 Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 4074 word. The PEEK alias does not shift the colour register 4075 when read, but still advances the lane 2 DC balance state. 4076 This is useful if all 3 lanes' worth of encode are to be 4077 read at once, rather than processing the entire scanline 4078 for one lane before moving to the next lane. */ 4079 __IOM uint32_t TMDS_POP_DOUBLE_L2; /*!< Get lane 2 of the encoding of two pixels' worth of colour data. 4080 Two 10-bit TMDS symbols are packed at the bottom of a 32-bit 4081 word. The POP alias shifts the colour register when read, 4082 according to the values of PIX_SHIFT and PIX2_NOSHIFT. */ 4083 } SIO_Type; /*!< Size = 488 (0x1e8) */ 4084 4085 4086 4087 /* =========================================================================================================================== */ 4088 /* ================ BOOTRAM ================ */ 4089 /* =========================================================================================================================== */ 4090 4091 4092 /** 4093 * @brief Additional registers mapped adjacent to the bootram, for use by the bootrom. (BOOTRAM) 4094 */ 4095 4096 typedef struct { /*!< BOOTRAM Structure */ 4097 __IM uint32_t RESERVED[512]; 4098 __IOM uint32_t WRITE_ONCE0; /*!< This registers always ORs writes into its current contents. 4099 Once a bit is set, it can only be cleared by a reset. */ 4100 __IOM uint32_t WRITE_ONCE1; /*!< This registers always ORs writes into its current contents. 4101 Once a bit is set, it can only be cleared by a reset. */ 4102 __IOM uint32_t BOOTLOCK_STAT; /*!< Bootlock status register. 1=unclaimed, 0=claimed. These locks 4103 function identically to the SIO spinlocks, but are reserved 4104 for bootrom use. */ 4105 __IOM uint32_t BOOTLOCK0; /*!< Read to claim and check. Write to unclaim. The value returned 4106 on successful claim is 1 << n, and on failed claim is zero. */ 4107 __IOM uint32_t BOOTLOCK1; /*!< Read to claim and check. Write to unclaim. The value returned 4108 on successful claim is 1 << n, and on failed claim is zero. */ 4109 __IOM uint32_t BOOTLOCK2; /*!< Read to claim and check. Write to unclaim. The value returned 4110 on successful claim is 1 << n, and on failed claim is zero. */ 4111 __IOM uint32_t BOOTLOCK3; /*!< Read to claim and check. Write to unclaim. The value returned 4112 on successful claim is 1 << n, and on failed claim is zero. */ 4113 __IOM uint32_t BOOTLOCK4; /*!< Read to claim and check. Write to unclaim. The value returned 4114 on successful claim is 1 << n, and on failed claim is zero. */ 4115 __IOM uint32_t BOOTLOCK5; /*!< Read to claim and check. Write to unclaim. The value returned 4116 on successful claim is 1 << n, and on failed claim is zero. */ 4117 __IOM uint32_t BOOTLOCK6; /*!< Read to claim and check. Write to unclaim. The value returned 4118 on successful claim is 1 << n, and on failed claim is zero. */ 4119 __IOM uint32_t BOOTLOCK7; /*!< Read to claim and check. Write to unclaim. The value returned 4120 on successful claim is 1 << n, and on failed claim is zero. */ 4121 } BOOTRAM_Type; /*!< Size = 2092 (0x82c) */ 4122 4123 4124 4125 /* =========================================================================================================================== */ 4126 /* ================ CORESIGHT_TRACE ================ */ 4127 /* =========================================================================================================================== */ 4128 4129 4130 /** 4131 * @brief Coresight block - RP specific registers (CORESIGHT_TRACE) 4132 */ 4133 4134 typedef struct { /*!< CORESIGHT_TRACE Structure */ 4135 __IOM uint32_t CTRL_STATUS; /*!< Control and status register */ 4136 __IOM uint32_t TRACE_CAPTURE_FIFO; /*!< FIFO for trace data captured from the TPIU */ 4137 } CORESIGHT_TRACE_Type; /*!< Size = 8 (0x8) */ 4138 4139 4140 4141 /* =========================================================================================================================== */ 4142 /* ================ USB ================ */ 4143 /* =========================================================================================================================== */ 4144 4145 4146 /** 4147 * @brief USB FS/LS controller device registers (USB) 4148 */ 4149 4150 typedef struct { /*!< USB Structure */ 4151 __IOM uint32_t ADDR_ENDP; /*!< Device address and endpoint control */ 4152 __IOM uint32_t ADDR_ENDP1; /*!< Interrupt endpoint 1. Only valid for HOST mode. */ 4153 __IOM uint32_t ADDR_ENDP2; /*!< Interrupt endpoint 2. Only valid for HOST mode. */ 4154 __IOM uint32_t ADDR_ENDP3; /*!< Interrupt endpoint 3. Only valid for HOST mode. */ 4155 __IOM uint32_t ADDR_ENDP4; /*!< Interrupt endpoint 4. Only valid for HOST mode. */ 4156 __IOM uint32_t ADDR_ENDP5; /*!< Interrupt endpoint 5. Only valid for HOST mode. */ 4157 __IOM uint32_t ADDR_ENDP6; /*!< Interrupt endpoint 6. Only valid for HOST mode. */ 4158 __IOM uint32_t ADDR_ENDP7; /*!< Interrupt endpoint 7. Only valid for HOST mode. */ 4159 __IOM uint32_t ADDR_ENDP8; /*!< Interrupt endpoint 8. Only valid for HOST mode. */ 4160 __IOM uint32_t ADDR_ENDP9; /*!< Interrupt endpoint 9. Only valid for HOST mode. */ 4161 __IOM uint32_t ADDR_ENDP10; /*!< Interrupt endpoint 10. Only valid for HOST mode. */ 4162 __IOM uint32_t ADDR_ENDP11; /*!< Interrupt endpoint 11. Only valid for HOST mode. */ 4163 __IOM uint32_t ADDR_ENDP12; /*!< Interrupt endpoint 12. Only valid for HOST mode. */ 4164 __IOM uint32_t ADDR_ENDP13; /*!< Interrupt endpoint 13. Only valid for HOST mode. */ 4165 __IOM uint32_t ADDR_ENDP14; /*!< Interrupt endpoint 14. Only valid for HOST mode. */ 4166 __IOM uint32_t ADDR_ENDP15; /*!< Interrupt endpoint 15. Only valid for HOST mode. */ 4167 __IOM uint32_t MAIN_CTRL; /*!< Main control register */ 4168 __IOM uint32_t SOF_WR; /*!< Set the SOF (Start of Frame) frame number in the host controller. 4169 The SOF packet is sent every 1ms and the host will increment 4170 the frame number by 1 each time. */ 4171 __IOM uint32_t SOF_RD; /*!< Read the last SOF (Start of Frame) frame number seen. In device 4172 mode the last SOF received from the host. In host mode 4173 the last SOF sent by the host. */ 4174 __IOM uint32_t SIE_CTRL; /*!< SIE control register */ 4175 __IOM uint32_t SIE_STATUS; /*!< SIE status register */ 4176 __IOM uint32_t INT_EP_CTRL; /*!< interrupt endpoint control register */ 4177 __IOM uint32_t BUFF_STATUS; /*!< Buffer status register. A bit set here indicates that a buffer 4178 has completed on the endpoint (if the buffer interrupt 4179 is enabled). It is possible for 2 buffers to be completed, 4180 so clearing the buffer status bit may instantly re set 4181 it on the next clock cycle. */ 4182 __IOM uint32_t BUFF_CPU_SHOULD_HANDLE; /*!< Which of the double buffers should be handled. Only valid if 4183 using an interrupt per buffer (i.e. not per 2 buffers). 4184 Not valid for host interrupt endpoint polling because they 4185 are only single buffered. */ 4186 __IOM uint32_t EP_ABORT; /*!< Device only: Can be set to ignore the buffer control register 4187 for this endpoint in case you would like to revoke a buffer. 4188 A NAK will be sent for every access to the endpoint until 4189 this bit is cleared. A corresponding bit in `EP_ABORT_DONE` 4190 is set when it is safe to modify the buffer control register. */ 4191 __IOM uint32_t EP_ABORT_DONE; /*!< Device only: Used in conjunction with `EP_ABORT`. Set once an 4192 endpoint is idle so the programmer knows it is safe to 4193 modify the buffer control register. */ 4194 __IOM uint32_t EP_STALL_ARM; /*!< Device: this bit must be set in conjunction with the `STALL` 4195 bit in the buffer control register to send a STALL on EP0. 4196 The device controller clears these bits when a SETUP packet 4197 is received because the USB spec requires that a STALL 4198 condition is cleared when a SETUP packet is received. */ 4199 __IOM uint32_t NAK_POLL; /*!< Used by the host controller. Sets the wait time in microseconds 4200 before trying again if the device replies with a NAK. */ 4201 __IOM uint32_t EP_STATUS_STALL_NAK; /*!< Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` 4202 bits are set. For EP0 this comes from `SIE_CTRL`. For all 4203 other endpoints it comes from the endpoint control register. */ 4204 __IOM uint32_t USB_MUXING; /*!< Where to connect the USB controller. Should be to_phy by default. */ 4205 __IOM uint32_t USB_PWR; /*!< Overrides for the power signals in the event that the VBUS signals 4206 are not hooked up to GPIO. Set the value of the override 4207 and then the override enable to switch over to the override 4208 value. */ 4209 __IOM uint32_t USBPHY_DIRECT; /*!< This register allows for direct control of the USB phy. Use 4210 in conjunction with usbphy_direct_override register to 4211 enable each override bit. */ 4212 __IOM uint32_t USBPHY_DIRECT_OVERRIDE; /*!< Override enable for each control in usbphy_direct */ 4213 __IOM uint32_t USBPHY_TRIM; /*!< Used to adjust trim values of USB phy pull down resistors. */ 4214 __IOM uint32_t LINESTATE_TUNING; /*!< Used for debug only. */ 4215 __IOM uint32_t INTR; /*!< Raw Interrupts */ 4216 __IOM uint32_t INTE; /*!< Interrupt Enable */ 4217 __IOM uint32_t INTF; /*!< Interrupt Force */ 4218 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 4219 __IM uint32_t RESERVED[25]; 4220 __IOM uint32_t SOF_TIMESTAMP_RAW; /*!< Device only. Raw value of free-running PHY clock counter @48MHz. 4221 Used to calculate time between SOF events. */ 4222 __IOM uint32_t SOF_TIMESTAMP_LAST; /*!< Device only. Value of free-running PHY clock counter @48MHz 4223 when last SOF event occurred. */ 4224 __IOM uint32_t SM_STATE; /*!< SM_STATE */ 4225 __IOM uint32_t EP_TX_ERROR; /*!< TX error count for each endpoint. Write to each field to reset 4226 the counter to 0. */ 4227 __IOM uint32_t EP_RX_ERROR; /*!< RX error count for each endpoint. Write to each field to reset 4228 the counter to 0. */ 4229 __IOM uint32_t DEV_SM_WATCHDOG; /*!< Watchdog that forces the device state machine to idle and raises 4230 an interrupt if the device stays in a state that isn't 4231 idle for the configured limit. The counter is reset on 4232 every state transition. Set limit while enable is low and 4233 then set the enable. */ 4234 } USB_Type; /*!< Size = 280 (0x118) */ 4235 4236 4237 4238 /* =========================================================================================================================== */ 4239 /* ================ TRNG ================ */ 4240 /* =========================================================================================================================== */ 4241 4242 4243 /** 4244 * @brief ARM TrustZone RNG register block (TRNG) 4245 */ 4246 4247 typedef struct { /*!< TRNG Structure */ 4248 __IM uint32_t RESERVED[64]; 4249 __IOM uint32_t RNG_IMR; /*!< Interrupt masking. */ 4250 __IOM uint32_t RNG_ISR; /*!< RNG status register. If corresponding RNG_IMR bit is unmasked, 4251 an interrupt will be generated. */ 4252 __IOM uint32_t RNG_ICR; /*!< Interrupt/status bit clear Register. */ 4253 __IOM uint32_t TRNG_CONFIG; /*!< Selecting the inverter-chain length. */ 4254 __IOM uint32_t TRNG_VALID; /*!< 192 bit collection indication. */ 4255 __IOM uint32_t EHR_DATA0; /*!< RNG collected bits. */ 4256 __IOM uint32_t EHR_DATA1; /*!< RNG collected bits. */ 4257 __IOM uint32_t EHR_DATA2; /*!< RNG collected bits. */ 4258 __IOM uint32_t EHR_DATA3; /*!< RNG collected bits. */ 4259 __IOM uint32_t EHR_DATA4; /*!< RNG collected bits. */ 4260 __IOM uint32_t EHR_DATA5; /*!< RNG collected bits. */ 4261 __IOM uint32_t RND_SOURCE_ENABLE; /*!< Enable signal for the random source. */ 4262 __IOM uint32_t SAMPLE_CNT1; /*!< Counts clocks between sampling of random bit. */ 4263 __IOM uint32_t AUTOCORR_STATISTIC; /*!< Statistic about Autocorrelation test activations. */ 4264 __IOM uint32_t TRNG_DEBUG_CONTROL; /*!< Debug register. */ 4265 __IM uint32_t RESERVED1; 4266 __IOM uint32_t TRNG_SW_RESET; /*!< Generate internal SW reset within the RNG block. */ 4267 __IM uint32_t RESERVED2[28]; 4268 __IOM uint32_t RNG_DEBUG_EN_INPUT; /*!< Enable the RNG debug mode */ 4269 __IOM uint32_t TRNG_BUSY; /*!< RNG Busy indication. */ 4270 __IOM uint32_t RST_BITS_COUNTER; /*!< Reset the counter of collected bits in the RNG. */ 4271 __IOM uint32_t RNG_VERSION; /*!< Displays the version settings of the TRNG. */ 4272 __IM uint32_t RESERVED3[7]; 4273 __IOM uint32_t RNG_BIST_CNTR_0; /*!< Collected BIST results. */ 4274 __IOM uint32_t RNG_BIST_CNTR_1; /*!< Collected BIST results. */ 4275 __IOM uint32_t RNG_BIST_CNTR_2; /*!< Collected BIST results. */ 4276 } TRNG_Type; /*!< Size = 492 (0x1ec) */ 4277 4278 4279 4280 /* =========================================================================================================================== */ 4281 /* ================ GLITCH_DETECTOR ================ */ 4282 /* =========================================================================================================================== */ 4283 4284 4285 /** 4286 * @brief Glitch detector controls (GLITCH_DETECTOR) 4287 */ 4288 4289 typedef struct { /*!< GLITCH_DETECTOR Structure */ 4290 __IOM uint32_t ARM; /*!< Forcibly arm the glitch detectors, if they are not already armed 4291 by OTP. When armed, any individual detector trigger will 4292 cause a restart of the switched core power domain's power-on 4293 reset state machine. Glitch detector triggers are recorded 4294 accumulatively in TRIG_STATUS. If the system is reset by 4295 a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. 4296 This register is Secure read/write only. */ 4297 __IOM uint32_t DISARM; /*!< DISARM */ 4298 __IOM uint32_t SENSITIVITY; /*!< Adjust the sensitivity of glitch detectors to values other than 4299 their OTP-provided defaults. This register is Secure read/write 4300 only. */ 4301 __IOM uint32_t LOCK; /*!< LOCK */ 4302 __IOM uint32_t TRIG_STATUS; /*!< Set when a detector output triggers. Write-1-clear. (May immediately 4303 return high if the detector remains in a failed state. 4304 Detectors can only be cleared by a full reset of the switched 4305 core power domain.) This register is Secure read/write 4306 only. */ 4307 __IOM uint32_t TRIG_FORCE; /*!< Simulate the firing of one or more detectors. Writing ones to 4308 this register will set the matching bits in STATUS_TRIG. 4309 If the glitch detectors are currently armed, writing ones 4310 will also immediately reset the switched core power domain, 4311 and set the reset reason latches in POWMAN_CHIP_RESET to 4312 indicate a glitch detector resets. This register is Secure 4313 read/write only. */ 4314 } GLITCH_DETECTOR_Type; /*!< Size = 24 (0x18) */ 4315 4316 4317 4318 /* =========================================================================================================================== */ 4319 /* ================ OTP ================ */ 4320 /* =========================================================================================================================== */ 4321 4322 4323 /** 4324 * @brief SNPS OTP control IF (SBPI and RPi wrapper control) (OTP) 4325 */ 4326 4327 typedef struct { /*!< OTP Structure */ 4328 __IOM uint32_t SW_LOCK0; /*!< Software lock register for page 0. Locks are initialised from 4329 the OTP lock pages at reset. This register can be written 4330 to further advance the lock state of each page (until next 4331 reset), and read to check the current lock state of a page. */ 4332 __IOM uint32_t SW_LOCK1; /*!< Software lock register for page 1. Locks are initialised from 4333 the OTP lock pages at reset. This register can be written 4334 to further advance the lock state of each page (until next 4335 reset), and read to check the current lock state of a page. */ 4336 __IOM uint32_t SW_LOCK2; /*!< Software lock register for page 2. Locks are initialised from 4337 the OTP lock pages at reset. This register can be written 4338 to further advance the lock state of each page (until next 4339 reset), and read to check the current lock state of a page. */ 4340 __IOM uint32_t SW_LOCK3; /*!< Software lock register for page 3. Locks are initialised from 4341 the OTP lock pages at reset. This register can be written 4342 to further advance the lock state of each page (until next 4343 reset), and read to check the current lock state of a page. */ 4344 __IOM uint32_t SW_LOCK4; /*!< Software lock register for page 4. Locks are initialised from 4345 the OTP lock pages at reset. This register can be written 4346 to further advance the lock state of each page (until next 4347 reset), and read to check the current lock state of a page. */ 4348 __IOM uint32_t SW_LOCK5; /*!< Software lock register for page 5. Locks are initialised from 4349 the OTP lock pages at reset. This register can be written 4350 to further advance the lock state of each page (until next 4351 reset), and read to check the current lock state of a page. */ 4352 __IOM uint32_t SW_LOCK6; /*!< Software lock register for page 6. Locks are initialised from 4353 the OTP lock pages at reset. This register can be written 4354 to further advance the lock state of each page (until next 4355 reset), and read to check the current lock state of a page. */ 4356 __IOM uint32_t SW_LOCK7; /*!< Software lock register for page 7. Locks are initialised from 4357 the OTP lock pages at reset. This register can be written 4358 to further advance the lock state of each page (until next 4359 reset), and read to check the current lock state of a page. */ 4360 __IOM uint32_t SW_LOCK8; /*!< Software lock register for page 8. Locks are initialised from 4361 the OTP lock pages at reset. This register can be written 4362 to further advance the lock state of each page (until next 4363 reset), and read to check the current lock state of a page. */ 4364 __IOM uint32_t SW_LOCK9; /*!< Software lock register for page 9. Locks are initialised from 4365 the OTP lock pages at reset. This register can be written 4366 to further advance the lock state of each page (until next 4367 reset), and read to check the current lock state of a page. */ 4368 __IOM uint32_t SW_LOCK10; /*!< Software lock register for page 10. Locks are initialised from 4369 the OTP lock pages at reset. This register can be written 4370 to further advance the lock state of each page (until next 4371 reset), and read to check the current lock state of a page. */ 4372 __IOM uint32_t SW_LOCK11; /*!< Software lock register for page 11. Locks are initialised from 4373 the OTP lock pages at reset. This register can be written 4374 to further advance the lock state of each page (until next 4375 reset), and read to check the current lock state of a page. */ 4376 __IOM uint32_t SW_LOCK12; /*!< Software lock register for page 12. Locks are initialised from 4377 the OTP lock pages at reset. This register can be written 4378 to further advance the lock state of each page (until next 4379 reset), and read to check the current lock state of a page. */ 4380 __IOM uint32_t SW_LOCK13; /*!< Software lock register for page 13. Locks are initialised from 4381 the OTP lock pages at reset. This register can be written 4382 to further advance the lock state of each page (until next 4383 reset), and read to check the current lock state of a page. */ 4384 __IOM uint32_t SW_LOCK14; /*!< Software lock register for page 14. Locks are initialised from 4385 the OTP lock pages at reset. This register can be written 4386 to further advance the lock state of each page (until next 4387 reset), and read to check the current lock state of a page. */ 4388 __IOM uint32_t SW_LOCK15; /*!< Software lock register for page 15. Locks are initialised from 4389 the OTP lock pages at reset. This register can be written 4390 to further advance the lock state of each page (until next 4391 reset), and read to check the current lock state of a page. */ 4392 __IOM uint32_t SW_LOCK16; /*!< Software lock register for page 16. Locks are initialised from 4393 the OTP lock pages at reset. This register can be written 4394 to further advance the lock state of each page (until next 4395 reset), and read to check the current lock state of a page. */ 4396 __IOM uint32_t SW_LOCK17; /*!< Software lock register for page 17. Locks are initialised from 4397 the OTP lock pages at reset. This register can be written 4398 to further advance the lock state of each page (until next 4399 reset), and read to check the current lock state of a page. */ 4400 __IOM uint32_t SW_LOCK18; /*!< Software lock register for page 18. Locks are initialised from 4401 the OTP lock pages at reset. This register can be written 4402 to further advance the lock state of each page (until next 4403 reset), and read to check the current lock state of a page. */ 4404 __IOM uint32_t SW_LOCK19; /*!< Software lock register for page 19. Locks are initialised from 4405 the OTP lock pages at reset. This register can be written 4406 to further advance the lock state of each page (until next 4407 reset), and read to check the current lock state of a page. */ 4408 __IOM uint32_t SW_LOCK20; /*!< Software lock register for page 20. Locks are initialised from 4409 the OTP lock pages at reset. This register can be written 4410 to further advance the lock state of each page (until next 4411 reset), and read to check the current lock state of a page. */ 4412 __IOM uint32_t SW_LOCK21; /*!< Software lock register for page 21. Locks are initialised from 4413 the OTP lock pages at reset. This register can be written 4414 to further advance the lock state of each page (until next 4415 reset), and read to check the current lock state of a page. */ 4416 __IOM uint32_t SW_LOCK22; /*!< Software lock register for page 22. Locks are initialised from 4417 the OTP lock pages at reset. This register can be written 4418 to further advance the lock state of each page (until next 4419 reset), and read to check the current lock state of a page. */ 4420 __IOM uint32_t SW_LOCK23; /*!< Software lock register for page 23. Locks are initialised from 4421 the OTP lock pages at reset. This register can be written 4422 to further advance the lock state of each page (until next 4423 reset), and read to check the current lock state of a page. */ 4424 __IOM uint32_t SW_LOCK24; /*!< Software lock register for page 24. Locks are initialised from 4425 the OTP lock pages at reset. This register can be written 4426 to further advance the lock state of each page (until next 4427 reset), and read to check the current lock state of a page. */ 4428 __IOM uint32_t SW_LOCK25; /*!< Software lock register for page 25. Locks are initialised from 4429 the OTP lock pages at reset. This register can be written 4430 to further advance the lock state of each page (until next 4431 reset), and read to check the current lock state of a page. */ 4432 __IOM uint32_t SW_LOCK26; /*!< Software lock register for page 26. Locks are initialised from 4433 the OTP lock pages at reset. This register can be written 4434 to further advance the lock state of each page (until next 4435 reset), and read to check the current lock state of a page. */ 4436 __IOM uint32_t SW_LOCK27; /*!< Software lock register for page 27. Locks are initialised from 4437 the OTP lock pages at reset. This register can be written 4438 to further advance the lock state of each page (until next 4439 reset), and read to check the current lock state of a page. */ 4440 __IOM uint32_t SW_LOCK28; /*!< Software lock register for page 28. Locks are initialised from 4441 the OTP lock pages at reset. This register can be written 4442 to further advance the lock state of each page (until next 4443 reset), and read to check the current lock state of a page. */ 4444 __IOM uint32_t SW_LOCK29; /*!< Software lock register for page 29. Locks are initialised from 4445 the OTP lock pages at reset. This register can be written 4446 to further advance the lock state of each page (until next 4447 reset), and read to check the current lock state of a page. */ 4448 __IOM uint32_t SW_LOCK30; /*!< Software lock register for page 30. Locks are initialised from 4449 the OTP lock pages at reset. This register can be written 4450 to further advance the lock state of each page (until next 4451 reset), and read to check the current lock state of a page. */ 4452 __IOM uint32_t SW_LOCK31; /*!< Software lock register for page 31. Locks are initialised from 4453 the OTP lock pages at reset. This register can be written 4454 to further advance the lock state of each page (until next 4455 reset), and read to check the current lock state of a page. */ 4456 __IOM uint32_t SW_LOCK32; /*!< Software lock register for page 32. Locks are initialised from 4457 the OTP lock pages at reset. This register can be written 4458 to further advance the lock state of each page (until next 4459 reset), and read to check the current lock state of a page. */ 4460 __IOM uint32_t SW_LOCK33; /*!< Software lock register for page 33. Locks are initialised from 4461 the OTP lock pages at reset. This register can be written 4462 to further advance the lock state of each page (until next 4463 reset), and read to check the current lock state of a page. */ 4464 __IOM uint32_t SW_LOCK34; /*!< Software lock register for page 34. Locks are initialised from 4465 the OTP lock pages at reset. This register can be written 4466 to further advance the lock state of each page (until next 4467 reset), and read to check the current lock state of a page. */ 4468 __IOM uint32_t SW_LOCK35; /*!< Software lock register for page 35. Locks are initialised from 4469 the OTP lock pages at reset. This register can be written 4470 to further advance the lock state of each page (until next 4471 reset), and read to check the current lock state of a page. */ 4472 __IOM uint32_t SW_LOCK36; /*!< Software lock register for page 36. Locks are initialised from 4473 the OTP lock pages at reset. This register can be written 4474 to further advance the lock state of each page (until next 4475 reset), and read to check the current lock state of a page. */ 4476 __IOM uint32_t SW_LOCK37; /*!< Software lock register for page 37. Locks are initialised from 4477 the OTP lock pages at reset. This register can be written 4478 to further advance the lock state of each page (until next 4479 reset), and read to check the current lock state of a page. */ 4480 __IOM uint32_t SW_LOCK38; /*!< Software lock register for page 38. Locks are initialised from 4481 the OTP lock pages at reset. This register can be written 4482 to further advance the lock state of each page (until next 4483 reset), and read to check the current lock state of a page. */ 4484 __IOM uint32_t SW_LOCK39; /*!< Software lock register for page 39. Locks are initialised from 4485 the OTP lock pages at reset. This register can be written 4486 to further advance the lock state of each page (until next 4487 reset), and read to check the current lock state of a page. */ 4488 __IOM uint32_t SW_LOCK40; /*!< Software lock register for page 40. Locks are initialised from 4489 the OTP lock pages at reset. This register can be written 4490 to further advance the lock state of each page (until next 4491 reset), and read to check the current lock state of a page. */ 4492 __IOM uint32_t SW_LOCK41; /*!< Software lock register for page 41. Locks are initialised from 4493 the OTP lock pages at reset. This register can be written 4494 to further advance the lock state of each page (until next 4495 reset), and read to check the current lock state of a page. */ 4496 __IOM uint32_t SW_LOCK42; /*!< Software lock register for page 42. Locks are initialised from 4497 the OTP lock pages at reset. This register can be written 4498 to further advance the lock state of each page (until next 4499 reset), and read to check the current lock state of a page. */ 4500 __IOM uint32_t SW_LOCK43; /*!< Software lock register for page 43. Locks are initialised from 4501 the OTP lock pages at reset. This register can be written 4502 to further advance the lock state of each page (until next 4503 reset), and read to check the current lock state of a page. */ 4504 __IOM uint32_t SW_LOCK44; /*!< Software lock register for page 44. Locks are initialised from 4505 the OTP lock pages at reset. This register can be written 4506 to further advance the lock state of each page (until next 4507 reset), and read to check the current lock state of a page. */ 4508 __IOM uint32_t SW_LOCK45; /*!< Software lock register for page 45. Locks are initialised from 4509 the OTP lock pages at reset. This register can be written 4510 to further advance the lock state of each page (until next 4511 reset), and read to check the current lock state of a page. */ 4512 __IOM uint32_t SW_LOCK46; /*!< Software lock register for page 46. Locks are initialised from 4513 the OTP lock pages at reset. This register can be written 4514 to further advance the lock state of each page (until next 4515 reset), and read to check the current lock state of a page. */ 4516 __IOM uint32_t SW_LOCK47; /*!< Software lock register for page 47. Locks are initialised from 4517 the OTP lock pages at reset. This register can be written 4518 to further advance the lock state of each page (until next 4519 reset), and read to check the current lock state of a page. */ 4520 __IOM uint32_t SW_LOCK48; /*!< Software lock register for page 48. Locks are initialised from 4521 the OTP lock pages at reset. This register can be written 4522 to further advance the lock state of each page (until next 4523 reset), and read to check the current lock state of a page. */ 4524 __IOM uint32_t SW_LOCK49; /*!< Software lock register for page 49. Locks are initialised from 4525 the OTP lock pages at reset. This register can be written 4526 to further advance the lock state of each page (until next 4527 reset), and read to check the current lock state of a page. */ 4528 __IOM uint32_t SW_LOCK50; /*!< Software lock register for page 50. Locks are initialised from 4529 the OTP lock pages at reset. This register can be written 4530 to further advance the lock state of each page (until next 4531 reset), and read to check the current lock state of a page. */ 4532 __IOM uint32_t SW_LOCK51; /*!< Software lock register for page 51. Locks are initialised from 4533 the OTP lock pages at reset. This register can be written 4534 to further advance the lock state of each page (until next 4535 reset), and read to check the current lock state of a page. */ 4536 __IOM uint32_t SW_LOCK52; /*!< Software lock register for page 52. Locks are initialised from 4537 the OTP lock pages at reset. This register can be written 4538 to further advance the lock state of each page (until next 4539 reset), and read to check the current lock state of a page. */ 4540 __IOM uint32_t SW_LOCK53; /*!< Software lock register for page 53. Locks are initialised from 4541 the OTP lock pages at reset. This register can be written 4542 to further advance the lock state of each page (until next 4543 reset), and read to check the current lock state of a page. */ 4544 __IOM uint32_t SW_LOCK54; /*!< Software lock register for page 54. Locks are initialised from 4545 the OTP lock pages at reset. This register can be written 4546 to further advance the lock state of each page (until next 4547 reset), and read to check the current lock state of a page. */ 4548 __IOM uint32_t SW_LOCK55; /*!< Software lock register for page 55. Locks are initialised from 4549 the OTP lock pages at reset. This register can be written 4550 to further advance the lock state of each page (until next 4551 reset), and read to check the current lock state of a page. */ 4552 __IOM uint32_t SW_LOCK56; /*!< Software lock register for page 56. Locks are initialised from 4553 the OTP lock pages at reset. This register can be written 4554 to further advance the lock state of each page (until next 4555 reset), and read to check the current lock state of a page. */ 4556 __IOM uint32_t SW_LOCK57; /*!< Software lock register for page 57. Locks are initialised from 4557 the OTP lock pages at reset. This register can be written 4558 to further advance the lock state of each page (until next 4559 reset), and read to check the current lock state of a page. */ 4560 __IOM uint32_t SW_LOCK58; /*!< Software lock register for page 58. Locks are initialised from 4561 the OTP lock pages at reset. This register can be written 4562 to further advance the lock state of each page (until next 4563 reset), and read to check the current lock state of a page. */ 4564 __IOM uint32_t SW_LOCK59; /*!< Software lock register for page 59. Locks are initialised from 4565 the OTP lock pages at reset. This register can be written 4566 to further advance the lock state of each page (until next 4567 reset), and read to check the current lock state of a page. */ 4568 __IOM uint32_t SW_LOCK60; /*!< Software lock register for page 60. Locks are initialised from 4569 the OTP lock pages at reset. This register can be written 4570 to further advance the lock state of each page (until next 4571 reset), and read to check the current lock state of a page. */ 4572 __IOM uint32_t SW_LOCK61; /*!< Software lock register for page 61. Locks are initialised from 4573 the OTP lock pages at reset. This register can be written 4574 to further advance the lock state of each page (until next 4575 reset), and read to check the current lock state of a page. */ 4576 __IOM uint32_t SW_LOCK62; /*!< Software lock register for page 62. Locks are initialised from 4577 the OTP lock pages at reset. This register can be written 4578 to further advance the lock state of each page (until next 4579 reset), and read to check the current lock state of a page. */ 4580 __IOM uint32_t SW_LOCK63; /*!< Software lock register for page 63. Locks are initialised from 4581 the OTP lock pages at reset. This register can be written 4582 to further advance the lock state of each page (until next 4583 reset), and read to check the current lock state of a page. */ 4584 __IOM uint32_t SBPI_INSTR; /*!< Dispatch instructions to the SBPI interface, used for programming 4585 the OTP fuses. */ 4586 __IOM uint32_t SBPI_WDATA_0; /*!< SBPI write payload bytes 3..0 */ 4587 __IOM uint32_t SBPI_WDATA_1; /*!< SBPI write payload bytes 7..4 */ 4588 __IOM uint32_t SBPI_WDATA_2; /*!< SBPI write payload bytes 11..8 */ 4589 __IOM uint32_t SBPI_WDATA_3; /*!< SBPI write payload bytes 15..12 */ 4590 __IOM uint32_t SBPI_RDATA_0; /*!< Read payload bytes 3..0. Once read, the data in the register 4591 will automatically clear to 0. */ 4592 __IOM uint32_t SBPI_RDATA_1; /*!< Read payload bytes 7..4. Once read, the data in the register 4593 will automatically clear to 0. */ 4594 __IOM uint32_t SBPI_RDATA_2; /*!< Read payload bytes 11..8. Once read, the data in the register 4595 will automatically clear to 0. */ 4596 __IOM uint32_t SBPI_RDATA_3; /*!< Read payload bytes 15..12. Once read, the data in the register 4597 will automatically clear to 0. */ 4598 __IOM uint32_t SBPI_STATUS; /*!< SBPI_STATUS */ 4599 __IOM uint32_t USR; /*!< Controls for APB data read interface (USER interface) */ 4600 __IOM uint32_t DBG; /*!< Debug for OTP power-on state machine */ 4601 __IM uint32_t RESERVED; 4602 __IOM uint32_t BIST; /*!< During BIST, count address locations that have at least one 4603 leaky bit */ 4604 __IOM uint32_t CRT_KEY_W0; /*!< Word 0 (bits 31..0) of the key. Write only, read returns 0x0 */ 4605 __IOM uint32_t CRT_KEY_W1; /*!< Word 1 (bits 63..32) of the key. Write only, read returns 0x0 */ 4606 __IOM uint32_t CRT_KEY_W2; /*!< Word 2 (bits 95..64) of the key. Write only, read returns 0x0 */ 4607 __IOM uint32_t CRT_KEY_W3; /*!< Word 3 (bits 127..96) of the key. Write only, read returns 0x0 */ 4608 __IOM uint32_t CRITICAL; /*!< Quickly check values of critical flags read during boot up */ 4609 __IOM uint32_t KEY_VALID; /*!< Which keys were valid (enrolled) at boot time */ 4610 __IOM uint32_t DEBUGEN; /*!< Enable a debug feature that has been disabled. Debug features 4611 are disabled if one of the relevant critical boot flags 4612 is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), 4613 OR if a debug key is marked valid in OTP, and the matching 4614 key value has not been supplied over SWD. Specifically: 4615 - The DEBUG_DISABLE flag disables all debug features. This 4616 can be fully overridden by setting all bits of this register. 4617 - The SECURE_DEBUG_DISABLE flag disables secure processor 4618 debug. This can be fully overridden by setting the PROC0_SECURE 4619 and PROC1_SECURE bits of this register. - If a single debug 4620 key has been registered, and no matching key value has 4621 been supplied over SWD, then all debug features are disabled. 4622 This can be fully overridden by setting all bits of this 4623 register. - If both debug keys have been registered, and 4624 the Non-secure key's value (key 6) has been supplied over 4625 SWD, secure processor debug is disabled. This can be fully 4626 overridden by setting the PROC0_SECURE and PROC1_SECURE 4627 bits of this register. - If both debug keys have been registered, 4628 and the Secure key's value (key 5) has been supplied over 4629 SWD, then no debug features are disabled by the key mechanism. 4630 However, note that in this case debug features may still 4631 be disabled by the critical boot flags. */ 4632 __IOM uint32_t DEBUGEN_LOCK; /*!< Write 1s to lock corresponding bits in DEBUGEN. This register 4633 is reset by the processor cold reset. */ 4634 __IOM uint32_t ARCHSEL; /*!< Architecture select (Arm/RISC-V). The default and allowable 4635 values of this register are constrained by the critical 4636 boot flags. This register is reset by the earliest reset 4637 in the switched core power domain (before a processor cold 4638 reset). Cores sample their architecture select signal on 4639 a warm reset. The source of the warm reset could be the 4640 system power-up state machine, the watchdog timer, Arm 4641 SYSRESETREQ or from RISC-V hartresetreq. Note that when 4642 an Arm core is deselected, its cold reset domain is also 4643 held in reset, since in particular the SYSRESETREQ bit 4644 becomes inaccessible once the core is deselected. Note 4645 also the RISC-V cores do not have a cold reset domain, 4646 since their corresponding controls are located in the Debug 4647 Module. */ 4648 __IOM uint32_t ARCHSEL_STATUS; /*!< Get the current architecture select state of each core. Cores 4649 sample the current value of the ARCHSEL register when their 4650 warm reset is released, at which point the corresponding 4651 bit in this register will also update. */ 4652 __IOM uint32_t BOOTDIS; /*!< Tell the bootrom to ignore scratch register boot vectors (both 4653 power manager and watchdog) on the next power up. If an 4654 early boot stage has soft-locked some OTP pages in order 4655 to protect their contents from later stages, there is a 4656 risk that Secure code running at a later stage can unlock 4657 the pages by performing a watchdog reset that resets the 4658 OTP. This register can be used to ensure that the bootloader 4659 runs as normal on the next power up, preventing Secure 4660 code at a later stage from accessing OTP in its unlocked 4661 state. Should be used in conjunction with the power manager 4662 BOOTDIS register. */ 4663 __IOM uint32_t INTR; /*!< Raw Interrupts */ 4664 __IOM uint32_t INTE; /*!< Interrupt Enable */ 4665 __IOM uint32_t INTF; /*!< Interrupt Force */ 4666 __IOM uint32_t INTS; /*!< Interrupt status after masking & forcing */ 4667 } OTP_Type; /*!< Size = 372 (0x174) */ 4668 4669 4670 4671 /* =========================================================================================================================== */ 4672 /* ================ OTP_DATA ================ */ 4673 /* =========================================================================================================================== */ 4674 4675 4676 /** 4677 * @brief Predefined OTP data layout for RP2350 (OTP_DATA) 4678 */ 4679 4680 typedef struct { /*!< OTP_DATA Structure */ 4681 __IOM uint16_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain 4682 a 64-bit random identifier for this chip, which can be 4683 read from the USB bootloader PICOBOOT interface or from 4684 the get_sys_info ROM API. The number of random bits makes 4685 the occurrence of twins exceedingly unlikely: for example, 4686 a fleet of a hundred million devices has a 99.97% probability 4687 of no twinned IDs. This is estimated to be lower than the 4688 occurrence of process errors in the assignment of sequential 4689 random IDs, and for practical purposes CHIPID may be treated 4690 as unique. */ 4691 __IOM uint16_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ 4692 __IOM uint16_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ 4693 __IOM uint16_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ 4694 __IOM uint16_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 4695 rows form a 128-bit random number generated during device 4696 test. This ID is not exposed through the USB PICOBOOT GET_INFO 4697 command or the ROM `get_sys_info()` API. However note that 4698 the USB PICOBOOT OTP access point can read the entirety 4699 of page 0, so this value is not meaningfully private unless 4700 the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO 4701 T_IFC flag in BOOT_FLAGS0. */ 4702 __IOM uint16_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ 4703 __IOM uint16_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ 4704 __IOM uint16_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ 4705 __IOM uint16_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ 4706 __IOM uint16_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ 4707 __IOM uint16_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ 4708 __IOM uint16_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ 4709 __IM uint16_t RESERVED[4]; 4710 __IOM uint16_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing 4711 (ECC) This is measured at 1.1 V, at room temperature, with 4712 the ROSC configuration registers in their reset state. */ 4713 __IOM uint16_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing 4714 (ECC) This is measured at 1.1V, at room temperature, with 4715 the LPOSC trim register in its reset state. */ 4716 __IM uint16_t RESERVED1[6]; 4717 __IOM uint16_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the 4718 QFN80 package, and 30 in the QFN60 package. (ECC) */ 4719 __IM uint16_t RESERVED2[29]; 4720 __IOM uint16_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 4721 0x4c11db7, input reflected, output reflected, seed all-ones, 4722 final XOR all-ones) (ECC) */ 4723 __IOM uint16_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ 4724 __IM uint16_t RESERVED3[28]; 4725 __IOM uint16_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed 4726 to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ 4727 __IOM uint16_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of 4728 flash (the default size is 4096 bytes) (ECC) Enabled by 4729 the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, 4730 the size is 4096 * (value + 1) */ 4731 __IOM uint16_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) 4732 Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ 4733 __IOM uint16_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should 4734 be configured to produce an exact 48 MHz based on the crystal 4735 oscillator frequency. User mode software may also use this 4736 value to calculate the expected crystal frequency based 4737 on an assumed 48 MHz PLL output. If no configuration is 4738 given, the crystal is assumed to be 12 MHz. The PLL frequency 4739 can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) 4740 x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal 4741 frequency can be calculated as: XOSC frequency = 48 MHz 4742 x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the 4743 +1 on REFDIV is because the value stored in this OTP location 4744 is the actual divisor value minus one.) Used if and only 4745 if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. 4746 That bit should be set only after this row and BOOTSEL_XOSC_CFG 4747 are both correctly programmed. */ 4748 __IOM uint16_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. 4749 (ECC) These values may also be used by user code configuring 4750 the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL 4751 _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set 4752 only after this row and BOOTSEL_PLL_CFG are both correctly 4753 programmed. */ 4754 __IM uint16_t RESERVED4[3]; 4755 __IOM uint16_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) 4756 The table has 16 rows, each of which are also ECC and marked 4757 valid by the corresponding valid bit in USB_BOOT_FLAGS 4758 (ECC). The entries are either _VALUEs where the 16 bit 4759 value is used as is, or _STRDEFs which acts as a pointers 4760 to a string value. The value stored in a _STRDEF is two 4761 separate bytes: The low seven bits of the first (LSB) byte 4762 indicates the number of characters in the string, and the 4763 top bit of the first (LSB) byte if set to indicate that 4764 each character in the string is two bytes (Unicode) versus 4765 one byte if unset. The second (MSB) byte represents the 4766 location of the string data, and is encoded as the number 4767 of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of 4768 the start of the string is USB_WHITE_LABEL_ADDR value + 4769 msb_byte. In each case, the corresponding valid bit enables 4770 replacing the default value for the corresponding item 4771 provided by the boot rom. Note that Unicode _STRDEFs are 4772 only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST 4773 DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values 4774 will be ignored if specified for other fields, and non-unicode 4775 values for these three items will be converted to Unicode 4776 characters by setting the upper 8 bits to zero. Note that 4777 if the USB_WHITE_LABEL structure or the corresponding strings 4778 are not readable by BOOTSEL mode based on OTP permissions, 4779 or if alignment requirements are not met, then the corresponding 4780 default values are used. The index values indicate where 4781 each field is located (row USB_WHITE_LABEL_ADDR value + 4782 index): */ 4783 __IM uint16_t RESERVED5; 4784 __IOM uint16_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, 4785 the bootrom will load from this location into SRAM and 4786 then directly enter the loaded image. Note that the image 4787 must be signed if SECURE_BOOT_ENABLE is set. The image 4788 itself is assumed to be ECC-protected. This must be an 4789 even number. Equivalently, the OTP boot image must start 4790 at a word-aligned location in the ECC read data address 4791 window. */ 4792 __IOM uint16_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must 4793 be even. The total image size must be a multiple of 4 bytes 4794 (32 bits). */ 4795 __IOM uint16_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry 4796 point). (ECC) This must be a location in main SRAM (main 4797 SRAM is addresses 0x20000000 through 0x20082000) and must 4798 be word-aligned. */ 4799 __IOM uint16_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry 4800 point). (ECC) This must be a location in main SRAM (main 4801 SRAM is addresses 0x20000000 through 0x20082000) and must 4802 be word-aligned. */ 4803 __IM uint16_t RESERVED6[30]; 4804 __IOM uint16_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ 4805 __IOM uint16_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ 4806 __IOM uint16_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ 4807 __IOM uint16_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ 4808 __IOM uint16_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ 4809 __IOM uint16_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ 4810 __IOM uint16_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ 4811 __IOM uint16_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ 4812 __IOM uint16_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ 4813 __IOM uint16_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ 4814 __IOM uint16_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ 4815 __IOM uint16_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ 4816 __IOM uint16_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ 4817 __IOM uint16_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ 4818 __IOM uint16_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ 4819 __IOM uint16_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ 4820 __IOM uint16_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ 4821 __IOM uint16_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ 4822 __IOM uint16_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ 4823 __IOM uint16_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ 4824 __IOM uint16_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ 4825 __IOM uint16_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ 4826 __IOM uint16_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ 4827 __IOM uint16_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ 4828 __IOM uint16_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ 4829 __IOM uint16_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ 4830 __IOM uint16_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ 4831 __IOM uint16_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ 4832 __IOM uint16_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ 4833 __IOM uint16_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ 4834 __IOM uint16_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ 4835 __IOM uint16_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ 4836 __IOM uint16_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ 4837 __IOM uint16_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ 4838 __IOM uint16_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ 4839 __IOM uint16_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ 4840 __IOM uint16_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ 4841 __IOM uint16_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ 4842 __IOM uint16_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ 4843 __IOM uint16_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ 4844 __IOM uint16_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ 4845 __IOM uint16_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ 4846 __IOM uint16_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ 4847 __IOM uint16_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ 4848 __IOM uint16_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ 4849 __IOM uint16_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ 4850 __IOM uint16_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ 4851 __IOM uint16_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ 4852 __IOM uint16_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ 4853 __IOM uint16_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ 4854 __IOM uint16_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ 4855 __IOM uint16_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ 4856 __IOM uint16_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ 4857 __IOM uint16_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ 4858 __IOM uint16_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ 4859 __IOM uint16_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ 4860 __IOM uint16_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ 4861 __IOM uint16_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ 4862 __IOM uint16_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ 4863 __IOM uint16_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ 4864 __IOM uint16_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ 4865 __IOM uint16_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ 4866 __IOM uint16_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ 4867 __IOM uint16_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ 4868 __IM uint16_t RESERVED7[3720]; 4869 __IOM uint16_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ 4870 __IOM uint16_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ 4871 __IOM uint16_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ 4872 __IOM uint16_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ 4873 __IOM uint16_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ 4874 __IOM uint16_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ 4875 __IOM uint16_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ 4876 __IOM uint16_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ 4877 __IOM uint16_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ 4878 __IOM uint16_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ 4879 __IOM uint16_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ 4880 __IOM uint16_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ 4881 __IOM uint16_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ 4882 __IOM uint16_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ 4883 __IOM uint16_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ 4884 __IOM uint16_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ 4885 __IOM uint16_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ 4886 __IOM uint16_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ 4887 __IOM uint16_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ 4888 __IOM uint16_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ 4889 __IOM uint16_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ 4890 __IOM uint16_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ 4891 __IOM uint16_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ 4892 __IOM uint16_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ 4893 __IOM uint16_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ 4894 __IOM uint16_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ 4895 __IOM uint16_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ 4896 __IOM uint16_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ 4897 __IOM uint16_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ 4898 __IOM uint16_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ 4899 __IOM uint16_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ 4900 __IOM uint16_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ 4901 __IOM uint16_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ 4902 __IOM uint16_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ 4903 __IOM uint16_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ 4904 __IOM uint16_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ 4905 __IOM uint16_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ 4906 __IOM uint16_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ 4907 __IOM uint16_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ 4908 __IOM uint16_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ 4909 __IOM uint16_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ 4910 __IOM uint16_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ 4911 __IOM uint16_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ 4912 __IOM uint16_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ 4913 __IOM uint16_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ 4914 __IOM uint16_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ 4915 __IOM uint16_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ 4916 __IOM uint16_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ 4917 } OTP_DATA_Type; /*!< Size = 7920 (0x1ef0) */ 4918 4919 4920 4921 /* =========================================================================================================================== */ 4922 /* ================ OTP_DATA_RAW ================ */ 4923 /* =========================================================================================================================== */ 4924 4925 4926 /** 4927 * @brief Predefined OTP data layout for RP2350 (OTP_DATA_RAW) 4928 */ 4929 4930 typedef struct { /*!< OTP_DATA_RAW Structure */ 4931 __IOM uint32_t CHIPID0; /*!< Bits 15:0 of public device ID. (ECC) The CHIPID0..3 rows contain 4932 a 64-bit random identifier for this chip, which can be 4933 read from the USB bootloader PICOBOOT interface or from 4934 the get_sys_info ROM API. The number of random bits makes 4935 the occurrence of twins exceedingly unlikely: for example, 4936 a fleet of a hundred million devices has a 99.97% probability 4937 of no twinned IDs. This is estimated to be lower than the 4938 occurrence of process errors in the assignment of sequential 4939 random IDs, and for practical purposes CHIPID may be treated 4940 as unique. */ 4941 __IOM uint32_t CHIPID1; /*!< Bits 31:16 of public device ID (ECC) */ 4942 __IOM uint32_t CHIPID2; /*!< Bits 47:32 of public device ID (ECC) */ 4943 __IOM uint32_t CHIPID3; /*!< Bits 63:48 of public device ID (ECC) */ 4944 __IOM uint32_t RANDID0; /*!< Bits 15:0 of private per-device random number (ECC) The RANDID0..7 4945 rows form a 128-bit random number generated during device 4946 test. This ID is not exposed through the USB PICOBOOT GET_INFO 4947 command or the ROM `get_sys_info()` API. However note that 4948 the USB PICOBOOT OTP access point can read the entirety 4949 of page 0, so this value is not meaningfully private unless 4950 the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBO 4951 T_IFC flag in BOOT_FLAGS0. */ 4952 __IOM uint32_t RANDID1; /*!< Bits 31:16 of private per-device random number (ECC) */ 4953 __IOM uint32_t RANDID2; /*!< Bits 47:32 of private per-device random number (ECC) */ 4954 __IOM uint32_t RANDID3; /*!< Bits 63:48 of private per-device random number (ECC) */ 4955 __IOM uint32_t RANDID4; /*!< Bits 79:64 of private per-device random number (ECC) */ 4956 __IOM uint32_t RANDID5; /*!< Bits 95:80 of private per-device random number (ECC) */ 4957 __IOM uint32_t RANDID6; /*!< Bits 111:96 of private per-device random number (ECC) */ 4958 __IOM uint32_t RANDID7; /*!< Bits 127:112 of private per-device random number (ECC) */ 4959 __IM uint32_t RESERVED[4]; 4960 __IOM uint32_t ROSC_CALIB; /*!< Ring oscillator frequency in kHz, measured during manufacturing 4961 (ECC) This is measured at 1.1 V, at room temperature, with 4962 the ROSC configuration registers in their reset state. */ 4963 __IOM uint32_t LPOSC_CALIB; /*!< Low-power oscillator frequency in Hz, measured during manufacturing 4964 (ECC) This is measured at 1.1V, at room temperature, with 4965 the LPOSC trim register in its reset state. */ 4966 __IM uint32_t RESERVED1[6]; 4967 __IOM uint32_t NUM_GPIOS; /*!< The number of main user GPIOs (bank 0). Should read 48 in the 4968 QFN80 package, and 30 in the QFN60 package. (ECC) */ 4969 __IM uint32_t RESERVED2[29]; 4970 __IOM uint32_t INFO_CRC0; /*!< Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 4971 0x4c11db7, input reflected, output reflected, seed all-ones, 4972 final XOR all-ones) (ECC) */ 4973 __IOM uint32_t INFO_CRC1; /*!< Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC) */ 4974 __IOM uint32_t CRIT0; /*!< Page 0 critical boot flags (RBIT-8) */ 4975 __IOM uint32_t CRIT0_R1; /*!< Redundant copy of CRIT0 */ 4976 __IOM uint32_t CRIT0_R2; /*!< Redundant copy of CRIT0 */ 4977 __IOM uint32_t CRIT0_R3; /*!< Redundant copy of CRIT0 */ 4978 __IOM uint32_t CRIT0_R4; /*!< Redundant copy of CRIT0 */ 4979 __IOM uint32_t CRIT0_R5; /*!< Redundant copy of CRIT0 */ 4980 __IOM uint32_t CRIT0_R6; /*!< Redundant copy of CRIT0 */ 4981 __IOM uint32_t CRIT0_R7; /*!< Redundant copy of CRIT0 */ 4982 __IOM uint32_t CRIT1; /*!< Page 1 critical boot flags (RBIT-8) */ 4983 __IOM uint32_t CRIT1_R1; /*!< Redundant copy of CRIT1 */ 4984 __IOM uint32_t CRIT1_R2; /*!< Redundant copy of CRIT1 */ 4985 __IOM uint32_t CRIT1_R3; /*!< Redundant copy of CRIT1 */ 4986 __IOM uint32_t CRIT1_R4; /*!< Redundant copy of CRIT1 */ 4987 __IOM uint32_t CRIT1_R5; /*!< Redundant copy of CRIT1 */ 4988 __IOM uint32_t CRIT1_R6; /*!< Redundant copy of CRIT1 */ 4989 __IOM uint32_t CRIT1_R7; /*!< Redundant copy of CRIT1 */ 4990 __IOM uint32_t BOOT_FLAGS0; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables 4991 always supersede enables. Enables are provided where there 4992 are other configurations in OTP that must be valid. (RBIT-3) */ 4993 __IOM uint32_t BOOT_FLAGS0_R1; /*!< Redundant copy of BOOT_FLAGS0 */ 4994 __IOM uint32_t BOOT_FLAGS0_R2; /*!< Redundant copy of BOOT_FLAGS0 */ 4995 __IOM uint32_t BOOT_FLAGS1; /*!< Disable/Enable boot paths/features in the RP2350 mask ROM. Disables 4996 always supersede enables. Enables are provided where there 4997 are other configurations in OTP that must be valid. (RBIT-3) */ 4998 __IOM uint32_t BOOT_FLAGS1_R1; /*!< Redundant copy of BOOT_FLAGS1 */ 4999 __IOM uint32_t BOOT_FLAGS1_R2; /*!< Redundant copy of BOOT_FLAGS1 */ 5000 __IOM uint32_t DEFAULT_BOOT_VERSION0; /*!< Default boot version thermometer counter, bits 23:0 (RBIT-3) */ 5001 __IOM uint32_t DEFAULT_BOOT_VERSION0_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ 5002 __IOM uint32_t DEFAULT_BOOT_VERSION0_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION0 */ 5003 __IOM uint32_t DEFAULT_BOOT_VERSION1; /*!< Default boot version thermometer counter, bits 47:24 (RBIT-3) */ 5004 __IOM uint32_t DEFAULT_BOOT_VERSION1_R1; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ 5005 __IOM uint32_t DEFAULT_BOOT_VERSION1_R2; /*!< Redundant copy of DEFAULT_BOOT_VERSION1 */ 5006 __IOM uint32_t FLASH_DEVINFO; /*!< Stores information about external flash device(s). (ECC) Assumed 5007 to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set. */ 5008 __IOM uint32_t FLASH_PARTITION_SLOT_SIZE; /*!< Gap between partition table slot 0 and slot 1 at the start of 5009 flash (the default size is 4096 bytes) (ECC) Enabled by 5010 the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, 5011 the size is 4096 * (value + 1) */ 5012 __IOM uint32_t BOOTSEL_LED_CFG; /*!< Pin configuration for LED status, used by USB bootloader. (ECC) 5013 Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set. */ 5014 __IOM uint32_t BOOTSEL_PLL_CFG; /*!< Optional PLL configuration for BOOTSEL mode. (ECC) This should 5015 be configured to produce an exact 48 MHz based on the crystal 5016 oscillator frequency. User mode software may also use this 5017 value to calculate the expected crystal frequency based 5018 on an assumed 48 MHz PLL output. If no configuration is 5019 given, the crystal is assumed to be 12 MHz. The PLL frequency 5020 can be calculated as: PLL out = (XOSC frequency / (REFDIV+1)) 5021 x FBDIV / (POSTDIV1 x POSTDIV2) Conversely the crystal 5022 frequency can be calculated as: XOSC frequency = 48 MHz 5023 x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV (Note the 5024 +1 on REFDIV is because the value stored in this OTP location 5025 is the actual divisor value minus one.) Used if and only 5026 if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. 5027 That bit should be set only after this row and BOOTSEL_XOSC_CFG 5028 are both correctly programmed. */ 5029 __IOM uint32_t BOOTSEL_XOSC_CFG; /*!< Non-default crystal oscillator configuration for the USB bootloader. 5030 (ECC) These values may also be used by user code configuring 5031 the crystal oscillator. Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PL 5032 _XOSC_CFG is set in BOOT_FLAGS0. That bit should be set 5033 only after this row and BOOTSEL_PLL_CFG are both correctly 5034 programmed. */ 5035 __IOM uint32_t USB_BOOT_FLAGS; /*!< USB boot specific feature flags (RBIT-3) */ 5036 __IOM uint32_t USB_BOOT_FLAGS_R1; /*!< Redundant copy of USB_BOOT_FLAGS */ 5037 __IOM uint32_t USB_BOOT_FLAGS_R2; /*!< Redundant copy of USB_BOOT_FLAGS */ 5038 __IOM uint32_t USB_WHITE_LABEL_ADDR; /*!< Row index of the USB_WHITE_LABEL structure within OTP (ECC) 5039 The table has 16 rows, each of which are also ECC and marked 5040 valid by the corresponding valid bit in USB_BOOT_FLAGS 5041 (ECC). The entries are either _VALUEs where the 16 bit 5042 value is used as is, or _STRDEFs which acts as a pointers 5043 to a string value. The value stored in a _STRDEF is two 5044 separate bytes: The low seven bits of the first (LSB) byte 5045 indicates the number of characters in the string, and the 5046 top bit of the first (LSB) byte if set to indicate that 5047 each character in the string is two bytes (Unicode) versus 5048 one byte if unset. The second (MSB) byte represents the 5049 location of the string data, and is encoded as the number 5050 of rows from this USB_WHITE_LABEL_ADDR; i.e. the row of 5051 the start of the string is USB_WHITE_LABEL_ADDR value + 5052 msb_byte. In each case, the corresponding valid bit enables 5053 replacing the default value for the corresponding item 5054 provided by the boot rom. Note that Unicode _STRDEFs are 5055 only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_ST 5056 DEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values 5057 will be ignored if specified for other fields, and non-unicode 5058 values for these three items will be converted to Unicode 5059 characters by setting the upper 8 bits to zero. Note that 5060 if the USB_WHITE_LABEL structure or the corresponding strings 5061 are not readable by BOOTSEL mode based on OTP permissions, 5062 or if alignment requirements are not met, then the corresponding 5063 default values are used. The index values indicate where 5064 each field is located (row USB_WHITE_LABEL_ADDR value + 5065 index): */ 5066 __IM uint32_t RESERVED3; 5067 __IOM uint32_t OTPBOOT_SRC; /*!< OTP start row for the OTP boot image. (ECC) If OTP boot is enabled, 5068 the bootrom will load from this location into SRAM and 5069 then directly enter the loaded image. Note that the image 5070 must be signed if SECURE_BOOT_ENABLE is set. The image 5071 itself is assumed to be ECC-protected. This must be an 5072 even number. Equivalently, the OTP boot image must start 5073 at a word-aligned location in the ECC read data address 5074 window. */ 5075 __IOM uint32_t OTPBOOT_LEN; /*!< Length in rows of the OTP boot image. (ECC) OTPBOOT_LEN must 5076 be even. The total image size must be a multiple of 4 bytes 5077 (32 bits). */ 5078 __IOM uint32_t OTPBOOT_DST0; /*!< Bits 15:0 of the OTP boot image load destination (and entry 5079 point). (ECC) This must be a location in main SRAM (main 5080 SRAM is addresses 0x20000000 through 0x20082000) and must 5081 be word-aligned. */ 5082 __IOM uint32_t OTPBOOT_DST1; /*!< Bits 31:16 of the OTP boot image load destination (and entry 5083 point). (ECC) This must be a location in main SRAM (main 5084 SRAM is addresses 0x20000000 through 0x20082000) and must 5085 be word-aligned. */ 5086 __IM uint32_t RESERVED4[30]; 5087 __IOM uint32_t BOOTKEY0_0; /*!< Bits 15:0 of SHA-256 hash of boot key 0 (ECC) */ 5088 __IOM uint32_t BOOTKEY0_1; /*!< Bits 31:16 of SHA-256 hash of boot key 0 (ECC) */ 5089 __IOM uint32_t BOOTKEY0_2; /*!< Bits 47:32 of SHA-256 hash of boot key 0 (ECC) */ 5090 __IOM uint32_t BOOTKEY0_3; /*!< Bits 63:48 of SHA-256 hash of boot key 0 (ECC) */ 5091 __IOM uint32_t BOOTKEY0_4; /*!< Bits 79:64 of SHA-256 hash of boot key 0 (ECC) */ 5092 __IOM uint32_t BOOTKEY0_5; /*!< Bits 95:80 of SHA-256 hash of boot key 0 (ECC) */ 5093 __IOM uint32_t BOOTKEY0_6; /*!< Bits 111:96 of SHA-256 hash of boot key 0 (ECC) */ 5094 __IOM uint32_t BOOTKEY0_7; /*!< Bits 127:112 of SHA-256 hash of boot key 0 (ECC) */ 5095 __IOM uint32_t BOOTKEY0_8; /*!< Bits 143:128 of SHA-256 hash of boot key 0 (ECC) */ 5096 __IOM uint32_t BOOTKEY0_9; /*!< Bits 159:144 of SHA-256 hash of boot key 0 (ECC) */ 5097 __IOM uint32_t BOOTKEY0_10; /*!< Bits 175:160 of SHA-256 hash of boot key 0 (ECC) */ 5098 __IOM uint32_t BOOTKEY0_11; /*!< Bits 191:176 of SHA-256 hash of boot key 0 (ECC) */ 5099 __IOM uint32_t BOOTKEY0_12; /*!< Bits 207:192 of SHA-256 hash of boot key 0 (ECC) */ 5100 __IOM uint32_t BOOTKEY0_13; /*!< Bits 223:208 of SHA-256 hash of boot key 0 (ECC) */ 5101 __IOM uint32_t BOOTKEY0_14; /*!< Bits 239:224 of SHA-256 hash of boot key 0 (ECC) */ 5102 __IOM uint32_t BOOTKEY0_15; /*!< Bits 255:240 of SHA-256 hash of boot key 0 (ECC) */ 5103 __IOM uint32_t BOOTKEY1_0; /*!< Bits 15:0 of SHA-256 hash of boot key 1 (ECC) */ 5104 __IOM uint32_t BOOTKEY1_1; /*!< Bits 31:16 of SHA-256 hash of boot key 1 (ECC) */ 5105 __IOM uint32_t BOOTKEY1_2; /*!< Bits 47:32 of SHA-256 hash of boot key 1 (ECC) */ 5106 __IOM uint32_t BOOTKEY1_3; /*!< Bits 63:48 of SHA-256 hash of boot key 1 (ECC) */ 5107 __IOM uint32_t BOOTKEY1_4; /*!< Bits 79:64 of SHA-256 hash of boot key 1 (ECC) */ 5108 __IOM uint32_t BOOTKEY1_5; /*!< Bits 95:80 of SHA-256 hash of boot key 1 (ECC) */ 5109 __IOM uint32_t BOOTKEY1_6; /*!< Bits 111:96 of SHA-256 hash of boot key 1 (ECC) */ 5110 __IOM uint32_t BOOTKEY1_7; /*!< Bits 127:112 of SHA-256 hash of boot key 1 (ECC) */ 5111 __IOM uint32_t BOOTKEY1_8; /*!< Bits 143:128 of SHA-256 hash of boot key 1 (ECC) */ 5112 __IOM uint32_t BOOTKEY1_9; /*!< Bits 159:144 of SHA-256 hash of boot key 1 (ECC) */ 5113 __IOM uint32_t BOOTKEY1_10; /*!< Bits 175:160 of SHA-256 hash of boot key 1 (ECC) */ 5114 __IOM uint32_t BOOTKEY1_11; /*!< Bits 191:176 of SHA-256 hash of boot key 1 (ECC) */ 5115 __IOM uint32_t BOOTKEY1_12; /*!< Bits 207:192 of SHA-256 hash of boot key 1 (ECC) */ 5116 __IOM uint32_t BOOTKEY1_13; /*!< Bits 223:208 of SHA-256 hash of boot key 1 (ECC) */ 5117 __IOM uint32_t BOOTKEY1_14; /*!< Bits 239:224 of SHA-256 hash of boot key 1 (ECC) */ 5118 __IOM uint32_t BOOTKEY1_15; /*!< Bits 255:240 of SHA-256 hash of boot key 1 (ECC) */ 5119 __IOM uint32_t BOOTKEY2_0; /*!< Bits 15:0 of SHA-256 hash of boot key 2 (ECC) */ 5120 __IOM uint32_t BOOTKEY2_1; /*!< Bits 31:16 of SHA-256 hash of boot key 2 (ECC) */ 5121 __IOM uint32_t BOOTKEY2_2; /*!< Bits 47:32 of SHA-256 hash of boot key 2 (ECC) */ 5122 __IOM uint32_t BOOTKEY2_3; /*!< Bits 63:48 of SHA-256 hash of boot key 2 (ECC) */ 5123 __IOM uint32_t BOOTKEY2_4; /*!< Bits 79:64 of SHA-256 hash of boot key 2 (ECC) */ 5124 __IOM uint32_t BOOTKEY2_5; /*!< Bits 95:80 of SHA-256 hash of boot key 2 (ECC) */ 5125 __IOM uint32_t BOOTKEY2_6; /*!< Bits 111:96 of SHA-256 hash of boot key 2 (ECC) */ 5126 __IOM uint32_t BOOTKEY2_7; /*!< Bits 127:112 of SHA-256 hash of boot key 2 (ECC) */ 5127 __IOM uint32_t BOOTKEY2_8; /*!< Bits 143:128 of SHA-256 hash of boot key 2 (ECC) */ 5128 __IOM uint32_t BOOTKEY2_9; /*!< Bits 159:144 of SHA-256 hash of boot key 2 (ECC) */ 5129 __IOM uint32_t BOOTKEY2_10; /*!< Bits 175:160 of SHA-256 hash of boot key 2 (ECC) */ 5130 __IOM uint32_t BOOTKEY2_11; /*!< Bits 191:176 of SHA-256 hash of boot key 2 (ECC) */ 5131 __IOM uint32_t BOOTKEY2_12; /*!< Bits 207:192 of SHA-256 hash of boot key 2 (ECC) */ 5132 __IOM uint32_t BOOTKEY2_13; /*!< Bits 223:208 of SHA-256 hash of boot key 2 (ECC) */ 5133 __IOM uint32_t BOOTKEY2_14; /*!< Bits 239:224 of SHA-256 hash of boot key 2 (ECC) */ 5134 __IOM uint32_t BOOTKEY2_15; /*!< Bits 255:240 of SHA-256 hash of boot key 2 (ECC) */ 5135 __IOM uint32_t BOOTKEY3_0; /*!< Bits 15:0 of SHA-256 hash of boot key 3 (ECC) */ 5136 __IOM uint32_t BOOTKEY3_1; /*!< Bits 31:16 of SHA-256 hash of boot key 3 (ECC) */ 5137 __IOM uint32_t BOOTKEY3_2; /*!< Bits 47:32 of SHA-256 hash of boot key 3 (ECC) */ 5138 __IOM uint32_t BOOTKEY3_3; /*!< Bits 63:48 of SHA-256 hash of boot key 3 (ECC) */ 5139 __IOM uint32_t BOOTKEY3_4; /*!< Bits 79:64 of SHA-256 hash of boot key 3 (ECC) */ 5140 __IOM uint32_t BOOTKEY3_5; /*!< Bits 95:80 of SHA-256 hash of boot key 3 (ECC) */ 5141 __IOM uint32_t BOOTKEY3_6; /*!< Bits 111:96 of SHA-256 hash of boot key 3 (ECC) */ 5142 __IOM uint32_t BOOTKEY3_7; /*!< Bits 127:112 of SHA-256 hash of boot key 3 (ECC) */ 5143 __IOM uint32_t BOOTKEY3_8; /*!< Bits 143:128 of SHA-256 hash of boot key 3 (ECC) */ 5144 __IOM uint32_t BOOTKEY3_9; /*!< Bits 159:144 of SHA-256 hash of boot key 3 (ECC) */ 5145 __IOM uint32_t BOOTKEY3_10; /*!< Bits 175:160 of SHA-256 hash of boot key 3 (ECC) */ 5146 __IOM uint32_t BOOTKEY3_11; /*!< Bits 191:176 of SHA-256 hash of boot key 3 (ECC) */ 5147 __IOM uint32_t BOOTKEY3_12; /*!< Bits 207:192 of SHA-256 hash of boot key 3 (ECC) */ 5148 __IOM uint32_t BOOTKEY3_13; /*!< Bits 223:208 of SHA-256 hash of boot key 3 (ECC) */ 5149 __IOM uint32_t BOOTKEY3_14; /*!< Bits 239:224 of SHA-256 hash of boot key 3 (ECC) */ 5150 __IOM uint32_t BOOTKEY3_15; /*!< Bits 255:240 of SHA-256 hash of boot key 3 (ECC) */ 5151 __IM uint32_t RESERVED5[3720]; 5152 __IOM uint32_t KEY1_0; /*!< Bits 15:0 of OTP access key 1 (ECC) */ 5153 __IOM uint32_t KEY1_1; /*!< Bits 31:16 of OTP access key 1 (ECC) */ 5154 __IOM uint32_t KEY1_2; /*!< Bits 47:32 of OTP access key 1 (ECC) */ 5155 __IOM uint32_t KEY1_3; /*!< Bits 63:48 of OTP access key 1 (ECC) */ 5156 __IOM uint32_t KEY1_4; /*!< Bits 79:64 of OTP access key 1 (ECC) */ 5157 __IOM uint32_t KEY1_5; /*!< Bits 95:80 of OTP access key 1 (ECC) */ 5158 __IOM uint32_t KEY1_6; /*!< Bits 111:96 of OTP access key 1 (ECC) */ 5159 __IOM uint32_t KEY1_7; /*!< Bits 127:112 of OTP access key 1 (ECC) */ 5160 __IOM uint32_t KEY2_0; /*!< Bits 15:0 of OTP access key 2 (ECC) */ 5161 __IOM uint32_t KEY2_1; /*!< Bits 31:16 of OTP access key 2 (ECC) */ 5162 __IOM uint32_t KEY2_2; /*!< Bits 47:32 of OTP access key 2 (ECC) */ 5163 __IOM uint32_t KEY2_3; /*!< Bits 63:48 of OTP access key 2 (ECC) */ 5164 __IOM uint32_t KEY2_4; /*!< Bits 79:64 of OTP access key 2 (ECC) */ 5165 __IOM uint32_t KEY2_5; /*!< Bits 95:80 of OTP access key 2 (ECC) */ 5166 __IOM uint32_t KEY2_6; /*!< Bits 111:96 of OTP access key 2 (ECC) */ 5167 __IOM uint32_t KEY2_7; /*!< Bits 127:112 of OTP access key 2 (ECC) */ 5168 __IOM uint32_t KEY3_0; /*!< Bits 15:0 of OTP access key 3 (ECC) */ 5169 __IOM uint32_t KEY3_1; /*!< Bits 31:16 of OTP access key 3 (ECC) */ 5170 __IOM uint32_t KEY3_2; /*!< Bits 47:32 of OTP access key 3 (ECC) */ 5171 __IOM uint32_t KEY3_3; /*!< Bits 63:48 of OTP access key 3 (ECC) */ 5172 __IOM uint32_t KEY3_4; /*!< Bits 79:64 of OTP access key 3 (ECC) */ 5173 __IOM uint32_t KEY3_5; /*!< Bits 95:80 of OTP access key 3 (ECC) */ 5174 __IOM uint32_t KEY3_6; /*!< Bits 111:96 of OTP access key 3 (ECC) */ 5175 __IOM uint32_t KEY3_7; /*!< Bits 127:112 of OTP access key 3 (ECC) */ 5176 __IOM uint32_t KEY4_0; /*!< Bits 15:0 of OTP access key 4 (ECC) */ 5177 __IOM uint32_t KEY4_1; /*!< Bits 31:16 of OTP access key 4 (ECC) */ 5178 __IOM uint32_t KEY4_2; /*!< Bits 47:32 of OTP access key 4 (ECC) */ 5179 __IOM uint32_t KEY4_3; /*!< Bits 63:48 of OTP access key 4 (ECC) */ 5180 __IOM uint32_t KEY4_4; /*!< Bits 79:64 of OTP access key 4 (ECC) */ 5181 __IOM uint32_t KEY4_5; /*!< Bits 95:80 of OTP access key 4 (ECC) */ 5182 __IOM uint32_t KEY4_6; /*!< Bits 111:96 of OTP access key 4 (ECC) */ 5183 __IOM uint32_t KEY4_7; /*!< Bits 127:112 of OTP access key 4 (ECC) */ 5184 __IOM uint32_t KEY5_0; /*!< Bits 15:0 of OTP access key 5 (ECC) */ 5185 __IOM uint32_t KEY5_1; /*!< Bits 31:16 of OTP access key 5 (ECC) */ 5186 __IOM uint32_t KEY5_2; /*!< Bits 47:32 of OTP access key 5 (ECC) */ 5187 __IOM uint32_t KEY5_3; /*!< Bits 63:48 of OTP access key 5 (ECC) */ 5188 __IOM uint32_t KEY5_4; /*!< Bits 79:64 of OTP access key 5 (ECC) */ 5189 __IOM uint32_t KEY5_5; /*!< Bits 95:80 of OTP access key 5 (ECC) */ 5190 __IOM uint32_t KEY5_6; /*!< Bits 111:96 of OTP access key 5 (ECC) */ 5191 __IOM uint32_t KEY5_7; /*!< Bits 127:112 of OTP access key 5 (ECC) */ 5192 __IOM uint32_t KEY6_0; /*!< Bits 15:0 of OTP access key 6 (ECC) */ 5193 __IOM uint32_t KEY6_1; /*!< Bits 31:16 of OTP access key 6 (ECC) */ 5194 __IOM uint32_t KEY6_2; /*!< Bits 47:32 of OTP access key 6 (ECC) */ 5195 __IOM uint32_t KEY6_3; /*!< Bits 63:48 of OTP access key 6 (ECC) */ 5196 __IOM uint32_t KEY6_4; /*!< Bits 79:64 of OTP access key 6 (ECC) */ 5197 __IOM uint32_t KEY6_5; /*!< Bits 95:80 of OTP access key 6 (ECC) */ 5198 __IOM uint32_t KEY6_6; /*!< Bits 111:96 of OTP access key 6 (ECC) */ 5199 __IOM uint32_t KEY6_7; /*!< Bits 127:112 of OTP access key 6 (ECC) */ 5200 __IM uint32_t RESERVED6; 5201 __IOM uint32_t KEY1_VALID; /*!< Valid flag for key 1. Once the valid flag is set, the key can 5202 no longer be read or written, and becomes a valid fixed 5203 key for protecting OTP pages. */ 5204 __IOM uint32_t KEY2_VALID; /*!< Valid flag for key 2. Once the valid flag is set, the key can 5205 no longer be read or written, and becomes a valid fixed 5206 key for protecting OTP pages. */ 5207 __IOM uint32_t KEY3_VALID; /*!< Valid flag for key 3. Once the valid flag is set, the key can 5208 no longer be read or written, and becomes a valid fixed 5209 key for protecting OTP pages. */ 5210 __IOM uint32_t KEY4_VALID; /*!< Valid flag for key 4. Once the valid flag is set, the key can 5211 no longer be read or written, and becomes a valid fixed 5212 key for protecting OTP pages. */ 5213 __IOM uint32_t KEY5_VALID; /*!< Valid flag for key 5. Once the valid flag is set, the key can 5214 no longer be read or written, and becomes a valid fixed 5215 key for protecting OTP pages. */ 5216 __IOM uint32_t KEY6_VALID; /*!< Valid flag for key 6. Once the valid flag is set, the key can 5217 no longer be read or written, and becomes a valid fixed 5218 key for protecting OTP pages. */ 5219 __IM uint32_t RESERVED7; 5220 __IOM uint32_t PAGE0_LOCK0; /*!< Lock configuration LSBs for page 0 (rows 0x0 through 0x3f). 5221 Locks are stored with 3-way majority vote encoding, so 5222 that bits can be set independently. This OTP location is 5223 always readable, and is write-protected by its own permissions. */ 5224 __IOM uint32_t PAGE0_LOCK1; /*!< Lock configuration MSBs for page 0 (rows 0x0 through 0x3f). 5225 Locks are stored with 3-way majority vote encoding, so 5226 that bits can be set independently. This OTP location is 5227 always readable, and is write-protected by its own permissions. */ 5228 __IOM uint32_t PAGE1_LOCK0; /*!< Lock configuration LSBs for page 1 (rows 0x40 through 0x7f). 5229 Locks are stored with 3-way majority vote encoding, so 5230 that bits can be set independently. This OTP location is 5231 always readable, and is write-protected by its own permissions. */ 5232 __IOM uint32_t PAGE1_LOCK1; /*!< Lock configuration MSBs for page 1 (rows 0x40 through 0x7f). 5233 Locks are stored with 3-way majority vote encoding, so 5234 that bits can be set independently. This OTP location is 5235 always readable, and is write-protected by its own permissions. */ 5236 __IOM uint32_t PAGE2_LOCK0; /*!< Lock configuration LSBs for page 2 (rows 0x80 through 0xbf). 5237 Locks are stored with 3-way majority vote encoding, so 5238 that bits can be set independently. This OTP location is 5239 always readable, and is write-protected by its own permissions. */ 5240 __IOM uint32_t PAGE2_LOCK1; /*!< Lock configuration MSBs for page 2 (rows 0x80 through 0xbf). 5241 Locks are stored with 3-way majority vote encoding, so 5242 that bits can be set independently. This OTP location is 5243 always readable, and is write-protected by its own permissions. */ 5244 __IOM uint32_t PAGE3_LOCK0; /*!< Lock configuration LSBs for page 3 (rows 0xc0 through 0xff). 5245 Locks are stored with 3-way majority vote encoding, so 5246 that bits can be set independently. This OTP location is 5247 always readable, and is write-protected by its own permissions. */ 5248 __IOM uint32_t PAGE3_LOCK1; /*!< Lock configuration MSBs for page 3 (rows 0xc0 through 0xff). 5249 Locks are stored with 3-way majority vote encoding, so 5250 that bits can be set independently. This OTP location is 5251 always readable, and is write-protected by its own permissions. */ 5252 __IOM uint32_t PAGE4_LOCK0; /*!< Lock configuration LSBs for page 4 (rows 0x100 through 0x13f). 5253 Locks are stored with 3-way majority vote encoding, so 5254 that bits can be set independently. This OTP location is 5255 always readable, and is write-protected by its own permissions. */ 5256 __IOM uint32_t PAGE4_LOCK1; /*!< Lock configuration MSBs for page 4 (rows 0x100 through 0x13f). 5257 Locks are stored with 3-way majority vote encoding, so 5258 that bits can be set independently. This OTP location is 5259 always readable, and is write-protected by its own permissions. */ 5260 __IOM uint32_t PAGE5_LOCK0; /*!< Lock configuration LSBs for page 5 (rows 0x140 through 0x17f). 5261 Locks are stored with 3-way majority vote encoding, so 5262 that bits can be set independently. This OTP location is 5263 always readable, and is write-protected by its own permissions. */ 5264 __IOM uint32_t PAGE5_LOCK1; /*!< Lock configuration MSBs for page 5 (rows 0x140 through 0x17f). 5265 Locks are stored with 3-way majority vote encoding, so 5266 that bits can be set independently. This OTP location is 5267 always readable, and is write-protected by its own permissions. */ 5268 __IOM uint32_t PAGE6_LOCK0; /*!< Lock configuration LSBs for page 6 (rows 0x180 through 0x1bf). 5269 Locks are stored with 3-way majority vote encoding, so 5270 that bits can be set independently. This OTP location is 5271 always readable, and is write-protected by its own permissions. */ 5272 __IOM uint32_t PAGE6_LOCK1; /*!< Lock configuration MSBs for page 6 (rows 0x180 through 0x1bf). 5273 Locks are stored with 3-way majority vote encoding, so 5274 that bits can be set independently. This OTP location is 5275 always readable, and is write-protected by its own permissions. */ 5276 __IOM uint32_t PAGE7_LOCK0; /*!< Lock configuration LSBs for page 7 (rows 0x1c0 through 0x1ff). 5277 Locks are stored with 3-way majority vote encoding, so 5278 that bits can be set independently. This OTP location is 5279 always readable, and is write-protected by its own permissions. */ 5280 __IOM uint32_t PAGE7_LOCK1; /*!< Lock configuration MSBs for page 7 (rows 0x1c0 through 0x1ff). 5281 Locks are stored with 3-way majority vote encoding, so 5282 that bits can be set independently. This OTP location is 5283 always readable, and is write-protected by its own permissions. */ 5284 __IOM uint32_t PAGE8_LOCK0; /*!< Lock configuration LSBs for page 8 (rows 0x200 through 0x23f). 5285 Locks are stored with 3-way majority vote encoding, so 5286 that bits can be set independently. This OTP location is 5287 always readable, and is write-protected by its own permissions. */ 5288 __IOM uint32_t PAGE8_LOCK1; /*!< Lock configuration MSBs for page 8 (rows 0x200 through 0x23f). 5289 Locks are stored with 3-way majority vote encoding, so 5290 that bits can be set independently. This OTP location is 5291 always readable, and is write-protected by its own permissions. */ 5292 __IOM uint32_t PAGE9_LOCK0; /*!< Lock configuration LSBs for page 9 (rows 0x240 through 0x27f). 5293 Locks are stored with 3-way majority vote encoding, so 5294 that bits can be set independently. This OTP location is 5295 always readable, and is write-protected by its own permissions. */ 5296 __IOM uint32_t PAGE9_LOCK1; /*!< Lock configuration MSBs for page 9 (rows 0x240 through 0x27f). 5297 Locks are stored with 3-way majority vote encoding, so 5298 that bits can be set independently. This OTP location is 5299 always readable, and is write-protected by its own permissions. */ 5300 __IOM uint32_t PAGE10_LOCK0; /*!< Lock configuration LSBs for page 10 (rows 0x280 through 0x2bf). 5301 Locks are stored with 3-way majority vote encoding, so 5302 that bits can be set independently. This OTP location is 5303 always readable, and is write-protected by its own permissions. */ 5304 __IOM uint32_t PAGE10_LOCK1; /*!< Lock configuration MSBs for page 10 (rows 0x280 through 0x2bf). 5305 Locks are stored with 3-way majority vote encoding, so 5306 that bits can be set independently. This OTP location is 5307 always readable, and is write-protected by its own permissions. */ 5308 __IOM uint32_t PAGE11_LOCK0; /*!< Lock configuration LSBs for page 11 (rows 0x2c0 through 0x2ff). 5309 Locks are stored with 3-way majority vote encoding, so 5310 that bits can be set independently. This OTP location is 5311 always readable, and is write-protected by its own permissions. */ 5312 __IOM uint32_t PAGE11_LOCK1; /*!< Lock configuration MSBs for page 11 (rows 0x2c0 through 0x2ff). 5313 Locks are stored with 3-way majority vote encoding, so 5314 that bits can be set independently. This OTP location is 5315 always readable, and is write-protected by its own permissions. */ 5316 __IOM uint32_t PAGE12_LOCK0; /*!< Lock configuration LSBs for page 12 (rows 0x300 through 0x33f). 5317 Locks are stored with 3-way majority vote encoding, so 5318 that bits can be set independently. This OTP location is 5319 always readable, and is write-protected by its own permissions. */ 5320 __IOM uint32_t PAGE12_LOCK1; /*!< Lock configuration MSBs for page 12 (rows 0x300 through 0x33f). 5321 Locks are stored with 3-way majority vote encoding, so 5322 that bits can be set independently. This OTP location is 5323 always readable, and is write-protected by its own permissions. */ 5324 __IOM uint32_t PAGE13_LOCK0; /*!< Lock configuration LSBs for page 13 (rows 0x340 through 0x37f). 5325 Locks are stored with 3-way majority vote encoding, so 5326 that bits can be set independently. This OTP location is 5327 always readable, and is write-protected by its own permissions. */ 5328 __IOM uint32_t PAGE13_LOCK1; /*!< Lock configuration MSBs for page 13 (rows 0x340 through 0x37f). 5329 Locks are stored with 3-way majority vote encoding, so 5330 that bits can be set independently. This OTP location is 5331 always readable, and is write-protected by its own permissions. */ 5332 __IOM uint32_t PAGE14_LOCK0; /*!< Lock configuration LSBs for page 14 (rows 0x380 through 0x3bf). 5333 Locks are stored with 3-way majority vote encoding, so 5334 that bits can be set independently. This OTP location is 5335 always readable, and is write-protected by its own permissions. */ 5336 __IOM uint32_t PAGE14_LOCK1; /*!< Lock configuration MSBs for page 14 (rows 0x380 through 0x3bf). 5337 Locks are stored with 3-way majority vote encoding, so 5338 that bits can be set independently. This OTP location is 5339 always readable, and is write-protected by its own permissions. */ 5340 __IOM uint32_t PAGE15_LOCK0; /*!< Lock configuration LSBs for page 15 (rows 0x3c0 through 0x3ff). 5341 Locks are stored with 3-way majority vote encoding, so 5342 that bits can be set independently. This OTP location is 5343 always readable, and is write-protected by its own permissions. */ 5344 __IOM uint32_t PAGE15_LOCK1; /*!< Lock configuration MSBs for page 15 (rows 0x3c0 through 0x3ff). 5345 Locks are stored with 3-way majority vote encoding, so 5346 that bits can be set independently. This OTP location is 5347 always readable, and is write-protected by its own permissions. */ 5348 __IOM uint32_t PAGE16_LOCK0; /*!< Lock configuration LSBs for page 16 (rows 0x400 through 0x43f). 5349 Locks are stored with 3-way majority vote encoding, so 5350 that bits can be set independently. This OTP location is 5351 always readable, and is write-protected by its own permissions. */ 5352 __IOM uint32_t PAGE16_LOCK1; /*!< Lock configuration MSBs for page 16 (rows 0x400 through 0x43f). 5353 Locks are stored with 3-way majority vote encoding, so 5354 that bits can be set independently. This OTP location is 5355 always readable, and is write-protected by its own permissions. */ 5356 __IOM uint32_t PAGE17_LOCK0; /*!< Lock configuration LSBs for page 17 (rows 0x440 through 0x47f). 5357 Locks are stored with 3-way majority vote encoding, so 5358 that bits can be set independently. This OTP location is 5359 always readable, and is write-protected by its own permissions. */ 5360 __IOM uint32_t PAGE17_LOCK1; /*!< Lock configuration MSBs for page 17 (rows 0x440 through 0x47f). 5361 Locks are stored with 3-way majority vote encoding, so 5362 that bits can be set independently. This OTP location is 5363 always readable, and is write-protected by its own permissions. */ 5364 __IOM uint32_t PAGE18_LOCK0; /*!< Lock configuration LSBs for page 18 (rows 0x480 through 0x4bf). 5365 Locks are stored with 3-way majority vote encoding, so 5366 that bits can be set independently. This OTP location is 5367 always readable, and is write-protected by its own permissions. */ 5368 __IOM uint32_t PAGE18_LOCK1; /*!< Lock configuration MSBs for page 18 (rows 0x480 through 0x4bf). 5369 Locks are stored with 3-way majority vote encoding, so 5370 that bits can be set independently. This OTP location is 5371 always readable, and is write-protected by its own permissions. */ 5372 __IOM uint32_t PAGE19_LOCK0; /*!< Lock configuration LSBs for page 19 (rows 0x4c0 through 0x4ff). 5373 Locks are stored with 3-way majority vote encoding, so 5374 that bits can be set independently. This OTP location is 5375 always readable, and is write-protected by its own permissions. */ 5376 __IOM uint32_t PAGE19_LOCK1; /*!< Lock configuration MSBs for page 19 (rows 0x4c0 through 0x4ff). 5377 Locks are stored with 3-way majority vote encoding, so 5378 that bits can be set independently. This OTP location is 5379 always readable, and is write-protected by its own permissions. */ 5380 __IOM uint32_t PAGE20_LOCK0; /*!< Lock configuration LSBs for page 20 (rows 0x500 through 0x53f). 5381 Locks are stored with 3-way majority vote encoding, so 5382 that bits can be set independently. This OTP location is 5383 always readable, and is write-protected by its own permissions. */ 5384 __IOM uint32_t PAGE20_LOCK1; /*!< Lock configuration MSBs for page 20 (rows 0x500 through 0x53f). 5385 Locks are stored with 3-way majority vote encoding, so 5386 that bits can be set independently. This OTP location is 5387 always readable, and is write-protected by its own permissions. */ 5388 __IOM uint32_t PAGE21_LOCK0; /*!< Lock configuration LSBs for page 21 (rows 0x540 through 0x57f). 5389 Locks are stored with 3-way majority vote encoding, so 5390 that bits can be set independently. This OTP location is 5391 always readable, and is write-protected by its own permissions. */ 5392 __IOM uint32_t PAGE21_LOCK1; /*!< Lock configuration MSBs for page 21 (rows 0x540 through 0x57f). 5393 Locks are stored with 3-way majority vote encoding, so 5394 that bits can be set independently. This OTP location is 5395 always readable, and is write-protected by its own permissions. */ 5396 __IOM uint32_t PAGE22_LOCK0; /*!< Lock configuration LSBs for page 22 (rows 0x580 through 0x5bf). 5397 Locks are stored with 3-way majority vote encoding, so 5398 that bits can be set independently. This OTP location is 5399 always readable, and is write-protected by its own permissions. */ 5400 __IOM uint32_t PAGE22_LOCK1; /*!< Lock configuration MSBs for page 22 (rows 0x580 through 0x5bf). 5401 Locks are stored with 3-way majority vote encoding, so 5402 that bits can be set independently. This OTP location is 5403 always readable, and is write-protected by its own permissions. */ 5404 __IOM uint32_t PAGE23_LOCK0; /*!< Lock configuration LSBs for page 23 (rows 0x5c0 through 0x5ff). 5405 Locks are stored with 3-way majority vote encoding, so 5406 that bits can be set independently. This OTP location is 5407 always readable, and is write-protected by its own permissions. */ 5408 __IOM uint32_t PAGE23_LOCK1; /*!< Lock configuration MSBs for page 23 (rows 0x5c0 through 0x5ff). 5409 Locks are stored with 3-way majority vote encoding, so 5410 that bits can be set independently. This OTP location is 5411 always readable, and is write-protected by its own permissions. */ 5412 __IOM uint32_t PAGE24_LOCK0; /*!< Lock configuration LSBs for page 24 (rows 0x600 through 0x63f). 5413 Locks are stored with 3-way majority vote encoding, so 5414 that bits can be set independently. This OTP location is 5415 always readable, and is write-protected by its own permissions. */ 5416 __IOM uint32_t PAGE24_LOCK1; /*!< Lock configuration MSBs for page 24 (rows 0x600 through 0x63f). 5417 Locks are stored with 3-way majority vote encoding, so 5418 that bits can be set independently. This OTP location is 5419 always readable, and is write-protected by its own permissions. */ 5420 __IOM uint32_t PAGE25_LOCK0; /*!< Lock configuration LSBs for page 25 (rows 0x640 through 0x67f). 5421 Locks are stored with 3-way majority vote encoding, so 5422 that bits can be set independently. This OTP location is 5423 always readable, and is write-protected by its own permissions. */ 5424 __IOM uint32_t PAGE25_LOCK1; /*!< Lock configuration MSBs for page 25 (rows 0x640 through 0x67f). 5425 Locks are stored with 3-way majority vote encoding, so 5426 that bits can be set independently. This OTP location is 5427 always readable, and is write-protected by its own permissions. */ 5428 __IOM uint32_t PAGE26_LOCK0; /*!< Lock configuration LSBs for page 26 (rows 0x680 through 0x6bf). 5429 Locks are stored with 3-way majority vote encoding, so 5430 that bits can be set independently. This OTP location is 5431 always readable, and is write-protected by its own permissions. */ 5432 __IOM uint32_t PAGE26_LOCK1; /*!< Lock configuration MSBs for page 26 (rows 0x680 through 0x6bf). 5433 Locks are stored with 3-way majority vote encoding, so 5434 that bits can be set independently. This OTP location is 5435 always readable, and is write-protected by its own permissions. */ 5436 __IOM uint32_t PAGE27_LOCK0; /*!< Lock configuration LSBs for page 27 (rows 0x6c0 through 0x6ff). 5437 Locks are stored with 3-way majority vote encoding, so 5438 that bits can be set independently. This OTP location is 5439 always readable, and is write-protected by its own permissions. */ 5440 __IOM uint32_t PAGE27_LOCK1; /*!< Lock configuration MSBs for page 27 (rows 0x6c0 through 0x6ff). 5441 Locks are stored with 3-way majority vote encoding, so 5442 that bits can be set independently. This OTP location is 5443 always readable, and is write-protected by its own permissions. */ 5444 __IOM uint32_t PAGE28_LOCK0; /*!< Lock configuration LSBs for page 28 (rows 0x700 through 0x73f). 5445 Locks are stored with 3-way majority vote encoding, so 5446 that bits can be set independently. This OTP location is 5447 always readable, and is write-protected by its own permissions. */ 5448 __IOM uint32_t PAGE28_LOCK1; /*!< Lock configuration MSBs for page 28 (rows 0x700 through 0x73f). 5449 Locks are stored with 3-way majority vote encoding, so 5450 that bits can be set independently. This OTP location is 5451 always readable, and is write-protected by its own permissions. */ 5452 __IOM uint32_t PAGE29_LOCK0; /*!< Lock configuration LSBs for page 29 (rows 0x740 through 0x77f). 5453 Locks are stored with 3-way majority vote encoding, so 5454 that bits can be set independently. This OTP location is 5455 always readable, and is write-protected by its own permissions. */ 5456 __IOM uint32_t PAGE29_LOCK1; /*!< Lock configuration MSBs for page 29 (rows 0x740 through 0x77f). 5457 Locks are stored with 3-way majority vote encoding, so 5458 that bits can be set independently. This OTP location is 5459 always readable, and is write-protected by its own permissions. */ 5460 __IOM uint32_t PAGE30_LOCK0; /*!< Lock configuration LSBs for page 30 (rows 0x780 through 0x7bf). 5461 Locks are stored with 3-way majority vote encoding, so 5462 that bits can be set independently. This OTP location is 5463 always readable, and is write-protected by its own permissions. */ 5464 __IOM uint32_t PAGE30_LOCK1; /*!< Lock configuration MSBs for page 30 (rows 0x780 through 0x7bf). 5465 Locks are stored with 3-way majority vote encoding, so 5466 that bits can be set independently. This OTP location is 5467 always readable, and is write-protected by its own permissions. */ 5468 __IOM uint32_t PAGE31_LOCK0; /*!< Lock configuration LSBs for page 31 (rows 0x7c0 through 0x7ff). 5469 Locks are stored with 3-way majority vote encoding, so 5470 that bits can be set independently. This OTP location is 5471 always readable, and is write-protected by its own permissions. */ 5472 __IOM uint32_t PAGE31_LOCK1; /*!< Lock configuration MSBs for page 31 (rows 0x7c0 through 0x7ff). 5473 Locks are stored with 3-way majority vote encoding, so 5474 that bits can be set independently. This OTP location is 5475 always readable, and is write-protected by its own permissions. */ 5476 __IOM uint32_t PAGE32_LOCK0; /*!< Lock configuration LSBs for page 32 (rows 0x800 through 0x83f). 5477 Locks are stored with 3-way majority vote encoding, so 5478 that bits can be set independently. This OTP location is 5479 always readable, and is write-protected by its own permissions. */ 5480 __IOM uint32_t PAGE32_LOCK1; /*!< Lock configuration MSBs for page 32 (rows 0x800 through 0x83f). 5481 Locks are stored with 3-way majority vote encoding, so 5482 that bits can be set independently. This OTP location is 5483 always readable, and is write-protected by its own permissions. */ 5484 __IOM uint32_t PAGE33_LOCK0; /*!< Lock configuration LSBs for page 33 (rows 0x840 through 0x87f). 5485 Locks are stored with 3-way majority vote encoding, so 5486 that bits can be set independently. This OTP location is 5487 always readable, and is write-protected by its own permissions. */ 5488 __IOM uint32_t PAGE33_LOCK1; /*!< Lock configuration MSBs for page 33 (rows 0x840 through 0x87f). 5489 Locks are stored with 3-way majority vote encoding, so 5490 that bits can be set independently. This OTP location is 5491 always readable, and is write-protected by its own permissions. */ 5492 __IOM uint32_t PAGE34_LOCK0; /*!< Lock configuration LSBs for page 34 (rows 0x880 through 0x8bf). 5493 Locks are stored with 3-way majority vote encoding, so 5494 that bits can be set independently. This OTP location is 5495 always readable, and is write-protected by its own permissions. */ 5496 __IOM uint32_t PAGE34_LOCK1; /*!< Lock configuration MSBs for page 34 (rows 0x880 through 0x8bf). 5497 Locks are stored with 3-way majority vote encoding, so 5498 that bits can be set independently. This OTP location is 5499 always readable, and is write-protected by its own permissions. */ 5500 __IOM uint32_t PAGE35_LOCK0; /*!< Lock configuration LSBs for page 35 (rows 0x8c0 through 0x8ff). 5501 Locks are stored with 3-way majority vote encoding, so 5502 that bits can be set independently. This OTP location is 5503 always readable, and is write-protected by its own permissions. */ 5504 __IOM uint32_t PAGE35_LOCK1; /*!< Lock configuration MSBs for page 35 (rows 0x8c0 through 0x8ff). 5505 Locks are stored with 3-way majority vote encoding, so 5506 that bits can be set independently. This OTP location is 5507 always readable, and is write-protected by its own permissions. */ 5508 __IOM uint32_t PAGE36_LOCK0; /*!< Lock configuration LSBs for page 36 (rows 0x900 through 0x93f). 5509 Locks are stored with 3-way majority vote encoding, so 5510 that bits can be set independently. This OTP location is 5511 always readable, and is write-protected by its own permissions. */ 5512 __IOM uint32_t PAGE36_LOCK1; /*!< Lock configuration MSBs for page 36 (rows 0x900 through 0x93f). 5513 Locks are stored with 3-way majority vote encoding, so 5514 that bits can be set independently. This OTP location is 5515 always readable, and is write-protected by its own permissions. */ 5516 __IOM uint32_t PAGE37_LOCK0; /*!< Lock configuration LSBs for page 37 (rows 0x940 through 0x97f). 5517 Locks are stored with 3-way majority vote encoding, so 5518 that bits can be set independently. This OTP location is 5519 always readable, and is write-protected by its own permissions. */ 5520 __IOM uint32_t PAGE37_LOCK1; /*!< Lock configuration MSBs for page 37 (rows 0x940 through 0x97f). 5521 Locks are stored with 3-way majority vote encoding, so 5522 that bits can be set independently. This OTP location is 5523 always readable, and is write-protected by its own permissions. */ 5524 __IOM uint32_t PAGE38_LOCK0; /*!< Lock configuration LSBs for page 38 (rows 0x980 through 0x9bf). 5525 Locks are stored with 3-way majority vote encoding, so 5526 that bits can be set independently. This OTP location is 5527 always readable, and is write-protected by its own permissions. */ 5528 __IOM uint32_t PAGE38_LOCK1; /*!< Lock configuration MSBs for page 38 (rows 0x980 through 0x9bf). 5529 Locks are stored with 3-way majority vote encoding, so 5530 that bits can be set independently. This OTP location is 5531 always readable, and is write-protected by its own permissions. */ 5532 __IOM uint32_t PAGE39_LOCK0; /*!< Lock configuration LSBs for page 39 (rows 0x9c0 through 0x9ff). 5533 Locks are stored with 3-way majority vote encoding, so 5534 that bits can be set independently. This OTP location is 5535 always readable, and is write-protected by its own permissions. */ 5536 __IOM uint32_t PAGE39_LOCK1; /*!< Lock configuration MSBs for page 39 (rows 0x9c0 through 0x9ff). 5537 Locks are stored with 3-way majority vote encoding, so 5538 that bits can be set independently. This OTP location is 5539 always readable, and is write-protected by its own permissions. */ 5540 __IOM uint32_t PAGE40_LOCK0; /*!< Lock configuration LSBs for page 40 (rows 0xa00 through 0xa3f). 5541 Locks are stored with 3-way majority vote encoding, so 5542 that bits can be set independently. This OTP location is 5543 always readable, and is write-protected by its own permissions. */ 5544 __IOM uint32_t PAGE40_LOCK1; /*!< Lock configuration MSBs for page 40 (rows 0xa00 through 0xa3f). 5545 Locks are stored with 3-way majority vote encoding, so 5546 that bits can be set independently. This OTP location is 5547 always readable, and is write-protected by its own permissions. */ 5548 __IOM uint32_t PAGE41_LOCK0; /*!< Lock configuration LSBs for page 41 (rows 0xa40 through 0xa7f). 5549 Locks are stored with 3-way majority vote encoding, so 5550 that bits can be set independently. This OTP location is 5551 always readable, and is write-protected by its own permissions. */ 5552 __IOM uint32_t PAGE41_LOCK1; /*!< Lock configuration MSBs for page 41 (rows 0xa40 through 0xa7f). 5553 Locks are stored with 3-way majority vote encoding, so 5554 that bits can be set independently. This OTP location is 5555 always readable, and is write-protected by its own permissions. */ 5556 __IOM uint32_t PAGE42_LOCK0; /*!< Lock configuration LSBs for page 42 (rows 0xa80 through 0xabf). 5557 Locks are stored with 3-way majority vote encoding, so 5558 that bits can be set independently. This OTP location is 5559 always readable, and is write-protected by its own permissions. */ 5560 __IOM uint32_t PAGE42_LOCK1; /*!< Lock configuration MSBs for page 42 (rows 0xa80 through 0xabf). 5561 Locks are stored with 3-way majority vote encoding, so 5562 that bits can be set independently. This OTP location is 5563 always readable, and is write-protected by its own permissions. */ 5564 __IOM uint32_t PAGE43_LOCK0; /*!< Lock configuration LSBs for page 43 (rows 0xac0 through 0xaff). 5565 Locks are stored with 3-way majority vote encoding, so 5566 that bits can be set independently. This OTP location is 5567 always readable, and is write-protected by its own permissions. */ 5568 __IOM uint32_t PAGE43_LOCK1; /*!< Lock configuration MSBs for page 43 (rows 0xac0 through 0xaff). 5569 Locks are stored with 3-way majority vote encoding, so 5570 that bits can be set independently. This OTP location is 5571 always readable, and is write-protected by its own permissions. */ 5572 __IOM uint32_t PAGE44_LOCK0; /*!< Lock configuration LSBs for page 44 (rows 0xb00 through 0xb3f). 5573 Locks are stored with 3-way majority vote encoding, so 5574 that bits can be set independently. This OTP location is 5575 always readable, and is write-protected by its own permissions. */ 5576 __IOM uint32_t PAGE44_LOCK1; /*!< Lock configuration MSBs for page 44 (rows 0xb00 through 0xb3f). 5577 Locks are stored with 3-way majority vote encoding, so 5578 that bits can be set independently. This OTP location is 5579 always readable, and is write-protected by its own permissions. */ 5580 __IOM uint32_t PAGE45_LOCK0; /*!< Lock configuration LSBs for page 45 (rows 0xb40 through 0xb7f). 5581 Locks are stored with 3-way majority vote encoding, so 5582 that bits can be set independently. This OTP location is 5583 always readable, and is write-protected by its own permissions. */ 5584 __IOM uint32_t PAGE45_LOCK1; /*!< Lock configuration MSBs for page 45 (rows 0xb40 through 0xb7f). 5585 Locks are stored with 3-way majority vote encoding, so 5586 that bits can be set independently. This OTP location is 5587 always readable, and is write-protected by its own permissions. */ 5588 __IOM uint32_t PAGE46_LOCK0; /*!< Lock configuration LSBs for page 46 (rows 0xb80 through 0xbbf). 5589 Locks are stored with 3-way majority vote encoding, so 5590 that bits can be set independently. This OTP location is 5591 always readable, and is write-protected by its own permissions. */ 5592 __IOM uint32_t PAGE46_LOCK1; /*!< Lock configuration MSBs for page 46 (rows 0xb80 through 0xbbf). 5593 Locks are stored with 3-way majority vote encoding, so 5594 that bits can be set independently. This OTP location is 5595 always readable, and is write-protected by its own permissions. */ 5596 __IOM uint32_t PAGE47_LOCK0; /*!< Lock configuration LSBs for page 47 (rows 0xbc0 through 0xbff). 5597 Locks are stored with 3-way majority vote encoding, so 5598 that bits can be set independently. This OTP location is 5599 always readable, and is write-protected by its own permissions. */ 5600 __IOM uint32_t PAGE47_LOCK1; /*!< Lock configuration MSBs for page 47 (rows 0xbc0 through 0xbff). 5601 Locks are stored with 3-way majority vote encoding, so 5602 that bits can be set independently. This OTP location is 5603 always readable, and is write-protected by its own permissions. */ 5604 __IOM uint32_t PAGE48_LOCK0; /*!< Lock configuration LSBs for page 48 (rows 0xc00 through 0xc3f). 5605 Locks are stored with 3-way majority vote encoding, so 5606 that bits can be set independently. This OTP location is 5607 always readable, and is write-protected by its own permissions. */ 5608 __IOM uint32_t PAGE48_LOCK1; /*!< Lock configuration MSBs for page 48 (rows 0xc00 through 0xc3f). 5609 Locks are stored with 3-way majority vote encoding, so 5610 that bits can be set independently. This OTP location is 5611 always readable, and is write-protected by its own permissions. */ 5612 __IOM uint32_t PAGE49_LOCK0; /*!< Lock configuration LSBs for page 49 (rows 0xc40 through 0xc7f). 5613 Locks are stored with 3-way majority vote encoding, so 5614 that bits can be set independently. This OTP location is 5615 always readable, and is write-protected by its own permissions. */ 5616 __IOM uint32_t PAGE49_LOCK1; /*!< Lock configuration MSBs for page 49 (rows 0xc40 through 0xc7f). 5617 Locks are stored with 3-way majority vote encoding, so 5618 that bits can be set independently. This OTP location is 5619 always readable, and is write-protected by its own permissions. */ 5620 __IOM uint32_t PAGE50_LOCK0; /*!< Lock configuration LSBs for page 50 (rows 0xc80 through 0xcbf). 5621 Locks are stored with 3-way majority vote encoding, so 5622 that bits can be set independently. This OTP location is 5623 always readable, and is write-protected by its own permissions. */ 5624 __IOM uint32_t PAGE50_LOCK1; /*!< Lock configuration MSBs for page 50 (rows 0xc80 through 0xcbf). 5625 Locks are stored with 3-way majority vote encoding, so 5626 that bits can be set independently. This OTP location is 5627 always readable, and is write-protected by its own permissions. */ 5628 __IOM uint32_t PAGE51_LOCK0; /*!< Lock configuration LSBs for page 51 (rows 0xcc0 through 0xcff). 5629 Locks are stored with 3-way majority vote encoding, so 5630 that bits can be set independently. This OTP location is 5631 always readable, and is write-protected by its own permissions. */ 5632 __IOM uint32_t PAGE51_LOCK1; /*!< Lock configuration MSBs for page 51 (rows 0xcc0 through 0xcff). 5633 Locks are stored with 3-way majority vote encoding, so 5634 that bits can be set independently. This OTP location is 5635 always readable, and is write-protected by its own permissions. */ 5636 __IOM uint32_t PAGE52_LOCK0; /*!< Lock configuration LSBs for page 52 (rows 0xd00 through 0xd3f). 5637 Locks are stored with 3-way majority vote encoding, so 5638 that bits can be set independently. This OTP location is 5639 always readable, and is write-protected by its own permissions. */ 5640 __IOM uint32_t PAGE52_LOCK1; /*!< Lock configuration MSBs for page 52 (rows 0xd00 through 0xd3f). 5641 Locks are stored with 3-way majority vote encoding, so 5642 that bits can be set independently. This OTP location is 5643 always readable, and is write-protected by its own permissions. */ 5644 __IOM uint32_t PAGE53_LOCK0; /*!< Lock configuration LSBs for page 53 (rows 0xd40 through 0xd7f). 5645 Locks are stored with 3-way majority vote encoding, so 5646 that bits can be set independently. This OTP location is 5647 always readable, and is write-protected by its own permissions. */ 5648 __IOM uint32_t PAGE53_LOCK1; /*!< Lock configuration MSBs for page 53 (rows 0xd40 through 0xd7f). 5649 Locks are stored with 3-way majority vote encoding, so 5650 that bits can be set independently. This OTP location is 5651 always readable, and is write-protected by its own permissions. */ 5652 __IOM uint32_t PAGE54_LOCK0; /*!< Lock configuration LSBs for page 54 (rows 0xd80 through 0xdbf). 5653 Locks are stored with 3-way majority vote encoding, so 5654 that bits can be set independently. This OTP location is 5655 always readable, and is write-protected by its own permissions. */ 5656 __IOM uint32_t PAGE54_LOCK1; /*!< Lock configuration MSBs for page 54 (rows 0xd80 through 0xdbf). 5657 Locks are stored with 3-way majority vote encoding, so 5658 that bits can be set independently. This OTP location is 5659 always readable, and is write-protected by its own permissions. */ 5660 __IOM uint32_t PAGE55_LOCK0; /*!< Lock configuration LSBs for page 55 (rows 0xdc0 through 0xdff). 5661 Locks are stored with 3-way majority vote encoding, so 5662 that bits can be set independently. This OTP location is 5663 always readable, and is write-protected by its own permissions. */ 5664 __IOM uint32_t PAGE55_LOCK1; /*!< Lock configuration MSBs for page 55 (rows 0xdc0 through 0xdff). 5665 Locks are stored with 3-way majority vote encoding, so 5666 that bits can be set independently. This OTP location is 5667 always readable, and is write-protected by its own permissions. */ 5668 __IOM uint32_t PAGE56_LOCK0; /*!< Lock configuration LSBs for page 56 (rows 0xe00 through 0xe3f). 5669 Locks are stored with 3-way majority vote encoding, so 5670 that bits can be set independently. This OTP location is 5671 always readable, and is write-protected by its own permissions. */ 5672 __IOM uint32_t PAGE56_LOCK1; /*!< Lock configuration MSBs for page 56 (rows 0xe00 through 0xe3f). 5673 Locks are stored with 3-way majority vote encoding, so 5674 that bits can be set independently. This OTP location is 5675 always readable, and is write-protected by its own permissions. */ 5676 __IOM uint32_t PAGE57_LOCK0; /*!< Lock configuration LSBs for page 57 (rows 0xe40 through 0xe7f). 5677 Locks are stored with 3-way majority vote encoding, so 5678 that bits can be set independently. This OTP location is 5679 always readable, and is write-protected by its own permissions. */ 5680 __IOM uint32_t PAGE57_LOCK1; /*!< Lock configuration MSBs for page 57 (rows 0xe40 through 0xe7f). 5681 Locks are stored with 3-way majority vote encoding, so 5682 that bits can be set independently. This OTP location is 5683 always readable, and is write-protected by its own permissions. */ 5684 __IOM uint32_t PAGE58_LOCK0; /*!< Lock configuration LSBs for page 58 (rows 0xe80 through 0xebf). 5685 Locks are stored with 3-way majority vote encoding, so 5686 that bits can be set independently. This OTP location is 5687 always readable, and is write-protected by its own permissions. */ 5688 __IOM uint32_t PAGE58_LOCK1; /*!< Lock configuration MSBs for page 58 (rows 0xe80 through 0xebf). 5689 Locks are stored with 3-way majority vote encoding, so 5690 that bits can be set independently. This OTP location is 5691 always readable, and is write-protected by its own permissions. */ 5692 __IOM uint32_t PAGE59_LOCK0; /*!< Lock configuration LSBs for page 59 (rows 0xec0 through 0xeff). 5693 Locks are stored with 3-way majority vote encoding, so 5694 that bits can be set independently. This OTP location is 5695 always readable, and is write-protected by its own permissions. */ 5696 __IOM uint32_t PAGE59_LOCK1; /*!< Lock configuration MSBs for page 59 (rows 0xec0 through 0xeff). 5697 Locks are stored with 3-way majority vote encoding, so 5698 that bits can be set independently. This OTP location is 5699 always readable, and is write-protected by its own permissions. */ 5700 __IOM uint32_t PAGE60_LOCK0; /*!< Lock configuration LSBs for page 60 (rows 0xf00 through 0xf3f). 5701 Locks are stored with 3-way majority vote encoding, so 5702 that bits can be set independently. This OTP location is 5703 always readable, and is write-protected by its own permissions. */ 5704 __IOM uint32_t PAGE60_LOCK1; /*!< Lock configuration MSBs for page 60 (rows 0xf00 through 0xf3f). 5705 Locks are stored with 3-way majority vote encoding, so 5706 that bits can be set independently. This OTP location is 5707 always readable, and is write-protected by its own permissions. */ 5708 __IOM uint32_t PAGE61_LOCK0; /*!< Lock configuration LSBs for page 61 (rows 0xf40 through 0xf7f). 5709 Locks are stored with 3-way majority vote encoding, so 5710 that bits can be set independently. This OTP location is 5711 always readable, and is write-protected by its own permissions. */ 5712 __IOM uint32_t PAGE61_LOCK1; /*!< Lock configuration MSBs for page 61 (rows 0xf40 through 0xf7f). 5713 Locks are stored with 3-way majority vote encoding, so 5714 that bits can be set independently. This OTP location is 5715 always readable, and is write-protected by its own permissions. */ 5716 __IOM uint32_t PAGE62_LOCK0; /*!< Lock configuration LSBs for page 62 (rows 0xf80 through 0xfbf). 5717 Locks are stored with 3-way majority vote encoding, so 5718 that bits can be set independently. This OTP location is 5719 always readable, and is write-protected by its own permissions. */ 5720 __IOM uint32_t PAGE62_LOCK1; /*!< Lock configuration MSBs for page 62 (rows 0xf80 through 0xfbf). 5721 Locks are stored with 3-way majority vote encoding, so 5722 that bits can be set independently. This OTP location is 5723 always readable, and is write-protected by its own permissions. */ 5724 __IOM uint32_t PAGE63_LOCK0; /*!< Lock configuration LSBs for page 63 (rows 0xfc0 through 0xfff). 5725 Locks are stored with 3-way majority vote encoding, so 5726 that bits can be set independently. This OTP location is 5727 always readable, and is write-protected by its own permissions. */ 5728 __IOM uint32_t PAGE63_LOCK1; /*!< Lock configuration MSBs for page 63 (rows 0xfc0 through 0xfff). 5729 Locks are stored with 3-way majority vote encoding, so 5730 that bits can be set independently. This OTP location is 5731 always readable, and is write-protected by its own permissions. */ 5732 } OTP_DATA_RAW_Type; /*!< Size = 16384 (0x4000) */ 5733 5734 5735 5736 /* =========================================================================================================================== */ 5737 /* ================ TBMAN ================ */ 5738 /* =========================================================================================================================== */ 5739 5740 5741 /** 5742 * @brief For managing simulation testbenches (TBMAN) 5743 */ 5744 5745 typedef struct { /*!< TBMAN Structure */ 5746 __IOM uint32_t PLATFORM; /*!< Indicates the type of platform in use */ 5747 } TBMAN_Type; /*!< Size = 4 (0x4) */ 5748 5749 5750 5751 /* =========================================================================================================================== */ 5752 /* ================ USB_DPRAM ================ */ 5753 /* =========================================================================================================================== */ 5754 5755 5756 /** 5757 * @brief DPRAM layout for USB device. (USB_DPRAM) 5758 */ 5759 5760 typedef struct { /*!< USB_DPRAM Structure */ 5761 __IOM uint32_t SETUP_PACKET_LOW; /*!< Bytes 0-3 of the SETUP packet from the host. */ 5762 __IOM uint32_t SETUP_PACKET_HIGH; /*!< Bytes 4-7 of the setup packet from the host. */ 5763 __IOM uint32_t EP1_IN_CONTROL; /*!< EP1_IN_CONTROL */ 5764 __IOM uint32_t EP1_OUT_CONTROL; /*!< EP1_OUT_CONTROL */ 5765 __IOM uint32_t EP2_IN_CONTROL; /*!< EP2_IN_CONTROL */ 5766 __IOM uint32_t EP2_OUT_CONTROL; /*!< EP2_OUT_CONTROL */ 5767 __IOM uint32_t EP3_IN_CONTROL; /*!< EP3_IN_CONTROL */ 5768 __IOM uint32_t EP3_OUT_CONTROL; /*!< EP3_OUT_CONTROL */ 5769 __IOM uint32_t EP4_IN_CONTROL; /*!< EP4_IN_CONTROL */ 5770 __IOM uint32_t EP4_OUT_CONTROL; /*!< EP4_OUT_CONTROL */ 5771 __IOM uint32_t EP5_IN_CONTROL; /*!< EP5_IN_CONTROL */ 5772 __IOM uint32_t EP5_OUT_CONTROL; /*!< EP5_OUT_CONTROL */ 5773 __IOM uint32_t EP6_IN_CONTROL; /*!< EP6_IN_CONTROL */ 5774 __IOM uint32_t EP6_OUT_CONTROL; /*!< EP6_OUT_CONTROL */ 5775 __IOM uint32_t EP7_IN_CONTROL; /*!< EP7_IN_CONTROL */ 5776 __IOM uint32_t EP7_OUT_CONTROL; /*!< EP7_OUT_CONTROL */ 5777 __IOM uint32_t EP8_IN_CONTROL; /*!< EP8_IN_CONTROL */ 5778 __IOM uint32_t EP8_OUT_CONTROL; /*!< EP8_OUT_CONTROL */ 5779 __IOM uint32_t EP9_IN_CONTROL; /*!< EP9_IN_CONTROL */ 5780 __IOM uint32_t EP9_OUT_CONTROL; /*!< EP9_OUT_CONTROL */ 5781 __IOM uint32_t EP10_IN_CONTROL; /*!< EP10_IN_CONTROL */ 5782 __IOM uint32_t EP10_OUT_CONTROL; /*!< EP10_OUT_CONTROL */ 5783 __IOM uint32_t EP11_IN_CONTROL; /*!< EP11_IN_CONTROL */ 5784 __IOM uint32_t EP11_OUT_CONTROL; /*!< EP11_OUT_CONTROL */ 5785 __IOM uint32_t EP12_IN_CONTROL; /*!< EP12_IN_CONTROL */ 5786 __IOM uint32_t EP12_OUT_CONTROL; /*!< EP12_OUT_CONTROL */ 5787 __IOM uint32_t EP13_IN_CONTROL; /*!< EP13_IN_CONTROL */ 5788 __IOM uint32_t EP13_OUT_CONTROL; /*!< EP13_OUT_CONTROL */ 5789 __IOM uint32_t EP14_IN_CONTROL; /*!< EP14_IN_CONTROL */ 5790 __IOM uint32_t EP14_OUT_CONTROL; /*!< EP14_OUT_CONTROL */ 5791 __IOM uint32_t EP15_IN_CONTROL; /*!< EP15_IN_CONTROL */ 5792 __IOM uint32_t EP15_OUT_CONTROL; /*!< EP15_OUT_CONTROL */ 5793 __IOM uint32_t EP0_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5794 in a _1 are for buffer 1. Fields ending in a _0 are for 5795 buffer 0. Buffer 1 controls are only valid if the endpoint 5796 is in double buffered mode. */ 5797 __IOM uint32_t EP0_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5798 in a _1 are for buffer 1. Fields ending in a _0 are for 5799 buffer 0. Buffer 1 controls are only valid if the endpoint 5800 is in double buffered mode. */ 5801 __IOM uint32_t EP1_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5802 in a _1 are for buffer 1. Fields ending in a _0 are for 5803 buffer 0. Buffer 1 controls are only valid if the endpoint 5804 is in double buffered mode. */ 5805 __IOM uint32_t EP1_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5806 in a _1 are for buffer 1. Fields ending in a _0 are for 5807 buffer 0. Buffer 1 controls are only valid if the endpoint 5808 is in double buffered mode. */ 5809 __IOM uint32_t EP2_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5810 in a _1 are for buffer 1. Fields ending in a _0 are for 5811 buffer 0. Buffer 1 controls are only valid if the endpoint 5812 is in double buffered mode. */ 5813 __IOM uint32_t EP2_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5814 in a _1 are for buffer 1. Fields ending in a _0 are for 5815 buffer 0. Buffer 1 controls are only valid if the endpoint 5816 is in double buffered mode. */ 5817 __IOM uint32_t EP3_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5818 in a _1 are for buffer 1. Fields ending in a _0 are for 5819 buffer 0. Buffer 1 controls are only valid if the endpoint 5820 is in double buffered mode. */ 5821 __IOM uint32_t EP3_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5822 in a _1 are for buffer 1. Fields ending in a _0 are for 5823 buffer 0. Buffer 1 controls are only valid if the endpoint 5824 is in double buffered mode. */ 5825 __IOM uint32_t EP4_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5826 in a _1 are for buffer 1. Fields ending in a _0 are for 5827 buffer 0. Buffer 1 controls are only valid if the endpoint 5828 is in double buffered mode. */ 5829 __IOM uint32_t EP4_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5830 in a _1 are for buffer 1. Fields ending in a _0 are for 5831 buffer 0. Buffer 1 controls are only valid if the endpoint 5832 is in double buffered mode. */ 5833 __IOM uint32_t EP5_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5834 in a _1 are for buffer 1. Fields ending in a _0 are for 5835 buffer 0. Buffer 1 controls are only valid if the endpoint 5836 is in double buffered mode. */ 5837 __IOM uint32_t EP5_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5838 in a _1 are for buffer 1. Fields ending in a _0 are for 5839 buffer 0. Buffer 1 controls are only valid if the endpoint 5840 is in double buffered mode. */ 5841 __IOM uint32_t EP6_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5842 in a _1 are for buffer 1. Fields ending in a _0 are for 5843 buffer 0. Buffer 1 controls are only valid if the endpoint 5844 is in double buffered mode. */ 5845 __IOM uint32_t EP6_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5846 in a _1 are for buffer 1. Fields ending in a _0 are for 5847 buffer 0. Buffer 1 controls are only valid if the endpoint 5848 is in double buffered mode. */ 5849 __IOM uint32_t EP7_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5850 in a _1 are for buffer 1. Fields ending in a _0 are for 5851 buffer 0. Buffer 1 controls are only valid if the endpoint 5852 is in double buffered mode. */ 5853 __IOM uint32_t EP7_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5854 in a _1 are for buffer 1. Fields ending in a _0 are for 5855 buffer 0. Buffer 1 controls are only valid if the endpoint 5856 is in double buffered mode. */ 5857 __IOM uint32_t EP8_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5858 in a _1 are for buffer 1. Fields ending in a _0 are for 5859 buffer 0. Buffer 1 controls are only valid if the endpoint 5860 is in double buffered mode. */ 5861 __IOM uint32_t EP8_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5862 in a _1 are for buffer 1. Fields ending in a _0 are for 5863 buffer 0. Buffer 1 controls are only valid if the endpoint 5864 is in double buffered mode. */ 5865 __IOM uint32_t EP9_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5866 in a _1 are for buffer 1. Fields ending in a _0 are for 5867 buffer 0. Buffer 1 controls are only valid if the endpoint 5868 is in double buffered mode. */ 5869 __IOM uint32_t EP9_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5870 in a _1 are for buffer 1. Fields ending in a _0 are for 5871 buffer 0. Buffer 1 controls are only valid if the endpoint 5872 is in double buffered mode. */ 5873 __IOM uint32_t EP10_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5874 in a _1 are for buffer 1. Fields ending in a _0 are for 5875 buffer 0. Buffer 1 controls are only valid if the endpoint 5876 is in double buffered mode. */ 5877 __IOM uint32_t EP10_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5878 in a _1 are for buffer 1. Fields ending in a _0 are for 5879 buffer 0. Buffer 1 controls are only valid if the endpoint 5880 is in double buffered mode. */ 5881 __IOM uint32_t EP11_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5882 in a _1 are for buffer 1. Fields ending in a _0 are for 5883 buffer 0. Buffer 1 controls are only valid if the endpoint 5884 is in double buffered mode. */ 5885 __IOM uint32_t EP11_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5886 in a _1 are for buffer 1. Fields ending in a _0 are for 5887 buffer 0. Buffer 1 controls are only valid if the endpoint 5888 is in double buffered mode. */ 5889 __IOM uint32_t EP12_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5890 in a _1 are for buffer 1. Fields ending in a _0 are for 5891 buffer 0. Buffer 1 controls are only valid if the endpoint 5892 is in double buffered mode. */ 5893 __IOM uint32_t EP12_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5894 in a _1 are for buffer 1. Fields ending in a _0 are for 5895 buffer 0. Buffer 1 controls are only valid if the endpoint 5896 is in double buffered mode. */ 5897 __IOM uint32_t EP13_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5898 in a _1 are for buffer 1. Fields ending in a _0 are for 5899 buffer 0. Buffer 1 controls are only valid if the endpoint 5900 is in double buffered mode. */ 5901 __IOM uint32_t EP13_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5902 in a _1 are for buffer 1. Fields ending in a _0 are for 5903 buffer 0. Buffer 1 controls are only valid if the endpoint 5904 is in double buffered mode. */ 5905 __IOM uint32_t EP14_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5906 in a _1 are for buffer 1. Fields ending in a _0 are for 5907 buffer 0. Buffer 1 controls are only valid if the endpoint 5908 is in double buffered mode. */ 5909 __IOM uint32_t EP14_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5910 in a _1 are for buffer 1. Fields ending in a _0 are for 5911 buffer 0. Buffer 1 controls are only valid if the endpoint 5912 is in double buffered mode. */ 5913 __IOM uint32_t EP15_IN_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5914 in a _1 are for buffer 1. Fields ending in a _0 are for 5915 buffer 0. Buffer 1 controls are only valid if the endpoint 5916 is in double buffered mode. */ 5917 __IOM uint32_t EP15_OUT_BUFFER_CONTROL; /*!< Buffer control for both buffers of an endpoint. Fields ending 5918 in a _1 are for buffer 1. Fields ending in a _0 are for 5919 buffer 0. Buffer 1 controls are only valid if the endpoint 5920 is in double buffered mode. */ 5921 } USB_DPRAM_Type; /*!< Size = 256 (0x100) */ 5922 5923 5924 /** @} */ /* End of group Device_Peripheral_peripherals */ 5925 5926 5927 /* =========================================================================================================================== */ 5928 /* ================ Device Specific Peripheral Address Map ================ */ 5929 /* =========================================================================================================================== */ 5930 5931 5932 /** @addtogroup Device_Peripheral_peripheralAddr 5933 * @{ 5934 */ 5935 5936 #define RESETS_BASE 0x40020000UL 5937 #define PSM_BASE 0x40018000UL 5938 #define CLOCKS_BASE 0x40010000UL 5939 #define TICKS_BASE 0x40108000UL 5940 #define PADS_BANK0_BASE 0x40038000UL 5941 #define PADS_QSPI_BASE 0x40040000UL 5942 #define IO_QSPI_BASE 0x40030000UL 5943 #define IO_BANK0_BASE 0x40028000UL 5944 #define SYSINFO_BASE 0x40000000UL 5945 #define SHA256_BASE 0x400F8000UL 5946 #define HSTX_FIFO_BASE 0x50600000UL 5947 #define HSTX_CTRL_BASE 0x400C0000UL 5948 #define EPPB_BASE 0xE0080000UL 5949 #define PPB_BASE 0xE0000000UL 5950 #define PPB_NS_BASE 0xE0020000UL 5951 #define QMI_BASE 0x400D0000UL 5952 #define XIP_CTRL_BASE 0x400C8000UL 5953 #define XIP_AUX_BASE 0x50500000UL 5954 #define SYSCFG_BASE 0x40008000UL 5955 #define XOSC_BASE 0x40048000UL 5956 #define PLL_SYS_BASE 0x40050000UL 5957 #define PLL_USB_BASE 0x40058000UL 5958 #define ACCESSCTRL_BASE 0x40060000UL 5959 #define UART0_BASE 0x40070000UL 5960 #define UART1_BASE 0x40078000UL 5961 #define ROSC_BASE 0x400E8000UL 5962 #define POWMAN_BASE 0x40100000UL 5963 #define WATCHDOG_BASE 0x400D8000UL 5964 #define DMA_BASE 0x50000000UL 5965 #define TIMER0_BASE 0x400B0000UL 5966 #define TIMER1_BASE 0x400B8000UL 5967 #define PWM_BASE 0x400A8000UL 5968 #define ADC_BASE 0x400A0000UL 5969 #define I2C0_BASE 0x40090000UL 5970 #define I2C1_BASE 0x40098000UL 5971 #define SPI0_BASE 0x40080000UL 5972 #define SPI1_BASE 0x40088000UL 5973 #define PIO0_BASE 0x50200000UL 5974 #define PIO1_BASE 0x50300000UL 5975 #define PIO2_BASE 0x50400000UL 5976 #define BUSCTRL_BASE 0x40068000UL 5977 #define SIO_BASE 0xD0000000UL 5978 #define SIO_NS_BASE 0xD0020000UL 5979 #define BOOTRAM_BASE 0x400E0000UL 5980 #define CORESIGHT_TRACE_BASE 0x50700000UL 5981 #define USB_BASE 0x50110000UL 5982 #define TRNG_BASE 0x400F0000UL 5983 #define GLITCH_DETECTOR_BASE 0x40158000UL 5984 #define OTP_BASE 0x40120000UL 5985 #define OTP_DATA_BASE 0x40130000UL 5986 #define OTP_DATA_RAW_BASE 0x40134000UL 5987 #define TBMAN_BASE 0x40160000UL 5988 #define USB_DPRAM_BASE 0x50100000UL 5989 5990 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 5991 5992 5993 /* =========================================================================================================================== */ 5994 /* ================ Peripheral declaration ================ */ 5995 /* =========================================================================================================================== */ 5996 5997 5998 /** @addtogroup Device_Peripheral_declaration 5999 * @{ 6000 */ 6001 6002 #define RESETS ((RESETS_Type*) RESETS_BASE) 6003 #define PSM ((PSM_Type*) PSM_BASE) 6004 #define CLOCKS ((CLOCKS_Type*) CLOCKS_BASE) 6005 #define TICKS ((TICKS_Type*) TICKS_BASE) 6006 #define PADS_BANK0 ((PADS_BANK0_Type*) PADS_BANK0_BASE) 6007 #define PADS_QSPI ((PADS_QSPI_Type*) PADS_QSPI_BASE) 6008 #define IO_QSPI ((IO_QSPI_Type*) IO_QSPI_BASE) 6009 #define IO_BANK0 ((IO_BANK0_Type*) IO_BANK0_BASE) 6010 #define SYSINFO ((SYSINFO_Type*) SYSINFO_BASE) 6011 #define SHA256 ((SHA256_Type*) SHA256_BASE) 6012 #define HSTX_FIFO ((HSTX_FIFO_Type*) HSTX_FIFO_BASE) 6013 #define HSTX_CTRL ((HSTX_CTRL_Type*) HSTX_CTRL_BASE) 6014 #define EPPB ((EPPB_Type*) EPPB_BASE) 6015 #define PPB ((PPB_Type*) PPB_BASE) 6016 #define PPB_NS ((PPB_Type*) PPB_NS_BASE) 6017 #define QMI ((QMI_Type*) QMI_BASE) 6018 #define XIP_CTRL ((XIP_CTRL_Type*) XIP_CTRL_BASE) 6019 #define XIP_AUX ((XIP_AUX_Type*) XIP_AUX_BASE) 6020 #define SYSCFG ((SYSCFG_Type*) SYSCFG_BASE) 6021 #define XOSC ((XOSC_Type*) XOSC_BASE) 6022 #define PLL_SYS ((PLL_SYS_Type*) PLL_SYS_BASE) 6023 #define PLL_USB ((PLL_SYS_Type*) PLL_USB_BASE) 6024 #define ACCESSCTRL ((ACCESSCTRL_Type*) ACCESSCTRL_BASE) 6025 #define UART0 ((UART0_Type*) UART0_BASE) 6026 #define UART1 ((UART0_Type*) UART1_BASE) 6027 #define ROSC ((ROSC_Type*) ROSC_BASE) 6028 #define POWMAN ((POWMAN_Type*) POWMAN_BASE) 6029 #define WATCHDOG ((WATCHDOG_Type*) WATCHDOG_BASE) 6030 #define DMA ((DMA_Type*) DMA_BASE) 6031 #define TIMER0 ((TIMER0_Type*) TIMER0_BASE) 6032 #define TIMER1 ((TIMER0_Type*) TIMER1_BASE) 6033 #define PWM ((PWM_Type*) PWM_BASE) 6034 #define ADC ((ADC_Type*) ADC_BASE) 6035 #define I2C0 ((I2C0_Type*) I2C0_BASE) 6036 #define I2C1 ((I2C0_Type*) I2C1_BASE) 6037 #define SPI0 ((SPI0_Type*) SPI0_BASE) 6038 #define SPI1 ((SPI0_Type*) SPI1_BASE) 6039 #define PIO0 ((PIO0_Type*) PIO0_BASE) 6040 #define PIO1 ((PIO0_Type*) PIO1_BASE) 6041 #define PIO2 ((PIO0_Type*) PIO2_BASE) 6042 #define BUSCTRL ((BUSCTRL_Type*) BUSCTRL_BASE) 6043 #define SIO ((SIO_Type*) SIO_BASE) 6044 #define SIO_NS ((SIO_Type*) SIO_NS_BASE) 6045 #define BOOTRAM ((BOOTRAM_Type*) BOOTRAM_BASE) 6046 #define CORESIGHT_TRACE ((CORESIGHT_TRACE_Type*) CORESIGHT_TRACE_BASE) 6047 #define USB ((USB_Type*) USB_BASE) 6048 #define TRNG ((TRNG_Type*) TRNG_BASE) 6049 #define GLITCH_DETECTOR ((GLITCH_DETECTOR_Type*) GLITCH_DETECTOR_BASE) 6050 #define OTP ((OTP_Type*) OTP_BASE) 6051 #define OTP_DATA ((OTP_DATA_Type*) OTP_DATA_BASE) 6052 #define OTP_DATA_RAW ((OTP_DATA_RAW_Type*) OTP_DATA_RAW_BASE) 6053 #define TBMAN ((TBMAN_Type*) TBMAN_BASE) 6054 #define USB_DPRAM ((USB_DPRAM_Type*) USB_DPRAM_BASE) 6055 6056 /** @} */ /* End of group Device_Peripheral_declaration */ 6057 6058 6059 #ifdef __cplusplus 6060 } 6061 #endif 6062 6063 #endif /* RP2350_H */ 6064 6065 6066 /** @} */ /* End of group RP2350 */ 6067 6068 /** @} */ /* End of group Raspberry Pi */ 6069
