1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : PADS_BANK0 10 // Version : 1 11 // Bus type : apb 12 // ============================================================================= 13 #ifndef _HARDWARE_REGS_PADS_BANK0_H 14 #define _HARDWARE_REGS_PADS_BANK0_H 15 // ============================================================================= 16 // Register : PADS_BANK0_VOLTAGE_SELECT 17 // Description : Voltage select. Per bank control 18 // 0x0 -> Set voltage to 3.3V (DVDD >= 2V5) 19 // 0x1 -> Set voltage to 1.8V (DVDD <= 1V8) 20 #define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000) 21 #define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001) 22 #define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000) 23 #define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0) 24 #define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0) 25 #define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW" 26 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0) 27 #define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1) 28 // ============================================================================= 29 // Register : PADS_BANK0_GPIO0 30 #define PADS_BANK0_GPIO0_OFFSET _u(0x00000004) 31 #define PADS_BANK0_GPIO0_BITS _u(0x000001ff) 32 #define PADS_BANK0_GPIO0_RESET _u(0x00000116) 33 // ----------------------------------------------------------------------------- 34 // Field : PADS_BANK0_GPIO0_ISO 35 // Description : Pad isolation control. Remove this once the pad is configured 36 // by software. 37 #define PADS_BANK0_GPIO0_ISO_RESET _u(0x1) 38 #define PADS_BANK0_GPIO0_ISO_BITS _u(0x00000100) 39 #define PADS_BANK0_GPIO0_ISO_MSB _u(8) 40 #define PADS_BANK0_GPIO0_ISO_LSB _u(8) 41 #define PADS_BANK0_GPIO0_ISO_ACCESS "RW" 42 // ----------------------------------------------------------------------------- 43 // Field : PADS_BANK0_GPIO0_OD 44 // Description : Output disable. Has priority over output enable from 45 // peripherals 46 #define PADS_BANK0_GPIO0_OD_RESET _u(0x0) 47 #define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080) 48 #define PADS_BANK0_GPIO0_OD_MSB _u(7) 49 #define PADS_BANK0_GPIO0_OD_LSB _u(7) 50 #define PADS_BANK0_GPIO0_OD_ACCESS "RW" 51 // ----------------------------------------------------------------------------- 52 // Field : PADS_BANK0_GPIO0_IE 53 // Description : Input enable 54 #define PADS_BANK0_GPIO0_IE_RESET _u(0x0) 55 #define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040) 56 #define PADS_BANK0_GPIO0_IE_MSB _u(6) 57 #define PADS_BANK0_GPIO0_IE_LSB _u(6) 58 #define PADS_BANK0_GPIO0_IE_ACCESS "RW" 59 // ----------------------------------------------------------------------------- 60 // Field : PADS_BANK0_GPIO0_DRIVE 61 // Description : Drive strength. 62 // 0x0 -> 2mA 63 // 0x1 -> 4mA 64 // 0x2 -> 8mA 65 // 0x3 -> 12mA 66 #define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1) 67 #define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030) 68 #define PADS_BANK0_GPIO0_DRIVE_MSB _u(5) 69 #define PADS_BANK0_GPIO0_DRIVE_LSB _u(4) 70 #define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW" 71 #define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0) 72 #define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1) 73 #define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2) 74 #define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3) 75 // ----------------------------------------------------------------------------- 76 // Field : PADS_BANK0_GPIO0_PUE 77 // Description : Pull up enable 78 #define PADS_BANK0_GPIO0_PUE_RESET _u(0x0) 79 #define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008) 80 #define PADS_BANK0_GPIO0_PUE_MSB _u(3) 81 #define PADS_BANK0_GPIO0_PUE_LSB _u(3) 82 #define PADS_BANK0_GPIO0_PUE_ACCESS "RW" 83 // ----------------------------------------------------------------------------- 84 // Field : PADS_BANK0_GPIO0_PDE 85 // Description : Pull down enable 86 #define PADS_BANK0_GPIO0_PDE_RESET _u(0x1) 87 #define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004) 88 #define PADS_BANK0_GPIO0_PDE_MSB _u(2) 89 #define PADS_BANK0_GPIO0_PDE_LSB _u(2) 90 #define PADS_BANK0_GPIO0_PDE_ACCESS "RW" 91 // ----------------------------------------------------------------------------- 92 // Field : PADS_BANK0_GPIO0_SCHMITT 93 // Description : Enable schmitt trigger 94 #define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1) 95 #define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002) 96 #define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1) 97 #define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1) 98 #define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW" 99 // ----------------------------------------------------------------------------- 100 // Field : PADS_BANK0_GPIO0_SLEWFAST 101 // Description : Slew rate control. 1 = Fast, 0 = Slow 102 #define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0) 103 #define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001) 104 #define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0) 105 #define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0) 106 #define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW" 107 // ============================================================================= 108 // Register : PADS_BANK0_GPIO1 109 #define PADS_BANK0_GPIO1_OFFSET _u(0x00000008) 110 #define PADS_BANK0_GPIO1_BITS _u(0x000001ff) 111 #define PADS_BANK0_GPIO1_RESET _u(0x00000116) 112 // ----------------------------------------------------------------------------- 113 // Field : PADS_BANK0_GPIO1_ISO 114 // Description : Pad isolation control. Remove this once the pad is configured 115 // by software. 116 #define PADS_BANK0_GPIO1_ISO_RESET _u(0x1) 117 #define PADS_BANK0_GPIO1_ISO_BITS _u(0x00000100) 118 #define PADS_BANK0_GPIO1_ISO_MSB _u(8) 119 #define PADS_BANK0_GPIO1_ISO_LSB _u(8) 120 #define PADS_BANK0_GPIO1_ISO_ACCESS "RW" 121 // ----------------------------------------------------------------------------- 122 // Field : PADS_BANK0_GPIO1_OD 123 // Description : Output disable. Has priority over output enable from 124 // peripherals 125 #define PADS_BANK0_GPIO1_OD_RESET _u(0x0) 126 #define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080) 127 #define PADS_BANK0_GPIO1_OD_MSB _u(7) 128 #define PADS_BANK0_GPIO1_OD_LSB _u(7) 129 #define PADS_BANK0_GPIO1_OD_ACCESS "RW" 130 // ----------------------------------------------------------------------------- 131 // Field : PADS_BANK0_GPIO1_IE 132 // Description : Input enable 133 #define PADS_BANK0_GPIO1_IE_RESET _u(0x0) 134 #define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040) 135 #define PADS_BANK0_GPIO1_IE_MSB _u(6) 136 #define PADS_BANK0_GPIO1_IE_LSB _u(6) 137 #define PADS_BANK0_GPIO1_IE_ACCESS "RW" 138 // ----------------------------------------------------------------------------- 139 // Field : PADS_BANK0_GPIO1_DRIVE 140 // Description : Drive strength. 141 // 0x0 -> 2mA 142 // 0x1 -> 4mA 143 // 0x2 -> 8mA 144 // 0x3 -> 12mA 145 #define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1) 146 #define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030) 147 #define PADS_BANK0_GPIO1_DRIVE_MSB _u(5) 148 #define PADS_BANK0_GPIO1_DRIVE_LSB _u(4) 149 #define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW" 150 #define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0) 151 #define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1) 152 #define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2) 153 #define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3) 154 // ----------------------------------------------------------------------------- 155 // Field : PADS_BANK0_GPIO1_PUE 156 // Description : Pull up enable 157 #define PADS_BANK0_GPIO1_PUE_RESET _u(0x0) 158 #define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008) 159 #define PADS_BANK0_GPIO1_PUE_MSB _u(3) 160 #define PADS_BANK0_GPIO1_PUE_LSB _u(3) 161 #define PADS_BANK0_GPIO1_PUE_ACCESS "RW" 162 // ----------------------------------------------------------------------------- 163 // Field : PADS_BANK0_GPIO1_PDE 164 // Description : Pull down enable 165 #define PADS_BANK0_GPIO1_PDE_RESET _u(0x1) 166 #define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004) 167 #define PADS_BANK0_GPIO1_PDE_MSB _u(2) 168 #define PADS_BANK0_GPIO1_PDE_LSB _u(2) 169 #define PADS_BANK0_GPIO1_PDE_ACCESS "RW" 170 // ----------------------------------------------------------------------------- 171 // Field : PADS_BANK0_GPIO1_SCHMITT 172 // Description : Enable schmitt trigger 173 #define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1) 174 #define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002) 175 #define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1) 176 #define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1) 177 #define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW" 178 // ----------------------------------------------------------------------------- 179 // Field : PADS_BANK0_GPIO1_SLEWFAST 180 // Description : Slew rate control. 1 = Fast, 0 = Slow 181 #define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0) 182 #define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001) 183 #define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0) 184 #define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0) 185 #define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW" 186 // ============================================================================= 187 // Register : PADS_BANK0_GPIO2 188 #define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c) 189 #define PADS_BANK0_GPIO2_BITS _u(0x000001ff) 190 #define PADS_BANK0_GPIO2_RESET _u(0x00000116) 191 // ----------------------------------------------------------------------------- 192 // Field : PADS_BANK0_GPIO2_ISO 193 // Description : Pad isolation control. Remove this once the pad is configured 194 // by software. 195 #define PADS_BANK0_GPIO2_ISO_RESET _u(0x1) 196 #define PADS_BANK0_GPIO2_ISO_BITS _u(0x00000100) 197 #define PADS_BANK0_GPIO2_ISO_MSB _u(8) 198 #define PADS_BANK0_GPIO2_ISO_LSB _u(8) 199 #define PADS_BANK0_GPIO2_ISO_ACCESS "RW" 200 // ----------------------------------------------------------------------------- 201 // Field : PADS_BANK0_GPIO2_OD 202 // Description : Output disable. Has priority over output enable from 203 // peripherals 204 #define PADS_BANK0_GPIO2_OD_RESET _u(0x0) 205 #define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080) 206 #define PADS_BANK0_GPIO2_OD_MSB _u(7) 207 #define PADS_BANK0_GPIO2_OD_LSB _u(7) 208 #define PADS_BANK0_GPIO2_OD_ACCESS "RW" 209 // ----------------------------------------------------------------------------- 210 // Field : PADS_BANK0_GPIO2_IE 211 // Description : Input enable 212 #define PADS_BANK0_GPIO2_IE_RESET _u(0x0) 213 #define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040) 214 #define PADS_BANK0_GPIO2_IE_MSB _u(6) 215 #define PADS_BANK0_GPIO2_IE_LSB _u(6) 216 #define PADS_BANK0_GPIO2_IE_ACCESS "RW" 217 // ----------------------------------------------------------------------------- 218 // Field : PADS_BANK0_GPIO2_DRIVE 219 // Description : Drive strength. 220 // 0x0 -> 2mA 221 // 0x1 -> 4mA 222 // 0x2 -> 8mA 223 // 0x3 -> 12mA 224 #define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1) 225 #define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030) 226 #define PADS_BANK0_GPIO2_DRIVE_MSB _u(5) 227 #define PADS_BANK0_GPIO2_DRIVE_LSB _u(4) 228 #define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW" 229 #define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0) 230 #define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1) 231 #define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2) 232 #define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3) 233 // ----------------------------------------------------------------------------- 234 // Field : PADS_BANK0_GPIO2_PUE 235 // Description : Pull up enable 236 #define PADS_BANK0_GPIO2_PUE_RESET _u(0x0) 237 #define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008) 238 #define PADS_BANK0_GPIO2_PUE_MSB _u(3) 239 #define PADS_BANK0_GPIO2_PUE_LSB _u(3) 240 #define PADS_BANK0_GPIO2_PUE_ACCESS "RW" 241 // ----------------------------------------------------------------------------- 242 // Field : PADS_BANK0_GPIO2_PDE 243 // Description : Pull down enable 244 #define PADS_BANK0_GPIO2_PDE_RESET _u(0x1) 245 #define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004) 246 #define PADS_BANK0_GPIO2_PDE_MSB _u(2) 247 #define PADS_BANK0_GPIO2_PDE_LSB _u(2) 248 #define PADS_BANK0_GPIO2_PDE_ACCESS "RW" 249 // ----------------------------------------------------------------------------- 250 // Field : PADS_BANK0_GPIO2_SCHMITT 251 // Description : Enable schmitt trigger 252 #define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1) 253 #define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002) 254 #define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1) 255 #define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1) 256 #define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW" 257 // ----------------------------------------------------------------------------- 258 // Field : PADS_BANK0_GPIO2_SLEWFAST 259 // Description : Slew rate control. 1 = Fast, 0 = Slow 260 #define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0) 261 #define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001) 262 #define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0) 263 #define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0) 264 #define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW" 265 // ============================================================================= 266 // Register : PADS_BANK0_GPIO3 267 #define PADS_BANK0_GPIO3_OFFSET _u(0x00000010) 268 #define PADS_BANK0_GPIO3_BITS _u(0x000001ff) 269 #define PADS_BANK0_GPIO3_RESET _u(0x00000116) 270 // ----------------------------------------------------------------------------- 271 // Field : PADS_BANK0_GPIO3_ISO 272 // Description : Pad isolation control. Remove this once the pad is configured 273 // by software. 274 #define PADS_BANK0_GPIO3_ISO_RESET _u(0x1) 275 #define PADS_BANK0_GPIO3_ISO_BITS _u(0x00000100) 276 #define PADS_BANK0_GPIO3_ISO_MSB _u(8) 277 #define PADS_BANK0_GPIO3_ISO_LSB _u(8) 278 #define PADS_BANK0_GPIO3_ISO_ACCESS "RW" 279 // ----------------------------------------------------------------------------- 280 // Field : PADS_BANK0_GPIO3_OD 281 // Description : Output disable. Has priority over output enable from 282 // peripherals 283 #define PADS_BANK0_GPIO3_OD_RESET _u(0x0) 284 #define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080) 285 #define PADS_BANK0_GPIO3_OD_MSB _u(7) 286 #define PADS_BANK0_GPIO3_OD_LSB _u(7) 287 #define PADS_BANK0_GPIO3_OD_ACCESS "RW" 288 // ----------------------------------------------------------------------------- 289 // Field : PADS_BANK0_GPIO3_IE 290 // Description : Input enable 291 #define PADS_BANK0_GPIO3_IE_RESET _u(0x0) 292 #define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040) 293 #define PADS_BANK0_GPIO3_IE_MSB _u(6) 294 #define PADS_BANK0_GPIO3_IE_LSB _u(6) 295 #define PADS_BANK0_GPIO3_IE_ACCESS "RW" 296 // ----------------------------------------------------------------------------- 297 // Field : PADS_BANK0_GPIO3_DRIVE 298 // Description : Drive strength. 299 // 0x0 -> 2mA 300 // 0x1 -> 4mA 301 // 0x2 -> 8mA 302 // 0x3 -> 12mA 303 #define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1) 304 #define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030) 305 #define PADS_BANK0_GPIO3_DRIVE_MSB _u(5) 306 #define PADS_BANK0_GPIO3_DRIVE_LSB _u(4) 307 #define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW" 308 #define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0) 309 #define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1) 310 #define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2) 311 #define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3) 312 // ----------------------------------------------------------------------------- 313 // Field : PADS_BANK0_GPIO3_PUE 314 // Description : Pull up enable 315 #define PADS_BANK0_GPIO3_PUE_RESET _u(0x0) 316 #define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008) 317 #define PADS_BANK0_GPIO3_PUE_MSB _u(3) 318 #define PADS_BANK0_GPIO3_PUE_LSB _u(3) 319 #define PADS_BANK0_GPIO3_PUE_ACCESS "RW" 320 // ----------------------------------------------------------------------------- 321 // Field : PADS_BANK0_GPIO3_PDE 322 // Description : Pull down enable 323 #define PADS_BANK0_GPIO3_PDE_RESET _u(0x1) 324 #define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004) 325 #define PADS_BANK0_GPIO3_PDE_MSB _u(2) 326 #define PADS_BANK0_GPIO3_PDE_LSB _u(2) 327 #define PADS_BANK0_GPIO3_PDE_ACCESS "RW" 328 // ----------------------------------------------------------------------------- 329 // Field : PADS_BANK0_GPIO3_SCHMITT 330 // Description : Enable schmitt trigger 331 #define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1) 332 #define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002) 333 #define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1) 334 #define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1) 335 #define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW" 336 // ----------------------------------------------------------------------------- 337 // Field : PADS_BANK0_GPIO3_SLEWFAST 338 // Description : Slew rate control. 1 = Fast, 0 = Slow 339 #define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0) 340 #define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001) 341 #define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0) 342 #define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0) 343 #define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW" 344 // ============================================================================= 345 // Register : PADS_BANK0_GPIO4 346 #define PADS_BANK0_GPIO4_OFFSET _u(0x00000014) 347 #define PADS_BANK0_GPIO4_BITS _u(0x000001ff) 348 #define PADS_BANK0_GPIO4_RESET _u(0x00000116) 349 // ----------------------------------------------------------------------------- 350 // Field : PADS_BANK0_GPIO4_ISO 351 // Description : Pad isolation control. Remove this once the pad is configured 352 // by software. 353 #define PADS_BANK0_GPIO4_ISO_RESET _u(0x1) 354 #define PADS_BANK0_GPIO4_ISO_BITS _u(0x00000100) 355 #define PADS_BANK0_GPIO4_ISO_MSB _u(8) 356 #define PADS_BANK0_GPIO4_ISO_LSB _u(8) 357 #define PADS_BANK0_GPIO4_ISO_ACCESS "RW" 358 // ----------------------------------------------------------------------------- 359 // Field : PADS_BANK0_GPIO4_OD 360 // Description : Output disable. Has priority over output enable from 361 // peripherals 362 #define PADS_BANK0_GPIO4_OD_RESET _u(0x0) 363 #define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080) 364 #define PADS_BANK0_GPIO4_OD_MSB _u(7) 365 #define PADS_BANK0_GPIO4_OD_LSB _u(7) 366 #define PADS_BANK0_GPIO4_OD_ACCESS "RW" 367 // ----------------------------------------------------------------------------- 368 // Field : PADS_BANK0_GPIO4_IE 369 // Description : Input enable 370 #define PADS_BANK0_GPIO4_IE_RESET _u(0x0) 371 #define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040) 372 #define PADS_BANK0_GPIO4_IE_MSB _u(6) 373 #define PADS_BANK0_GPIO4_IE_LSB _u(6) 374 #define PADS_BANK0_GPIO4_IE_ACCESS "RW" 375 // ----------------------------------------------------------------------------- 376 // Field : PADS_BANK0_GPIO4_DRIVE 377 // Description : Drive strength. 378 // 0x0 -> 2mA 379 // 0x1 -> 4mA 380 // 0x2 -> 8mA 381 // 0x3 -> 12mA 382 #define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1) 383 #define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030) 384 #define PADS_BANK0_GPIO4_DRIVE_MSB _u(5) 385 #define PADS_BANK0_GPIO4_DRIVE_LSB _u(4) 386 #define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW" 387 #define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0) 388 #define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1) 389 #define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2) 390 #define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3) 391 // ----------------------------------------------------------------------------- 392 // Field : PADS_BANK0_GPIO4_PUE 393 // Description : Pull up enable 394 #define PADS_BANK0_GPIO4_PUE_RESET _u(0x0) 395 #define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008) 396 #define PADS_BANK0_GPIO4_PUE_MSB _u(3) 397 #define PADS_BANK0_GPIO4_PUE_LSB _u(3) 398 #define PADS_BANK0_GPIO4_PUE_ACCESS "RW" 399 // ----------------------------------------------------------------------------- 400 // Field : PADS_BANK0_GPIO4_PDE 401 // Description : Pull down enable 402 #define PADS_BANK0_GPIO4_PDE_RESET _u(0x1) 403 #define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004) 404 #define PADS_BANK0_GPIO4_PDE_MSB _u(2) 405 #define PADS_BANK0_GPIO4_PDE_LSB _u(2) 406 #define PADS_BANK0_GPIO4_PDE_ACCESS "RW" 407 // ----------------------------------------------------------------------------- 408 // Field : PADS_BANK0_GPIO4_SCHMITT 409 // Description : Enable schmitt trigger 410 #define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1) 411 #define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002) 412 #define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1) 413 #define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1) 414 #define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW" 415 // ----------------------------------------------------------------------------- 416 // Field : PADS_BANK0_GPIO4_SLEWFAST 417 // Description : Slew rate control. 1 = Fast, 0 = Slow 418 #define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0) 419 #define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001) 420 #define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0) 421 #define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0) 422 #define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW" 423 // ============================================================================= 424 // Register : PADS_BANK0_GPIO5 425 #define PADS_BANK0_GPIO5_OFFSET _u(0x00000018) 426 #define PADS_BANK0_GPIO5_BITS _u(0x000001ff) 427 #define PADS_BANK0_GPIO5_RESET _u(0x00000116) 428 // ----------------------------------------------------------------------------- 429 // Field : PADS_BANK0_GPIO5_ISO 430 // Description : Pad isolation control. Remove this once the pad is configured 431 // by software. 432 #define PADS_BANK0_GPIO5_ISO_RESET _u(0x1) 433 #define PADS_BANK0_GPIO5_ISO_BITS _u(0x00000100) 434 #define PADS_BANK0_GPIO5_ISO_MSB _u(8) 435 #define PADS_BANK0_GPIO5_ISO_LSB _u(8) 436 #define PADS_BANK0_GPIO5_ISO_ACCESS "RW" 437 // ----------------------------------------------------------------------------- 438 // Field : PADS_BANK0_GPIO5_OD 439 // Description : Output disable. Has priority over output enable from 440 // peripherals 441 #define PADS_BANK0_GPIO5_OD_RESET _u(0x0) 442 #define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080) 443 #define PADS_BANK0_GPIO5_OD_MSB _u(7) 444 #define PADS_BANK0_GPIO5_OD_LSB _u(7) 445 #define PADS_BANK0_GPIO5_OD_ACCESS "RW" 446 // ----------------------------------------------------------------------------- 447 // Field : PADS_BANK0_GPIO5_IE 448 // Description : Input enable 449 #define PADS_BANK0_GPIO5_IE_RESET _u(0x0) 450 #define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040) 451 #define PADS_BANK0_GPIO5_IE_MSB _u(6) 452 #define PADS_BANK0_GPIO5_IE_LSB _u(6) 453 #define PADS_BANK0_GPIO5_IE_ACCESS "RW" 454 // ----------------------------------------------------------------------------- 455 // Field : PADS_BANK0_GPIO5_DRIVE 456 // Description : Drive strength. 457 // 0x0 -> 2mA 458 // 0x1 -> 4mA 459 // 0x2 -> 8mA 460 // 0x3 -> 12mA 461 #define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1) 462 #define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030) 463 #define PADS_BANK0_GPIO5_DRIVE_MSB _u(5) 464 #define PADS_BANK0_GPIO5_DRIVE_LSB _u(4) 465 #define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW" 466 #define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0) 467 #define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1) 468 #define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2) 469 #define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3) 470 // ----------------------------------------------------------------------------- 471 // Field : PADS_BANK0_GPIO5_PUE 472 // Description : Pull up enable 473 #define PADS_BANK0_GPIO5_PUE_RESET _u(0x0) 474 #define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008) 475 #define PADS_BANK0_GPIO5_PUE_MSB _u(3) 476 #define PADS_BANK0_GPIO5_PUE_LSB _u(3) 477 #define PADS_BANK0_GPIO5_PUE_ACCESS "RW" 478 // ----------------------------------------------------------------------------- 479 // Field : PADS_BANK0_GPIO5_PDE 480 // Description : Pull down enable 481 #define PADS_BANK0_GPIO5_PDE_RESET _u(0x1) 482 #define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004) 483 #define PADS_BANK0_GPIO5_PDE_MSB _u(2) 484 #define PADS_BANK0_GPIO5_PDE_LSB _u(2) 485 #define PADS_BANK0_GPIO5_PDE_ACCESS "RW" 486 // ----------------------------------------------------------------------------- 487 // Field : PADS_BANK0_GPIO5_SCHMITT 488 // Description : Enable schmitt trigger 489 #define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1) 490 #define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002) 491 #define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1) 492 #define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1) 493 #define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW" 494 // ----------------------------------------------------------------------------- 495 // Field : PADS_BANK0_GPIO5_SLEWFAST 496 // Description : Slew rate control. 1 = Fast, 0 = Slow 497 #define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0) 498 #define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001) 499 #define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0) 500 #define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0) 501 #define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW" 502 // ============================================================================= 503 // Register : PADS_BANK0_GPIO6 504 #define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c) 505 #define PADS_BANK0_GPIO6_BITS _u(0x000001ff) 506 #define PADS_BANK0_GPIO6_RESET _u(0x00000116) 507 // ----------------------------------------------------------------------------- 508 // Field : PADS_BANK0_GPIO6_ISO 509 // Description : Pad isolation control. Remove this once the pad is configured 510 // by software. 511 #define PADS_BANK0_GPIO6_ISO_RESET _u(0x1) 512 #define PADS_BANK0_GPIO6_ISO_BITS _u(0x00000100) 513 #define PADS_BANK0_GPIO6_ISO_MSB _u(8) 514 #define PADS_BANK0_GPIO6_ISO_LSB _u(8) 515 #define PADS_BANK0_GPIO6_ISO_ACCESS "RW" 516 // ----------------------------------------------------------------------------- 517 // Field : PADS_BANK0_GPIO6_OD 518 // Description : Output disable. Has priority over output enable from 519 // peripherals 520 #define PADS_BANK0_GPIO6_OD_RESET _u(0x0) 521 #define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080) 522 #define PADS_BANK0_GPIO6_OD_MSB _u(7) 523 #define PADS_BANK0_GPIO6_OD_LSB _u(7) 524 #define PADS_BANK0_GPIO6_OD_ACCESS "RW" 525 // ----------------------------------------------------------------------------- 526 // Field : PADS_BANK0_GPIO6_IE 527 // Description : Input enable 528 #define PADS_BANK0_GPIO6_IE_RESET _u(0x0) 529 #define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040) 530 #define PADS_BANK0_GPIO6_IE_MSB _u(6) 531 #define PADS_BANK0_GPIO6_IE_LSB _u(6) 532 #define PADS_BANK0_GPIO6_IE_ACCESS "RW" 533 // ----------------------------------------------------------------------------- 534 // Field : PADS_BANK0_GPIO6_DRIVE 535 // Description : Drive strength. 536 // 0x0 -> 2mA 537 // 0x1 -> 4mA 538 // 0x2 -> 8mA 539 // 0x3 -> 12mA 540 #define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1) 541 #define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030) 542 #define PADS_BANK0_GPIO6_DRIVE_MSB _u(5) 543 #define PADS_BANK0_GPIO6_DRIVE_LSB _u(4) 544 #define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW" 545 #define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0) 546 #define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1) 547 #define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2) 548 #define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3) 549 // ----------------------------------------------------------------------------- 550 // Field : PADS_BANK0_GPIO6_PUE 551 // Description : Pull up enable 552 #define PADS_BANK0_GPIO6_PUE_RESET _u(0x0) 553 #define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008) 554 #define PADS_BANK0_GPIO6_PUE_MSB _u(3) 555 #define PADS_BANK0_GPIO6_PUE_LSB _u(3) 556 #define PADS_BANK0_GPIO6_PUE_ACCESS "RW" 557 // ----------------------------------------------------------------------------- 558 // Field : PADS_BANK0_GPIO6_PDE 559 // Description : Pull down enable 560 #define PADS_BANK0_GPIO6_PDE_RESET _u(0x1) 561 #define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004) 562 #define PADS_BANK0_GPIO6_PDE_MSB _u(2) 563 #define PADS_BANK0_GPIO6_PDE_LSB _u(2) 564 #define PADS_BANK0_GPIO6_PDE_ACCESS "RW" 565 // ----------------------------------------------------------------------------- 566 // Field : PADS_BANK0_GPIO6_SCHMITT 567 // Description : Enable schmitt trigger 568 #define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1) 569 #define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002) 570 #define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1) 571 #define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1) 572 #define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW" 573 // ----------------------------------------------------------------------------- 574 // Field : PADS_BANK0_GPIO6_SLEWFAST 575 // Description : Slew rate control. 1 = Fast, 0 = Slow 576 #define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0) 577 #define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001) 578 #define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0) 579 #define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0) 580 #define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW" 581 // ============================================================================= 582 // Register : PADS_BANK0_GPIO7 583 #define PADS_BANK0_GPIO7_OFFSET _u(0x00000020) 584 #define PADS_BANK0_GPIO7_BITS _u(0x000001ff) 585 #define PADS_BANK0_GPIO7_RESET _u(0x00000116) 586 // ----------------------------------------------------------------------------- 587 // Field : PADS_BANK0_GPIO7_ISO 588 // Description : Pad isolation control. Remove this once the pad is configured 589 // by software. 590 #define PADS_BANK0_GPIO7_ISO_RESET _u(0x1) 591 #define PADS_BANK0_GPIO7_ISO_BITS _u(0x00000100) 592 #define PADS_BANK0_GPIO7_ISO_MSB _u(8) 593 #define PADS_BANK0_GPIO7_ISO_LSB _u(8) 594 #define PADS_BANK0_GPIO7_ISO_ACCESS "RW" 595 // ----------------------------------------------------------------------------- 596 // Field : PADS_BANK0_GPIO7_OD 597 // Description : Output disable. Has priority over output enable from 598 // peripherals 599 #define PADS_BANK0_GPIO7_OD_RESET _u(0x0) 600 #define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080) 601 #define PADS_BANK0_GPIO7_OD_MSB _u(7) 602 #define PADS_BANK0_GPIO7_OD_LSB _u(7) 603 #define PADS_BANK0_GPIO7_OD_ACCESS "RW" 604 // ----------------------------------------------------------------------------- 605 // Field : PADS_BANK0_GPIO7_IE 606 // Description : Input enable 607 #define PADS_BANK0_GPIO7_IE_RESET _u(0x0) 608 #define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040) 609 #define PADS_BANK0_GPIO7_IE_MSB _u(6) 610 #define PADS_BANK0_GPIO7_IE_LSB _u(6) 611 #define PADS_BANK0_GPIO7_IE_ACCESS "RW" 612 // ----------------------------------------------------------------------------- 613 // Field : PADS_BANK0_GPIO7_DRIVE 614 // Description : Drive strength. 615 // 0x0 -> 2mA 616 // 0x1 -> 4mA 617 // 0x2 -> 8mA 618 // 0x3 -> 12mA 619 #define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1) 620 #define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030) 621 #define PADS_BANK0_GPIO7_DRIVE_MSB _u(5) 622 #define PADS_BANK0_GPIO7_DRIVE_LSB _u(4) 623 #define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW" 624 #define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0) 625 #define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1) 626 #define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2) 627 #define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3) 628 // ----------------------------------------------------------------------------- 629 // Field : PADS_BANK0_GPIO7_PUE 630 // Description : Pull up enable 631 #define PADS_BANK0_GPIO7_PUE_RESET _u(0x0) 632 #define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008) 633 #define PADS_BANK0_GPIO7_PUE_MSB _u(3) 634 #define PADS_BANK0_GPIO7_PUE_LSB _u(3) 635 #define PADS_BANK0_GPIO7_PUE_ACCESS "RW" 636 // ----------------------------------------------------------------------------- 637 // Field : PADS_BANK0_GPIO7_PDE 638 // Description : Pull down enable 639 #define PADS_BANK0_GPIO7_PDE_RESET _u(0x1) 640 #define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004) 641 #define PADS_BANK0_GPIO7_PDE_MSB _u(2) 642 #define PADS_BANK0_GPIO7_PDE_LSB _u(2) 643 #define PADS_BANK0_GPIO7_PDE_ACCESS "RW" 644 // ----------------------------------------------------------------------------- 645 // Field : PADS_BANK0_GPIO7_SCHMITT 646 // Description : Enable schmitt trigger 647 #define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1) 648 #define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002) 649 #define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1) 650 #define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1) 651 #define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW" 652 // ----------------------------------------------------------------------------- 653 // Field : PADS_BANK0_GPIO7_SLEWFAST 654 // Description : Slew rate control. 1 = Fast, 0 = Slow 655 #define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0) 656 #define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001) 657 #define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0) 658 #define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0) 659 #define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW" 660 // ============================================================================= 661 // Register : PADS_BANK0_GPIO8 662 #define PADS_BANK0_GPIO8_OFFSET _u(0x00000024) 663 #define PADS_BANK0_GPIO8_BITS _u(0x000001ff) 664 #define PADS_BANK0_GPIO8_RESET _u(0x00000116) 665 // ----------------------------------------------------------------------------- 666 // Field : PADS_BANK0_GPIO8_ISO 667 // Description : Pad isolation control. Remove this once the pad is configured 668 // by software. 669 #define PADS_BANK0_GPIO8_ISO_RESET _u(0x1) 670 #define PADS_BANK0_GPIO8_ISO_BITS _u(0x00000100) 671 #define PADS_BANK0_GPIO8_ISO_MSB _u(8) 672 #define PADS_BANK0_GPIO8_ISO_LSB _u(8) 673 #define PADS_BANK0_GPIO8_ISO_ACCESS "RW" 674 // ----------------------------------------------------------------------------- 675 // Field : PADS_BANK0_GPIO8_OD 676 // Description : Output disable. Has priority over output enable from 677 // peripherals 678 #define PADS_BANK0_GPIO8_OD_RESET _u(0x0) 679 #define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080) 680 #define PADS_BANK0_GPIO8_OD_MSB _u(7) 681 #define PADS_BANK0_GPIO8_OD_LSB _u(7) 682 #define PADS_BANK0_GPIO8_OD_ACCESS "RW" 683 // ----------------------------------------------------------------------------- 684 // Field : PADS_BANK0_GPIO8_IE 685 // Description : Input enable 686 #define PADS_BANK0_GPIO8_IE_RESET _u(0x0) 687 #define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040) 688 #define PADS_BANK0_GPIO8_IE_MSB _u(6) 689 #define PADS_BANK0_GPIO8_IE_LSB _u(6) 690 #define PADS_BANK0_GPIO8_IE_ACCESS "RW" 691 // ----------------------------------------------------------------------------- 692 // Field : PADS_BANK0_GPIO8_DRIVE 693 // Description : Drive strength. 694 // 0x0 -> 2mA 695 // 0x1 -> 4mA 696 // 0x2 -> 8mA 697 // 0x3 -> 12mA 698 #define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1) 699 #define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030) 700 #define PADS_BANK0_GPIO8_DRIVE_MSB _u(5) 701 #define PADS_BANK0_GPIO8_DRIVE_LSB _u(4) 702 #define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW" 703 #define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0) 704 #define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1) 705 #define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2) 706 #define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3) 707 // ----------------------------------------------------------------------------- 708 // Field : PADS_BANK0_GPIO8_PUE 709 // Description : Pull up enable 710 #define PADS_BANK0_GPIO8_PUE_RESET _u(0x0) 711 #define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008) 712 #define PADS_BANK0_GPIO8_PUE_MSB _u(3) 713 #define PADS_BANK0_GPIO8_PUE_LSB _u(3) 714 #define PADS_BANK0_GPIO8_PUE_ACCESS "RW" 715 // ----------------------------------------------------------------------------- 716 // Field : PADS_BANK0_GPIO8_PDE 717 // Description : Pull down enable 718 #define PADS_BANK0_GPIO8_PDE_RESET _u(0x1) 719 #define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004) 720 #define PADS_BANK0_GPIO8_PDE_MSB _u(2) 721 #define PADS_BANK0_GPIO8_PDE_LSB _u(2) 722 #define PADS_BANK0_GPIO8_PDE_ACCESS "RW" 723 // ----------------------------------------------------------------------------- 724 // Field : PADS_BANK0_GPIO8_SCHMITT 725 // Description : Enable schmitt trigger 726 #define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1) 727 #define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002) 728 #define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1) 729 #define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1) 730 #define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW" 731 // ----------------------------------------------------------------------------- 732 // Field : PADS_BANK0_GPIO8_SLEWFAST 733 // Description : Slew rate control. 1 = Fast, 0 = Slow 734 #define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0) 735 #define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001) 736 #define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0) 737 #define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0) 738 #define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW" 739 // ============================================================================= 740 // Register : PADS_BANK0_GPIO9 741 #define PADS_BANK0_GPIO9_OFFSET _u(0x00000028) 742 #define PADS_BANK0_GPIO9_BITS _u(0x000001ff) 743 #define PADS_BANK0_GPIO9_RESET _u(0x00000116) 744 // ----------------------------------------------------------------------------- 745 // Field : PADS_BANK0_GPIO9_ISO 746 // Description : Pad isolation control. Remove this once the pad is configured 747 // by software. 748 #define PADS_BANK0_GPIO9_ISO_RESET _u(0x1) 749 #define PADS_BANK0_GPIO9_ISO_BITS _u(0x00000100) 750 #define PADS_BANK0_GPIO9_ISO_MSB _u(8) 751 #define PADS_BANK0_GPIO9_ISO_LSB _u(8) 752 #define PADS_BANK0_GPIO9_ISO_ACCESS "RW" 753 // ----------------------------------------------------------------------------- 754 // Field : PADS_BANK0_GPIO9_OD 755 // Description : Output disable. Has priority over output enable from 756 // peripherals 757 #define PADS_BANK0_GPIO9_OD_RESET _u(0x0) 758 #define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080) 759 #define PADS_BANK0_GPIO9_OD_MSB _u(7) 760 #define PADS_BANK0_GPIO9_OD_LSB _u(7) 761 #define PADS_BANK0_GPIO9_OD_ACCESS "RW" 762 // ----------------------------------------------------------------------------- 763 // Field : PADS_BANK0_GPIO9_IE 764 // Description : Input enable 765 #define PADS_BANK0_GPIO9_IE_RESET _u(0x0) 766 #define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040) 767 #define PADS_BANK0_GPIO9_IE_MSB _u(6) 768 #define PADS_BANK0_GPIO9_IE_LSB _u(6) 769 #define PADS_BANK0_GPIO9_IE_ACCESS "RW" 770 // ----------------------------------------------------------------------------- 771 // Field : PADS_BANK0_GPIO9_DRIVE 772 // Description : Drive strength. 773 // 0x0 -> 2mA 774 // 0x1 -> 4mA 775 // 0x2 -> 8mA 776 // 0x3 -> 12mA 777 #define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1) 778 #define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030) 779 #define PADS_BANK0_GPIO9_DRIVE_MSB _u(5) 780 #define PADS_BANK0_GPIO9_DRIVE_LSB _u(4) 781 #define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW" 782 #define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0) 783 #define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1) 784 #define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2) 785 #define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3) 786 // ----------------------------------------------------------------------------- 787 // Field : PADS_BANK0_GPIO9_PUE 788 // Description : Pull up enable 789 #define PADS_BANK0_GPIO9_PUE_RESET _u(0x0) 790 #define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008) 791 #define PADS_BANK0_GPIO9_PUE_MSB _u(3) 792 #define PADS_BANK0_GPIO9_PUE_LSB _u(3) 793 #define PADS_BANK0_GPIO9_PUE_ACCESS "RW" 794 // ----------------------------------------------------------------------------- 795 // Field : PADS_BANK0_GPIO9_PDE 796 // Description : Pull down enable 797 #define PADS_BANK0_GPIO9_PDE_RESET _u(0x1) 798 #define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004) 799 #define PADS_BANK0_GPIO9_PDE_MSB _u(2) 800 #define PADS_BANK0_GPIO9_PDE_LSB _u(2) 801 #define PADS_BANK0_GPIO9_PDE_ACCESS "RW" 802 // ----------------------------------------------------------------------------- 803 // Field : PADS_BANK0_GPIO9_SCHMITT 804 // Description : Enable schmitt trigger 805 #define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1) 806 #define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002) 807 #define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1) 808 #define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1) 809 #define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW" 810 // ----------------------------------------------------------------------------- 811 // Field : PADS_BANK0_GPIO9_SLEWFAST 812 // Description : Slew rate control. 1 = Fast, 0 = Slow 813 #define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0) 814 #define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001) 815 #define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0) 816 #define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0) 817 #define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW" 818 // ============================================================================= 819 // Register : PADS_BANK0_GPIO10 820 #define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c) 821 #define PADS_BANK0_GPIO10_BITS _u(0x000001ff) 822 #define PADS_BANK0_GPIO10_RESET _u(0x00000116) 823 // ----------------------------------------------------------------------------- 824 // Field : PADS_BANK0_GPIO10_ISO 825 // Description : Pad isolation control. Remove this once the pad is configured 826 // by software. 827 #define PADS_BANK0_GPIO10_ISO_RESET _u(0x1) 828 #define PADS_BANK0_GPIO10_ISO_BITS _u(0x00000100) 829 #define PADS_BANK0_GPIO10_ISO_MSB _u(8) 830 #define PADS_BANK0_GPIO10_ISO_LSB _u(8) 831 #define PADS_BANK0_GPIO10_ISO_ACCESS "RW" 832 // ----------------------------------------------------------------------------- 833 // Field : PADS_BANK0_GPIO10_OD 834 // Description : Output disable. Has priority over output enable from 835 // peripherals 836 #define PADS_BANK0_GPIO10_OD_RESET _u(0x0) 837 #define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080) 838 #define PADS_BANK0_GPIO10_OD_MSB _u(7) 839 #define PADS_BANK0_GPIO10_OD_LSB _u(7) 840 #define PADS_BANK0_GPIO10_OD_ACCESS "RW" 841 // ----------------------------------------------------------------------------- 842 // Field : PADS_BANK0_GPIO10_IE 843 // Description : Input enable 844 #define PADS_BANK0_GPIO10_IE_RESET _u(0x0) 845 #define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040) 846 #define PADS_BANK0_GPIO10_IE_MSB _u(6) 847 #define PADS_BANK0_GPIO10_IE_LSB _u(6) 848 #define PADS_BANK0_GPIO10_IE_ACCESS "RW" 849 // ----------------------------------------------------------------------------- 850 // Field : PADS_BANK0_GPIO10_DRIVE 851 // Description : Drive strength. 852 // 0x0 -> 2mA 853 // 0x1 -> 4mA 854 // 0x2 -> 8mA 855 // 0x3 -> 12mA 856 #define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1) 857 #define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030) 858 #define PADS_BANK0_GPIO10_DRIVE_MSB _u(5) 859 #define PADS_BANK0_GPIO10_DRIVE_LSB _u(4) 860 #define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW" 861 #define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0) 862 #define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1) 863 #define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2) 864 #define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3) 865 // ----------------------------------------------------------------------------- 866 // Field : PADS_BANK0_GPIO10_PUE 867 // Description : Pull up enable 868 #define PADS_BANK0_GPIO10_PUE_RESET _u(0x0) 869 #define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008) 870 #define PADS_BANK0_GPIO10_PUE_MSB _u(3) 871 #define PADS_BANK0_GPIO10_PUE_LSB _u(3) 872 #define PADS_BANK0_GPIO10_PUE_ACCESS "RW" 873 // ----------------------------------------------------------------------------- 874 // Field : PADS_BANK0_GPIO10_PDE 875 // Description : Pull down enable 876 #define PADS_BANK0_GPIO10_PDE_RESET _u(0x1) 877 #define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004) 878 #define PADS_BANK0_GPIO10_PDE_MSB _u(2) 879 #define PADS_BANK0_GPIO10_PDE_LSB _u(2) 880 #define PADS_BANK0_GPIO10_PDE_ACCESS "RW" 881 // ----------------------------------------------------------------------------- 882 // Field : PADS_BANK0_GPIO10_SCHMITT 883 // Description : Enable schmitt trigger 884 #define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1) 885 #define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002) 886 #define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1) 887 #define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1) 888 #define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW" 889 // ----------------------------------------------------------------------------- 890 // Field : PADS_BANK0_GPIO10_SLEWFAST 891 // Description : Slew rate control. 1 = Fast, 0 = Slow 892 #define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0) 893 #define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001) 894 #define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0) 895 #define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0) 896 #define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW" 897 // ============================================================================= 898 // Register : PADS_BANK0_GPIO11 899 #define PADS_BANK0_GPIO11_OFFSET _u(0x00000030) 900 #define PADS_BANK0_GPIO11_BITS _u(0x000001ff) 901 #define PADS_BANK0_GPIO11_RESET _u(0x00000116) 902 // ----------------------------------------------------------------------------- 903 // Field : PADS_BANK0_GPIO11_ISO 904 // Description : Pad isolation control. Remove this once the pad is configured 905 // by software. 906 #define PADS_BANK0_GPIO11_ISO_RESET _u(0x1) 907 #define PADS_BANK0_GPIO11_ISO_BITS _u(0x00000100) 908 #define PADS_BANK0_GPIO11_ISO_MSB _u(8) 909 #define PADS_BANK0_GPIO11_ISO_LSB _u(8) 910 #define PADS_BANK0_GPIO11_ISO_ACCESS "RW" 911 // ----------------------------------------------------------------------------- 912 // Field : PADS_BANK0_GPIO11_OD 913 // Description : Output disable. Has priority over output enable from 914 // peripherals 915 #define PADS_BANK0_GPIO11_OD_RESET _u(0x0) 916 #define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080) 917 #define PADS_BANK0_GPIO11_OD_MSB _u(7) 918 #define PADS_BANK0_GPIO11_OD_LSB _u(7) 919 #define PADS_BANK0_GPIO11_OD_ACCESS "RW" 920 // ----------------------------------------------------------------------------- 921 // Field : PADS_BANK0_GPIO11_IE 922 // Description : Input enable 923 #define PADS_BANK0_GPIO11_IE_RESET _u(0x0) 924 #define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040) 925 #define PADS_BANK0_GPIO11_IE_MSB _u(6) 926 #define PADS_BANK0_GPIO11_IE_LSB _u(6) 927 #define PADS_BANK0_GPIO11_IE_ACCESS "RW" 928 // ----------------------------------------------------------------------------- 929 // Field : PADS_BANK0_GPIO11_DRIVE 930 // Description : Drive strength. 931 // 0x0 -> 2mA 932 // 0x1 -> 4mA 933 // 0x2 -> 8mA 934 // 0x3 -> 12mA 935 #define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1) 936 #define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030) 937 #define PADS_BANK0_GPIO11_DRIVE_MSB _u(5) 938 #define PADS_BANK0_GPIO11_DRIVE_LSB _u(4) 939 #define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW" 940 #define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0) 941 #define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1) 942 #define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2) 943 #define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3) 944 // ----------------------------------------------------------------------------- 945 // Field : PADS_BANK0_GPIO11_PUE 946 // Description : Pull up enable 947 #define PADS_BANK0_GPIO11_PUE_RESET _u(0x0) 948 #define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008) 949 #define PADS_BANK0_GPIO11_PUE_MSB _u(3) 950 #define PADS_BANK0_GPIO11_PUE_LSB _u(3) 951 #define PADS_BANK0_GPIO11_PUE_ACCESS "RW" 952 // ----------------------------------------------------------------------------- 953 // Field : PADS_BANK0_GPIO11_PDE 954 // Description : Pull down enable 955 #define PADS_BANK0_GPIO11_PDE_RESET _u(0x1) 956 #define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004) 957 #define PADS_BANK0_GPIO11_PDE_MSB _u(2) 958 #define PADS_BANK0_GPIO11_PDE_LSB _u(2) 959 #define PADS_BANK0_GPIO11_PDE_ACCESS "RW" 960 // ----------------------------------------------------------------------------- 961 // Field : PADS_BANK0_GPIO11_SCHMITT 962 // Description : Enable schmitt trigger 963 #define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1) 964 #define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002) 965 #define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1) 966 #define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1) 967 #define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW" 968 // ----------------------------------------------------------------------------- 969 // Field : PADS_BANK0_GPIO11_SLEWFAST 970 // Description : Slew rate control. 1 = Fast, 0 = Slow 971 #define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0) 972 #define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001) 973 #define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0) 974 #define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0) 975 #define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW" 976 // ============================================================================= 977 // Register : PADS_BANK0_GPIO12 978 #define PADS_BANK0_GPIO12_OFFSET _u(0x00000034) 979 #define PADS_BANK0_GPIO12_BITS _u(0x000001ff) 980 #define PADS_BANK0_GPIO12_RESET _u(0x00000116) 981 // ----------------------------------------------------------------------------- 982 // Field : PADS_BANK0_GPIO12_ISO 983 // Description : Pad isolation control. Remove this once the pad is configured 984 // by software. 985 #define PADS_BANK0_GPIO12_ISO_RESET _u(0x1) 986 #define PADS_BANK0_GPIO12_ISO_BITS _u(0x00000100) 987 #define PADS_BANK0_GPIO12_ISO_MSB _u(8) 988 #define PADS_BANK0_GPIO12_ISO_LSB _u(8) 989 #define PADS_BANK0_GPIO12_ISO_ACCESS "RW" 990 // ----------------------------------------------------------------------------- 991 // Field : PADS_BANK0_GPIO12_OD 992 // Description : Output disable. Has priority over output enable from 993 // peripherals 994 #define PADS_BANK0_GPIO12_OD_RESET _u(0x0) 995 #define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080) 996 #define PADS_BANK0_GPIO12_OD_MSB _u(7) 997 #define PADS_BANK0_GPIO12_OD_LSB _u(7) 998 #define PADS_BANK0_GPIO12_OD_ACCESS "RW" 999 // ----------------------------------------------------------------------------- 1000 // Field : PADS_BANK0_GPIO12_IE 1001 // Description : Input enable 1002 #define PADS_BANK0_GPIO12_IE_RESET _u(0x0) 1003 #define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040) 1004 #define PADS_BANK0_GPIO12_IE_MSB _u(6) 1005 #define PADS_BANK0_GPIO12_IE_LSB _u(6) 1006 #define PADS_BANK0_GPIO12_IE_ACCESS "RW" 1007 // ----------------------------------------------------------------------------- 1008 // Field : PADS_BANK0_GPIO12_DRIVE 1009 // Description : Drive strength. 1010 // 0x0 -> 2mA 1011 // 0x1 -> 4mA 1012 // 0x2 -> 8mA 1013 // 0x3 -> 12mA 1014 #define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1) 1015 #define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030) 1016 #define PADS_BANK0_GPIO12_DRIVE_MSB _u(5) 1017 #define PADS_BANK0_GPIO12_DRIVE_LSB _u(4) 1018 #define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW" 1019 #define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0) 1020 #define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1) 1021 #define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2) 1022 #define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3) 1023 // ----------------------------------------------------------------------------- 1024 // Field : PADS_BANK0_GPIO12_PUE 1025 // Description : Pull up enable 1026 #define PADS_BANK0_GPIO12_PUE_RESET _u(0x0) 1027 #define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008) 1028 #define PADS_BANK0_GPIO12_PUE_MSB _u(3) 1029 #define PADS_BANK0_GPIO12_PUE_LSB _u(3) 1030 #define PADS_BANK0_GPIO12_PUE_ACCESS "RW" 1031 // ----------------------------------------------------------------------------- 1032 // Field : PADS_BANK0_GPIO12_PDE 1033 // Description : Pull down enable 1034 #define PADS_BANK0_GPIO12_PDE_RESET _u(0x1) 1035 #define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004) 1036 #define PADS_BANK0_GPIO12_PDE_MSB _u(2) 1037 #define PADS_BANK0_GPIO12_PDE_LSB _u(2) 1038 #define PADS_BANK0_GPIO12_PDE_ACCESS "RW" 1039 // ----------------------------------------------------------------------------- 1040 // Field : PADS_BANK0_GPIO12_SCHMITT 1041 // Description : Enable schmitt trigger 1042 #define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1) 1043 #define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002) 1044 #define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1) 1045 #define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1) 1046 #define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW" 1047 // ----------------------------------------------------------------------------- 1048 // Field : PADS_BANK0_GPIO12_SLEWFAST 1049 // Description : Slew rate control. 1 = Fast, 0 = Slow 1050 #define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0) 1051 #define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001) 1052 #define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0) 1053 #define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0) 1054 #define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW" 1055 // ============================================================================= 1056 // Register : PADS_BANK0_GPIO13 1057 #define PADS_BANK0_GPIO13_OFFSET _u(0x00000038) 1058 #define PADS_BANK0_GPIO13_BITS _u(0x000001ff) 1059 #define PADS_BANK0_GPIO13_RESET _u(0x00000116) 1060 // ----------------------------------------------------------------------------- 1061 // Field : PADS_BANK0_GPIO13_ISO 1062 // Description : Pad isolation control. Remove this once the pad is configured 1063 // by software. 1064 #define PADS_BANK0_GPIO13_ISO_RESET _u(0x1) 1065 #define PADS_BANK0_GPIO13_ISO_BITS _u(0x00000100) 1066 #define PADS_BANK0_GPIO13_ISO_MSB _u(8) 1067 #define PADS_BANK0_GPIO13_ISO_LSB _u(8) 1068 #define PADS_BANK0_GPIO13_ISO_ACCESS "RW" 1069 // ----------------------------------------------------------------------------- 1070 // Field : PADS_BANK0_GPIO13_OD 1071 // Description : Output disable. Has priority over output enable from 1072 // peripherals 1073 #define PADS_BANK0_GPIO13_OD_RESET _u(0x0) 1074 #define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080) 1075 #define PADS_BANK0_GPIO13_OD_MSB _u(7) 1076 #define PADS_BANK0_GPIO13_OD_LSB _u(7) 1077 #define PADS_BANK0_GPIO13_OD_ACCESS "RW" 1078 // ----------------------------------------------------------------------------- 1079 // Field : PADS_BANK0_GPIO13_IE 1080 // Description : Input enable 1081 #define PADS_BANK0_GPIO13_IE_RESET _u(0x0) 1082 #define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040) 1083 #define PADS_BANK0_GPIO13_IE_MSB _u(6) 1084 #define PADS_BANK0_GPIO13_IE_LSB _u(6) 1085 #define PADS_BANK0_GPIO13_IE_ACCESS "RW" 1086 // ----------------------------------------------------------------------------- 1087 // Field : PADS_BANK0_GPIO13_DRIVE 1088 // Description : Drive strength. 1089 // 0x0 -> 2mA 1090 // 0x1 -> 4mA 1091 // 0x2 -> 8mA 1092 // 0x3 -> 12mA 1093 #define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1) 1094 #define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030) 1095 #define PADS_BANK0_GPIO13_DRIVE_MSB _u(5) 1096 #define PADS_BANK0_GPIO13_DRIVE_LSB _u(4) 1097 #define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW" 1098 #define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0) 1099 #define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1) 1100 #define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2) 1101 #define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3) 1102 // ----------------------------------------------------------------------------- 1103 // Field : PADS_BANK0_GPIO13_PUE 1104 // Description : Pull up enable 1105 #define PADS_BANK0_GPIO13_PUE_RESET _u(0x0) 1106 #define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008) 1107 #define PADS_BANK0_GPIO13_PUE_MSB _u(3) 1108 #define PADS_BANK0_GPIO13_PUE_LSB _u(3) 1109 #define PADS_BANK0_GPIO13_PUE_ACCESS "RW" 1110 // ----------------------------------------------------------------------------- 1111 // Field : PADS_BANK0_GPIO13_PDE 1112 // Description : Pull down enable 1113 #define PADS_BANK0_GPIO13_PDE_RESET _u(0x1) 1114 #define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004) 1115 #define PADS_BANK0_GPIO13_PDE_MSB _u(2) 1116 #define PADS_BANK0_GPIO13_PDE_LSB _u(2) 1117 #define PADS_BANK0_GPIO13_PDE_ACCESS "RW" 1118 // ----------------------------------------------------------------------------- 1119 // Field : PADS_BANK0_GPIO13_SCHMITT 1120 // Description : Enable schmitt trigger 1121 #define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1) 1122 #define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002) 1123 #define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1) 1124 #define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1) 1125 #define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW" 1126 // ----------------------------------------------------------------------------- 1127 // Field : PADS_BANK0_GPIO13_SLEWFAST 1128 // Description : Slew rate control. 1 = Fast, 0 = Slow 1129 #define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0) 1130 #define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001) 1131 #define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0) 1132 #define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0) 1133 #define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW" 1134 // ============================================================================= 1135 // Register : PADS_BANK0_GPIO14 1136 #define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c) 1137 #define PADS_BANK0_GPIO14_BITS _u(0x000001ff) 1138 #define PADS_BANK0_GPIO14_RESET _u(0x00000116) 1139 // ----------------------------------------------------------------------------- 1140 // Field : PADS_BANK0_GPIO14_ISO 1141 // Description : Pad isolation control. Remove this once the pad is configured 1142 // by software. 1143 #define PADS_BANK0_GPIO14_ISO_RESET _u(0x1) 1144 #define PADS_BANK0_GPIO14_ISO_BITS _u(0x00000100) 1145 #define PADS_BANK0_GPIO14_ISO_MSB _u(8) 1146 #define PADS_BANK0_GPIO14_ISO_LSB _u(8) 1147 #define PADS_BANK0_GPIO14_ISO_ACCESS "RW" 1148 // ----------------------------------------------------------------------------- 1149 // Field : PADS_BANK0_GPIO14_OD 1150 // Description : Output disable. Has priority over output enable from 1151 // peripherals 1152 #define PADS_BANK0_GPIO14_OD_RESET _u(0x0) 1153 #define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080) 1154 #define PADS_BANK0_GPIO14_OD_MSB _u(7) 1155 #define PADS_BANK0_GPIO14_OD_LSB _u(7) 1156 #define PADS_BANK0_GPIO14_OD_ACCESS "RW" 1157 // ----------------------------------------------------------------------------- 1158 // Field : PADS_BANK0_GPIO14_IE 1159 // Description : Input enable 1160 #define PADS_BANK0_GPIO14_IE_RESET _u(0x0) 1161 #define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040) 1162 #define PADS_BANK0_GPIO14_IE_MSB _u(6) 1163 #define PADS_BANK0_GPIO14_IE_LSB _u(6) 1164 #define PADS_BANK0_GPIO14_IE_ACCESS "RW" 1165 // ----------------------------------------------------------------------------- 1166 // Field : PADS_BANK0_GPIO14_DRIVE 1167 // Description : Drive strength. 1168 // 0x0 -> 2mA 1169 // 0x1 -> 4mA 1170 // 0x2 -> 8mA 1171 // 0x3 -> 12mA 1172 #define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1) 1173 #define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030) 1174 #define PADS_BANK0_GPIO14_DRIVE_MSB _u(5) 1175 #define PADS_BANK0_GPIO14_DRIVE_LSB _u(4) 1176 #define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW" 1177 #define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0) 1178 #define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1) 1179 #define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2) 1180 #define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3) 1181 // ----------------------------------------------------------------------------- 1182 // Field : PADS_BANK0_GPIO14_PUE 1183 // Description : Pull up enable 1184 #define PADS_BANK0_GPIO14_PUE_RESET _u(0x0) 1185 #define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008) 1186 #define PADS_BANK0_GPIO14_PUE_MSB _u(3) 1187 #define PADS_BANK0_GPIO14_PUE_LSB _u(3) 1188 #define PADS_BANK0_GPIO14_PUE_ACCESS "RW" 1189 // ----------------------------------------------------------------------------- 1190 // Field : PADS_BANK0_GPIO14_PDE 1191 // Description : Pull down enable 1192 #define PADS_BANK0_GPIO14_PDE_RESET _u(0x1) 1193 #define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004) 1194 #define PADS_BANK0_GPIO14_PDE_MSB _u(2) 1195 #define PADS_BANK0_GPIO14_PDE_LSB _u(2) 1196 #define PADS_BANK0_GPIO14_PDE_ACCESS "RW" 1197 // ----------------------------------------------------------------------------- 1198 // Field : PADS_BANK0_GPIO14_SCHMITT 1199 // Description : Enable schmitt trigger 1200 #define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1) 1201 #define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002) 1202 #define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1) 1203 #define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1) 1204 #define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW" 1205 // ----------------------------------------------------------------------------- 1206 // Field : PADS_BANK0_GPIO14_SLEWFAST 1207 // Description : Slew rate control. 1 = Fast, 0 = Slow 1208 #define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0) 1209 #define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001) 1210 #define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0) 1211 #define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0) 1212 #define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW" 1213 // ============================================================================= 1214 // Register : PADS_BANK0_GPIO15 1215 #define PADS_BANK0_GPIO15_OFFSET _u(0x00000040) 1216 #define PADS_BANK0_GPIO15_BITS _u(0x000001ff) 1217 #define PADS_BANK0_GPIO15_RESET _u(0x00000116) 1218 // ----------------------------------------------------------------------------- 1219 // Field : PADS_BANK0_GPIO15_ISO 1220 // Description : Pad isolation control. Remove this once the pad is configured 1221 // by software. 1222 #define PADS_BANK0_GPIO15_ISO_RESET _u(0x1) 1223 #define PADS_BANK0_GPIO15_ISO_BITS _u(0x00000100) 1224 #define PADS_BANK0_GPIO15_ISO_MSB _u(8) 1225 #define PADS_BANK0_GPIO15_ISO_LSB _u(8) 1226 #define PADS_BANK0_GPIO15_ISO_ACCESS "RW" 1227 // ----------------------------------------------------------------------------- 1228 // Field : PADS_BANK0_GPIO15_OD 1229 // Description : Output disable. Has priority over output enable from 1230 // peripherals 1231 #define PADS_BANK0_GPIO15_OD_RESET _u(0x0) 1232 #define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080) 1233 #define PADS_BANK0_GPIO15_OD_MSB _u(7) 1234 #define PADS_BANK0_GPIO15_OD_LSB _u(7) 1235 #define PADS_BANK0_GPIO15_OD_ACCESS "RW" 1236 // ----------------------------------------------------------------------------- 1237 // Field : PADS_BANK0_GPIO15_IE 1238 // Description : Input enable 1239 #define PADS_BANK0_GPIO15_IE_RESET _u(0x0) 1240 #define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040) 1241 #define PADS_BANK0_GPIO15_IE_MSB _u(6) 1242 #define PADS_BANK0_GPIO15_IE_LSB _u(6) 1243 #define PADS_BANK0_GPIO15_IE_ACCESS "RW" 1244 // ----------------------------------------------------------------------------- 1245 // Field : PADS_BANK0_GPIO15_DRIVE 1246 // Description : Drive strength. 1247 // 0x0 -> 2mA 1248 // 0x1 -> 4mA 1249 // 0x2 -> 8mA 1250 // 0x3 -> 12mA 1251 #define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1) 1252 #define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030) 1253 #define PADS_BANK0_GPIO15_DRIVE_MSB _u(5) 1254 #define PADS_BANK0_GPIO15_DRIVE_LSB _u(4) 1255 #define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW" 1256 #define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0) 1257 #define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1) 1258 #define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2) 1259 #define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3) 1260 // ----------------------------------------------------------------------------- 1261 // Field : PADS_BANK0_GPIO15_PUE 1262 // Description : Pull up enable 1263 #define PADS_BANK0_GPIO15_PUE_RESET _u(0x0) 1264 #define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008) 1265 #define PADS_BANK0_GPIO15_PUE_MSB _u(3) 1266 #define PADS_BANK0_GPIO15_PUE_LSB _u(3) 1267 #define PADS_BANK0_GPIO15_PUE_ACCESS "RW" 1268 // ----------------------------------------------------------------------------- 1269 // Field : PADS_BANK0_GPIO15_PDE 1270 // Description : Pull down enable 1271 #define PADS_BANK0_GPIO15_PDE_RESET _u(0x1) 1272 #define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004) 1273 #define PADS_BANK0_GPIO15_PDE_MSB _u(2) 1274 #define PADS_BANK0_GPIO15_PDE_LSB _u(2) 1275 #define PADS_BANK0_GPIO15_PDE_ACCESS "RW" 1276 // ----------------------------------------------------------------------------- 1277 // Field : PADS_BANK0_GPIO15_SCHMITT 1278 // Description : Enable schmitt trigger 1279 #define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1) 1280 #define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002) 1281 #define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1) 1282 #define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1) 1283 #define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW" 1284 // ----------------------------------------------------------------------------- 1285 // Field : PADS_BANK0_GPIO15_SLEWFAST 1286 // Description : Slew rate control. 1 = Fast, 0 = Slow 1287 #define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0) 1288 #define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001) 1289 #define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0) 1290 #define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0) 1291 #define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW" 1292 // ============================================================================= 1293 // Register : PADS_BANK0_GPIO16 1294 #define PADS_BANK0_GPIO16_OFFSET _u(0x00000044) 1295 #define PADS_BANK0_GPIO16_BITS _u(0x000001ff) 1296 #define PADS_BANK0_GPIO16_RESET _u(0x00000116) 1297 // ----------------------------------------------------------------------------- 1298 // Field : PADS_BANK0_GPIO16_ISO 1299 // Description : Pad isolation control. Remove this once the pad is configured 1300 // by software. 1301 #define PADS_BANK0_GPIO16_ISO_RESET _u(0x1) 1302 #define PADS_BANK0_GPIO16_ISO_BITS _u(0x00000100) 1303 #define PADS_BANK0_GPIO16_ISO_MSB _u(8) 1304 #define PADS_BANK0_GPIO16_ISO_LSB _u(8) 1305 #define PADS_BANK0_GPIO16_ISO_ACCESS "RW" 1306 // ----------------------------------------------------------------------------- 1307 // Field : PADS_BANK0_GPIO16_OD 1308 // Description : Output disable. Has priority over output enable from 1309 // peripherals 1310 #define PADS_BANK0_GPIO16_OD_RESET _u(0x0) 1311 #define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080) 1312 #define PADS_BANK0_GPIO16_OD_MSB _u(7) 1313 #define PADS_BANK0_GPIO16_OD_LSB _u(7) 1314 #define PADS_BANK0_GPIO16_OD_ACCESS "RW" 1315 // ----------------------------------------------------------------------------- 1316 // Field : PADS_BANK0_GPIO16_IE 1317 // Description : Input enable 1318 #define PADS_BANK0_GPIO16_IE_RESET _u(0x0) 1319 #define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040) 1320 #define PADS_BANK0_GPIO16_IE_MSB _u(6) 1321 #define PADS_BANK0_GPIO16_IE_LSB _u(6) 1322 #define PADS_BANK0_GPIO16_IE_ACCESS "RW" 1323 // ----------------------------------------------------------------------------- 1324 // Field : PADS_BANK0_GPIO16_DRIVE 1325 // Description : Drive strength. 1326 // 0x0 -> 2mA 1327 // 0x1 -> 4mA 1328 // 0x2 -> 8mA 1329 // 0x3 -> 12mA 1330 #define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1) 1331 #define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030) 1332 #define PADS_BANK0_GPIO16_DRIVE_MSB _u(5) 1333 #define PADS_BANK0_GPIO16_DRIVE_LSB _u(4) 1334 #define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW" 1335 #define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0) 1336 #define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1) 1337 #define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2) 1338 #define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3) 1339 // ----------------------------------------------------------------------------- 1340 // Field : PADS_BANK0_GPIO16_PUE 1341 // Description : Pull up enable 1342 #define PADS_BANK0_GPIO16_PUE_RESET _u(0x0) 1343 #define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008) 1344 #define PADS_BANK0_GPIO16_PUE_MSB _u(3) 1345 #define PADS_BANK0_GPIO16_PUE_LSB _u(3) 1346 #define PADS_BANK0_GPIO16_PUE_ACCESS "RW" 1347 // ----------------------------------------------------------------------------- 1348 // Field : PADS_BANK0_GPIO16_PDE 1349 // Description : Pull down enable 1350 #define PADS_BANK0_GPIO16_PDE_RESET _u(0x1) 1351 #define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004) 1352 #define PADS_BANK0_GPIO16_PDE_MSB _u(2) 1353 #define PADS_BANK0_GPIO16_PDE_LSB _u(2) 1354 #define PADS_BANK0_GPIO16_PDE_ACCESS "RW" 1355 // ----------------------------------------------------------------------------- 1356 // Field : PADS_BANK0_GPIO16_SCHMITT 1357 // Description : Enable schmitt trigger 1358 #define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1) 1359 #define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002) 1360 #define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1) 1361 #define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1) 1362 #define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW" 1363 // ----------------------------------------------------------------------------- 1364 // Field : PADS_BANK0_GPIO16_SLEWFAST 1365 // Description : Slew rate control. 1 = Fast, 0 = Slow 1366 #define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0) 1367 #define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001) 1368 #define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0) 1369 #define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0) 1370 #define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW" 1371 // ============================================================================= 1372 // Register : PADS_BANK0_GPIO17 1373 #define PADS_BANK0_GPIO17_OFFSET _u(0x00000048) 1374 #define PADS_BANK0_GPIO17_BITS _u(0x000001ff) 1375 #define PADS_BANK0_GPIO17_RESET _u(0x00000116) 1376 // ----------------------------------------------------------------------------- 1377 // Field : PADS_BANK0_GPIO17_ISO 1378 // Description : Pad isolation control. Remove this once the pad is configured 1379 // by software. 1380 #define PADS_BANK0_GPIO17_ISO_RESET _u(0x1) 1381 #define PADS_BANK0_GPIO17_ISO_BITS _u(0x00000100) 1382 #define PADS_BANK0_GPIO17_ISO_MSB _u(8) 1383 #define PADS_BANK0_GPIO17_ISO_LSB _u(8) 1384 #define PADS_BANK0_GPIO17_ISO_ACCESS "RW" 1385 // ----------------------------------------------------------------------------- 1386 // Field : PADS_BANK0_GPIO17_OD 1387 // Description : Output disable. Has priority over output enable from 1388 // peripherals 1389 #define PADS_BANK0_GPIO17_OD_RESET _u(0x0) 1390 #define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080) 1391 #define PADS_BANK0_GPIO17_OD_MSB _u(7) 1392 #define PADS_BANK0_GPIO17_OD_LSB _u(7) 1393 #define PADS_BANK0_GPIO17_OD_ACCESS "RW" 1394 // ----------------------------------------------------------------------------- 1395 // Field : PADS_BANK0_GPIO17_IE 1396 // Description : Input enable 1397 #define PADS_BANK0_GPIO17_IE_RESET _u(0x0) 1398 #define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040) 1399 #define PADS_BANK0_GPIO17_IE_MSB _u(6) 1400 #define PADS_BANK0_GPIO17_IE_LSB _u(6) 1401 #define PADS_BANK0_GPIO17_IE_ACCESS "RW" 1402 // ----------------------------------------------------------------------------- 1403 // Field : PADS_BANK0_GPIO17_DRIVE 1404 // Description : Drive strength. 1405 // 0x0 -> 2mA 1406 // 0x1 -> 4mA 1407 // 0x2 -> 8mA 1408 // 0x3 -> 12mA 1409 #define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1) 1410 #define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030) 1411 #define PADS_BANK0_GPIO17_DRIVE_MSB _u(5) 1412 #define PADS_BANK0_GPIO17_DRIVE_LSB _u(4) 1413 #define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW" 1414 #define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0) 1415 #define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1) 1416 #define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2) 1417 #define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3) 1418 // ----------------------------------------------------------------------------- 1419 // Field : PADS_BANK0_GPIO17_PUE 1420 // Description : Pull up enable 1421 #define PADS_BANK0_GPIO17_PUE_RESET _u(0x0) 1422 #define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008) 1423 #define PADS_BANK0_GPIO17_PUE_MSB _u(3) 1424 #define PADS_BANK0_GPIO17_PUE_LSB _u(3) 1425 #define PADS_BANK0_GPIO17_PUE_ACCESS "RW" 1426 // ----------------------------------------------------------------------------- 1427 // Field : PADS_BANK0_GPIO17_PDE 1428 // Description : Pull down enable 1429 #define PADS_BANK0_GPIO17_PDE_RESET _u(0x1) 1430 #define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004) 1431 #define PADS_BANK0_GPIO17_PDE_MSB _u(2) 1432 #define PADS_BANK0_GPIO17_PDE_LSB _u(2) 1433 #define PADS_BANK0_GPIO17_PDE_ACCESS "RW" 1434 // ----------------------------------------------------------------------------- 1435 // Field : PADS_BANK0_GPIO17_SCHMITT 1436 // Description : Enable schmitt trigger 1437 #define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1) 1438 #define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002) 1439 #define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1) 1440 #define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1) 1441 #define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW" 1442 // ----------------------------------------------------------------------------- 1443 // Field : PADS_BANK0_GPIO17_SLEWFAST 1444 // Description : Slew rate control. 1 = Fast, 0 = Slow 1445 #define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0) 1446 #define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001) 1447 #define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0) 1448 #define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0) 1449 #define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW" 1450 // ============================================================================= 1451 // Register : PADS_BANK0_GPIO18 1452 #define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c) 1453 #define PADS_BANK0_GPIO18_BITS _u(0x000001ff) 1454 #define PADS_BANK0_GPIO18_RESET _u(0x00000116) 1455 // ----------------------------------------------------------------------------- 1456 // Field : PADS_BANK0_GPIO18_ISO 1457 // Description : Pad isolation control. Remove this once the pad is configured 1458 // by software. 1459 #define PADS_BANK0_GPIO18_ISO_RESET _u(0x1) 1460 #define PADS_BANK0_GPIO18_ISO_BITS _u(0x00000100) 1461 #define PADS_BANK0_GPIO18_ISO_MSB _u(8) 1462 #define PADS_BANK0_GPIO18_ISO_LSB _u(8) 1463 #define PADS_BANK0_GPIO18_ISO_ACCESS "RW" 1464 // ----------------------------------------------------------------------------- 1465 // Field : PADS_BANK0_GPIO18_OD 1466 // Description : Output disable. Has priority over output enable from 1467 // peripherals 1468 #define PADS_BANK0_GPIO18_OD_RESET _u(0x0) 1469 #define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080) 1470 #define PADS_BANK0_GPIO18_OD_MSB _u(7) 1471 #define PADS_BANK0_GPIO18_OD_LSB _u(7) 1472 #define PADS_BANK0_GPIO18_OD_ACCESS "RW" 1473 // ----------------------------------------------------------------------------- 1474 // Field : PADS_BANK0_GPIO18_IE 1475 // Description : Input enable 1476 #define PADS_BANK0_GPIO18_IE_RESET _u(0x0) 1477 #define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040) 1478 #define PADS_BANK0_GPIO18_IE_MSB _u(6) 1479 #define PADS_BANK0_GPIO18_IE_LSB _u(6) 1480 #define PADS_BANK0_GPIO18_IE_ACCESS "RW" 1481 // ----------------------------------------------------------------------------- 1482 // Field : PADS_BANK0_GPIO18_DRIVE 1483 // Description : Drive strength. 1484 // 0x0 -> 2mA 1485 // 0x1 -> 4mA 1486 // 0x2 -> 8mA 1487 // 0x3 -> 12mA 1488 #define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1) 1489 #define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030) 1490 #define PADS_BANK0_GPIO18_DRIVE_MSB _u(5) 1491 #define PADS_BANK0_GPIO18_DRIVE_LSB _u(4) 1492 #define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW" 1493 #define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0) 1494 #define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1) 1495 #define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2) 1496 #define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3) 1497 // ----------------------------------------------------------------------------- 1498 // Field : PADS_BANK0_GPIO18_PUE 1499 // Description : Pull up enable 1500 #define PADS_BANK0_GPIO18_PUE_RESET _u(0x0) 1501 #define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008) 1502 #define PADS_BANK0_GPIO18_PUE_MSB _u(3) 1503 #define PADS_BANK0_GPIO18_PUE_LSB _u(3) 1504 #define PADS_BANK0_GPIO18_PUE_ACCESS "RW" 1505 // ----------------------------------------------------------------------------- 1506 // Field : PADS_BANK0_GPIO18_PDE 1507 // Description : Pull down enable 1508 #define PADS_BANK0_GPIO18_PDE_RESET _u(0x1) 1509 #define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004) 1510 #define PADS_BANK0_GPIO18_PDE_MSB _u(2) 1511 #define PADS_BANK0_GPIO18_PDE_LSB _u(2) 1512 #define PADS_BANK0_GPIO18_PDE_ACCESS "RW" 1513 // ----------------------------------------------------------------------------- 1514 // Field : PADS_BANK0_GPIO18_SCHMITT 1515 // Description : Enable schmitt trigger 1516 #define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1) 1517 #define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002) 1518 #define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1) 1519 #define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1) 1520 #define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW" 1521 // ----------------------------------------------------------------------------- 1522 // Field : PADS_BANK0_GPIO18_SLEWFAST 1523 // Description : Slew rate control. 1 = Fast, 0 = Slow 1524 #define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0) 1525 #define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001) 1526 #define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0) 1527 #define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0) 1528 #define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW" 1529 // ============================================================================= 1530 // Register : PADS_BANK0_GPIO19 1531 #define PADS_BANK0_GPIO19_OFFSET _u(0x00000050) 1532 #define PADS_BANK0_GPIO19_BITS _u(0x000001ff) 1533 #define PADS_BANK0_GPIO19_RESET _u(0x00000116) 1534 // ----------------------------------------------------------------------------- 1535 // Field : PADS_BANK0_GPIO19_ISO 1536 // Description : Pad isolation control. Remove this once the pad is configured 1537 // by software. 1538 #define PADS_BANK0_GPIO19_ISO_RESET _u(0x1) 1539 #define PADS_BANK0_GPIO19_ISO_BITS _u(0x00000100) 1540 #define PADS_BANK0_GPIO19_ISO_MSB _u(8) 1541 #define PADS_BANK0_GPIO19_ISO_LSB _u(8) 1542 #define PADS_BANK0_GPIO19_ISO_ACCESS "RW" 1543 // ----------------------------------------------------------------------------- 1544 // Field : PADS_BANK0_GPIO19_OD 1545 // Description : Output disable. Has priority over output enable from 1546 // peripherals 1547 #define PADS_BANK0_GPIO19_OD_RESET _u(0x0) 1548 #define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080) 1549 #define PADS_BANK0_GPIO19_OD_MSB _u(7) 1550 #define PADS_BANK0_GPIO19_OD_LSB _u(7) 1551 #define PADS_BANK0_GPIO19_OD_ACCESS "RW" 1552 // ----------------------------------------------------------------------------- 1553 // Field : PADS_BANK0_GPIO19_IE 1554 // Description : Input enable 1555 #define PADS_BANK0_GPIO19_IE_RESET _u(0x0) 1556 #define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040) 1557 #define PADS_BANK0_GPIO19_IE_MSB _u(6) 1558 #define PADS_BANK0_GPIO19_IE_LSB _u(6) 1559 #define PADS_BANK0_GPIO19_IE_ACCESS "RW" 1560 // ----------------------------------------------------------------------------- 1561 // Field : PADS_BANK0_GPIO19_DRIVE 1562 // Description : Drive strength. 1563 // 0x0 -> 2mA 1564 // 0x1 -> 4mA 1565 // 0x2 -> 8mA 1566 // 0x3 -> 12mA 1567 #define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1) 1568 #define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030) 1569 #define PADS_BANK0_GPIO19_DRIVE_MSB _u(5) 1570 #define PADS_BANK0_GPIO19_DRIVE_LSB _u(4) 1571 #define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW" 1572 #define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0) 1573 #define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1) 1574 #define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2) 1575 #define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3) 1576 // ----------------------------------------------------------------------------- 1577 // Field : PADS_BANK0_GPIO19_PUE 1578 // Description : Pull up enable 1579 #define PADS_BANK0_GPIO19_PUE_RESET _u(0x0) 1580 #define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008) 1581 #define PADS_BANK0_GPIO19_PUE_MSB _u(3) 1582 #define PADS_BANK0_GPIO19_PUE_LSB _u(3) 1583 #define PADS_BANK0_GPIO19_PUE_ACCESS "RW" 1584 // ----------------------------------------------------------------------------- 1585 // Field : PADS_BANK0_GPIO19_PDE 1586 // Description : Pull down enable 1587 #define PADS_BANK0_GPIO19_PDE_RESET _u(0x1) 1588 #define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004) 1589 #define PADS_BANK0_GPIO19_PDE_MSB _u(2) 1590 #define PADS_BANK0_GPIO19_PDE_LSB _u(2) 1591 #define PADS_BANK0_GPIO19_PDE_ACCESS "RW" 1592 // ----------------------------------------------------------------------------- 1593 // Field : PADS_BANK0_GPIO19_SCHMITT 1594 // Description : Enable schmitt trigger 1595 #define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1) 1596 #define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002) 1597 #define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1) 1598 #define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1) 1599 #define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW" 1600 // ----------------------------------------------------------------------------- 1601 // Field : PADS_BANK0_GPIO19_SLEWFAST 1602 // Description : Slew rate control. 1 = Fast, 0 = Slow 1603 #define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0) 1604 #define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001) 1605 #define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0) 1606 #define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0) 1607 #define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW" 1608 // ============================================================================= 1609 // Register : PADS_BANK0_GPIO20 1610 #define PADS_BANK0_GPIO20_OFFSET _u(0x00000054) 1611 #define PADS_BANK0_GPIO20_BITS _u(0x000001ff) 1612 #define PADS_BANK0_GPIO20_RESET _u(0x00000116) 1613 // ----------------------------------------------------------------------------- 1614 // Field : PADS_BANK0_GPIO20_ISO 1615 // Description : Pad isolation control. Remove this once the pad is configured 1616 // by software. 1617 #define PADS_BANK0_GPIO20_ISO_RESET _u(0x1) 1618 #define PADS_BANK0_GPIO20_ISO_BITS _u(0x00000100) 1619 #define PADS_BANK0_GPIO20_ISO_MSB _u(8) 1620 #define PADS_BANK0_GPIO20_ISO_LSB _u(8) 1621 #define PADS_BANK0_GPIO20_ISO_ACCESS "RW" 1622 // ----------------------------------------------------------------------------- 1623 // Field : PADS_BANK0_GPIO20_OD 1624 // Description : Output disable. Has priority over output enable from 1625 // peripherals 1626 #define PADS_BANK0_GPIO20_OD_RESET _u(0x0) 1627 #define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080) 1628 #define PADS_BANK0_GPIO20_OD_MSB _u(7) 1629 #define PADS_BANK0_GPIO20_OD_LSB _u(7) 1630 #define PADS_BANK0_GPIO20_OD_ACCESS "RW" 1631 // ----------------------------------------------------------------------------- 1632 // Field : PADS_BANK0_GPIO20_IE 1633 // Description : Input enable 1634 #define PADS_BANK0_GPIO20_IE_RESET _u(0x0) 1635 #define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040) 1636 #define PADS_BANK0_GPIO20_IE_MSB _u(6) 1637 #define PADS_BANK0_GPIO20_IE_LSB _u(6) 1638 #define PADS_BANK0_GPIO20_IE_ACCESS "RW" 1639 // ----------------------------------------------------------------------------- 1640 // Field : PADS_BANK0_GPIO20_DRIVE 1641 // Description : Drive strength. 1642 // 0x0 -> 2mA 1643 // 0x1 -> 4mA 1644 // 0x2 -> 8mA 1645 // 0x3 -> 12mA 1646 #define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1) 1647 #define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030) 1648 #define PADS_BANK0_GPIO20_DRIVE_MSB _u(5) 1649 #define PADS_BANK0_GPIO20_DRIVE_LSB _u(4) 1650 #define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW" 1651 #define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0) 1652 #define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1) 1653 #define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2) 1654 #define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3) 1655 // ----------------------------------------------------------------------------- 1656 // Field : PADS_BANK0_GPIO20_PUE 1657 // Description : Pull up enable 1658 #define PADS_BANK0_GPIO20_PUE_RESET _u(0x0) 1659 #define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008) 1660 #define PADS_BANK0_GPIO20_PUE_MSB _u(3) 1661 #define PADS_BANK0_GPIO20_PUE_LSB _u(3) 1662 #define PADS_BANK0_GPIO20_PUE_ACCESS "RW" 1663 // ----------------------------------------------------------------------------- 1664 // Field : PADS_BANK0_GPIO20_PDE 1665 // Description : Pull down enable 1666 #define PADS_BANK0_GPIO20_PDE_RESET _u(0x1) 1667 #define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004) 1668 #define PADS_BANK0_GPIO20_PDE_MSB _u(2) 1669 #define PADS_BANK0_GPIO20_PDE_LSB _u(2) 1670 #define PADS_BANK0_GPIO20_PDE_ACCESS "RW" 1671 // ----------------------------------------------------------------------------- 1672 // Field : PADS_BANK0_GPIO20_SCHMITT 1673 // Description : Enable schmitt trigger 1674 #define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1) 1675 #define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002) 1676 #define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1) 1677 #define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1) 1678 #define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW" 1679 // ----------------------------------------------------------------------------- 1680 // Field : PADS_BANK0_GPIO20_SLEWFAST 1681 // Description : Slew rate control. 1 = Fast, 0 = Slow 1682 #define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0) 1683 #define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001) 1684 #define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0) 1685 #define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0) 1686 #define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW" 1687 // ============================================================================= 1688 // Register : PADS_BANK0_GPIO21 1689 #define PADS_BANK0_GPIO21_OFFSET _u(0x00000058) 1690 #define PADS_BANK0_GPIO21_BITS _u(0x000001ff) 1691 #define PADS_BANK0_GPIO21_RESET _u(0x00000116) 1692 // ----------------------------------------------------------------------------- 1693 // Field : PADS_BANK0_GPIO21_ISO 1694 // Description : Pad isolation control. Remove this once the pad is configured 1695 // by software. 1696 #define PADS_BANK0_GPIO21_ISO_RESET _u(0x1) 1697 #define PADS_BANK0_GPIO21_ISO_BITS _u(0x00000100) 1698 #define PADS_BANK0_GPIO21_ISO_MSB _u(8) 1699 #define PADS_BANK0_GPIO21_ISO_LSB _u(8) 1700 #define PADS_BANK0_GPIO21_ISO_ACCESS "RW" 1701 // ----------------------------------------------------------------------------- 1702 // Field : PADS_BANK0_GPIO21_OD 1703 // Description : Output disable. Has priority over output enable from 1704 // peripherals 1705 #define PADS_BANK0_GPIO21_OD_RESET _u(0x0) 1706 #define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080) 1707 #define PADS_BANK0_GPIO21_OD_MSB _u(7) 1708 #define PADS_BANK0_GPIO21_OD_LSB _u(7) 1709 #define PADS_BANK0_GPIO21_OD_ACCESS "RW" 1710 // ----------------------------------------------------------------------------- 1711 // Field : PADS_BANK0_GPIO21_IE 1712 // Description : Input enable 1713 #define PADS_BANK0_GPIO21_IE_RESET _u(0x0) 1714 #define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040) 1715 #define PADS_BANK0_GPIO21_IE_MSB _u(6) 1716 #define PADS_BANK0_GPIO21_IE_LSB _u(6) 1717 #define PADS_BANK0_GPIO21_IE_ACCESS "RW" 1718 // ----------------------------------------------------------------------------- 1719 // Field : PADS_BANK0_GPIO21_DRIVE 1720 // Description : Drive strength. 1721 // 0x0 -> 2mA 1722 // 0x1 -> 4mA 1723 // 0x2 -> 8mA 1724 // 0x3 -> 12mA 1725 #define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1) 1726 #define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030) 1727 #define PADS_BANK0_GPIO21_DRIVE_MSB _u(5) 1728 #define PADS_BANK0_GPIO21_DRIVE_LSB _u(4) 1729 #define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW" 1730 #define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0) 1731 #define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1) 1732 #define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2) 1733 #define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3) 1734 // ----------------------------------------------------------------------------- 1735 // Field : PADS_BANK0_GPIO21_PUE 1736 // Description : Pull up enable 1737 #define PADS_BANK0_GPIO21_PUE_RESET _u(0x0) 1738 #define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008) 1739 #define PADS_BANK0_GPIO21_PUE_MSB _u(3) 1740 #define PADS_BANK0_GPIO21_PUE_LSB _u(3) 1741 #define PADS_BANK0_GPIO21_PUE_ACCESS "RW" 1742 // ----------------------------------------------------------------------------- 1743 // Field : PADS_BANK0_GPIO21_PDE 1744 // Description : Pull down enable 1745 #define PADS_BANK0_GPIO21_PDE_RESET _u(0x1) 1746 #define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004) 1747 #define PADS_BANK0_GPIO21_PDE_MSB _u(2) 1748 #define PADS_BANK0_GPIO21_PDE_LSB _u(2) 1749 #define PADS_BANK0_GPIO21_PDE_ACCESS "RW" 1750 // ----------------------------------------------------------------------------- 1751 // Field : PADS_BANK0_GPIO21_SCHMITT 1752 // Description : Enable schmitt trigger 1753 #define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1) 1754 #define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002) 1755 #define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1) 1756 #define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1) 1757 #define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW" 1758 // ----------------------------------------------------------------------------- 1759 // Field : PADS_BANK0_GPIO21_SLEWFAST 1760 // Description : Slew rate control. 1 = Fast, 0 = Slow 1761 #define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0) 1762 #define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001) 1763 #define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0) 1764 #define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0) 1765 #define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW" 1766 // ============================================================================= 1767 // Register : PADS_BANK0_GPIO22 1768 #define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c) 1769 #define PADS_BANK0_GPIO22_BITS _u(0x000001ff) 1770 #define PADS_BANK0_GPIO22_RESET _u(0x00000116) 1771 // ----------------------------------------------------------------------------- 1772 // Field : PADS_BANK0_GPIO22_ISO 1773 // Description : Pad isolation control. Remove this once the pad is configured 1774 // by software. 1775 #define PADS_BANK0_GPIO22_ISO_RESET _u(0x1) 1776 #define PADS_BANK0_GPIO22_ISO_BITS _u(0x00000100) 1777 #define PADS_BANK0_GPIO22_ISO_MSB _u(8) 1778 #define PADS_BANK0_GPIO22_ISO_LSB _u(8) 1779 #define PADS_BANK0_GPIO22_ISO_ACCESS "RW" 1780 // ----------------------------------------------------------------------------- 1781 // Field : PADS_BANK0_GPIO22_OD 1782 // Description : Output disable. Has priority over output enable from 1783 // peripherals 1784 #define PADS_BANK0_GPIO22_OD_RESET _u(0x0) 1785 #define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080) 1786 #define PADS_BANK0_GPIO22_OD_MSB _u(7) 1787 #define PADS_BANK0_GPIO22_OD_LSB _u(7) 1788 #define PADS_BANK0_GPIO22_OD_ACCESS "RW" 1789 // ----------------------------------------------------------------------------- 1790 // Field : PADS_BANK0_GPIO22_IE 1791 // Description : Input enable 1792 #define PADS_BANK0_GPIO22_IE_RESET _u(0x0) 1793 #define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040) 1794 #define PADS_BANK0_GPIO22_IE_MSB _u(6) 1795 #define PADS_BANK0_GPIO22_IE_LSB _u(6) 1796 #define PADS_BANK0_GPIO22_IE_ACCESS "RW" 1797 // ----------------------------------------------------------------------------- 1798 // Field : PADS_BANK0_GPIO22_DRIVE 1799 // Description : Drive strength. 1800 // 0x0 -> 2mA 1801 // 0x1 -> 4mA 1802 // 0x2 -> 8mA 1803 // 0x3 -> 12mA 1804 #define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1) 1805 #define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030) 1806 #define PADS_BANK0_GPIO22_DRIVE_MSB _u(5) 1807 #define PADS_BANK0_GPIO22_DRIVE_LSB _u(4) 1808 #define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW" 1809 #define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0) 1810 #define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1) 1811 #define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2) 1812 #define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3) 1813 // ----------------------------------------------------------------------------- 1814 // Field : PADS_BANK0_GPIO22_PUE 1815 // Description : Pull up enable 1816 #define PADS_BANK0_GPIO22_PUE_RESET _u(0x0) 1817 #define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008) 1818 #define PADS_BANK0_GPIO22_PUE_MSB _u(3) 1819 #define PADS_BANK0_GPIO22_PUE_LSB _u(3) 1820 #define PADS_BANK0_GPIO22_PUE_ACCESS "RW" 1821 // ----------------------------------------------------------------------------- 1822 // Field : PADS_BANK0_GPIO22_PDE 1823 // Description : Pull down enable 1824 #define PADS_BANK0_GPIO22_PDE_RESET _u(0x1) 1825 #define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004) 1826 #define PADS_BANK0_GPIO22_PDE_MSB _u(2) 1827 #define PADS_BANK0_GPIO22_PDE_LSB _u(2) 1828 #define PADS_BANK0_GPIO22_PDE_ACCESS "RW" 1829 // ----------------------------------------------------------------------------- 1830 // Field : PADS_BANK0_GPIO22_SCHMITT 1831 // Description : Enable schmitt trigger 1832 #define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1) 1833 #define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002) 1834 #define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1) 1835 #define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1) 1836 #define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW" 1837 // ----------------------------------------------------------------------------- 1838 // Field : PADS_BANK0_GPIO22_SLEWFAST 1839 // Description : Slew rate control. 1 = Fast, 0 = Slow 1840 #define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0) 1841 #define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001) 1842 #define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0) 1843 #define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0) 1844 #define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW" 1845 // ============================================================================= 1846 // Register : PADS_BANK0_GPIO23 1847 #define PADS_BANK0_GPIO23_OFFSET _u(0x00000060) 1848 #define PADS_BANK0_GPIO23_BITS _u(0x000001ff) 1849 #define PADS_BANK0_GPIO23_RESET _u(0x00000116) 1850 // ----------------------------------------------------------------------------- 1851 // Field : PADS_BANK0_GPIO23_ISO 1852 // Description : Pad isolation control. Remove this once the pad is configured 1853 // by software. 1854 #define PADS_BANK0_GPIO23_ISO_RESET _u(0x1) 1855 #define PADS_BANK0_GPIO23_ISO_BITS _u(0x00000100) 1856 #define PADS_BANK0_GPIO23_ISO_MSB _u(8) 1857 #define PADS_BANK0_GPIO23_ISO_LSB _u(8) 1858 #define PADS_BANK0_GPIO23_ISO_ACCESS "RW" 1859 // ----------------------------------------------------------------------------- 1860 // Field : PADS_BANK0_GPIO23_OD 1861 // Description : Output disable. Has priority over output enable from 1862 // peripherals 1863 #define PADS_BANK0_GPIO23_OD_RESET _u(0x0) 1864 #define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080) 1865 #define PADS_BANK0_GPIO23_OD_MSB _u(7) 1866 #define PADS_BANK0_GPIO23_OD_LSB _u(7) 1867 #define PADS_BANK0_GPIO23_OD_ACCESS "RW" 1868 // ----------------------------------------------------------------------------- 1869 // Field : PADS_BANK0_GPIO23_IE 1870 // Description : Input enable 1871 #define PADS_BANK0_GPIO23_IE_RESET _u(0x0) 1872 #define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040) 1873 #define PADS_BANK0_GPIO23_IE_MSB _u(6) 1874 #define PADS_BANK0_GPIO23_IE_LSB _u(6) 1875 #define PADS_BANK0_GPIO23_IE_ACCESS "RW" 1876 // ----------------------------------------------------------------------------- 1877 // Field : PADS_BANK0_GPIO23_DRIVE 1878 // Description : Drive strength. 1879 // 0x0 -> 2mA 1880 // 0x1 -> 4mA 1881 // 0x2 -> 8mA 1882 // 0x3 -> 12mA 1883 #define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1) 1884 #define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030) 1885 #define PADS_BANK0_GPIO23_DRIVE_MSB _u(5) 1886 #define PADS_BANK0_GPIO23_DRIVE_LSB _u(4) 1887 #define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW" 1888 #define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0) 1889 #define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1) 1890 #define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2) 1891 #define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3) 1892 // ----------------------------------------------------------------------------- 1893 // Field : PADS_BANK0_GPIO23_PUE 1894 // Description : Pull up enable 1895 #define PADS_BANK0_GPIO23_PUE_RESET _u(0x0) 1896 #define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008) 1897 #define PADS_BANK0_GPIO23_PUE_MSB _u(3) 1898 #define PADS_BANK0_GPIO23_PUE_LSB _u(3) 1899 #define PADS_BANK0_GPIO23_PUE_ACCESS "RW" 1900 // ----------------------------------------------------------------------------- 1901 // Field : PADS_BANK0_GPIO23_PDE 1902 // Description : Pull down enable 1903 #define PADS_BANK0_GPIO23_PDE_RESET _u(0x1) 1904 #define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004) 1905 #define PADS_BANK0_GPIO23_PDE_MSB _u(2) 1906 #define PADS_BANK0_GPIO23_PDE_LSB _u(2) 1907 #define PADS_BANK0_GPIO23_PDE_ACCESS "RW" 1908 // ----------------------------------------------------------------------------- 1909 // Field : PADS_BANK0_GPIO23_SCHMITT 1910 // Description : Enable schmitt trigger 1911 #define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1) 1912 #define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002) 1913 #define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1) 1914 #define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1) 1915 #define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW" 1916 // ----------------------------------------------------------------------------- 1917 // Field : PADS_BANK0_GPIO23_SLEWFAST 1918 // Description : Slew rate control. 1 = Fast, 0 = Slow 1919 #define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0) 1920 #define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001) 1921 #define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0) 1922 #define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0) 1923 #define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW" 1924 // ============================================================================= 1925 // Register : PADS_BANK0_GPIO24 1926 #define PADS_BANK0_GPIO24_OFFSET _u(0x00000064) 1927 #define PADS_BANK0_GPIO24_BITS _u(0x000001ff) 1928 #define PADS_BANK0_GPIO24_RESET _u(0x00000116) 1929 // ----------------------------------------------------------------------------- 1930 // Field : PADS_BANK0_GPIO24_ISO 1931 // Description : Pad isolation control. Remove this once the pad is configured 1932 // by software. 1933 #define PADS_BANK0_GPIO24_ISO_RESET _u(0x1) 1934 #define PADS_BANK0_GPIO24_ISO_BITS _u(0x00000100) 1935 #define PADS_BANK0_GPIO24_ISO_MSB _u(8) 1936 #define PADS_BANK0_GPIO24_ISO_LSB _u(8) 1937 #define PADS_BANK0_GPIO24_ISO_ACCESS "RW" 1938 // ----------------------------------------------------------------------------- 1939 // Field : PADS_BANK0_GPIO24_OD 1940 // Description : Output disable. Has priority over output enable from 1941 // peripherals 1942 #define PADS_BANK0_GPIO24_OD_RESET _u(0x0) 1943 #define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080) 1944 #define PADS_BANK0_GPIO24_OD_MSB _u(7) 1945 #define PADS_BANK0_GPIO24_OD_LSB _u(7) 1946 #define PADS_BANK0_GPIO24_OD_ACCESS "RW" 1947 // ----------------------------------------------------------------------------- 1948 // Field : PADS_BANK0_GPIO24_IE 1949 // Description : Input enable 1950 #define PADS_BANK0_GPIO24_IE_RESET _u(0x0) 1951 #define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040) 1952 #define PADS_BANK0_GPIO24_IE_MSB _u(6) 1953 #define PADS_BANK0_GPIO24_IE_LSB _u(6) 1954 #define PADS_BANK0_GPIO24_IE_ACCESS "RW" 1955 // ----------------------------------------------------------------------------- 1956 // Field : PADS_BANK0_GPIO24_DRIVE 1957 // Description : Drive strength. 1958 // 0x0 -> 2mA 1959 // 0x1 -> 4mA 1960 // 0x2 -> 8mA 1961 // 0x3 -> 12mA 1962 #define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1) 1963 #define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030) 1964 #define PADS_BANK0_GPIO24_DRIVE_MSB _u(5) 1965 #define PADS_BANK0_GPIO24_DRIVE_LSB _u(4) 1966 #define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW" 1967 #define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0) 1968 #define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1) 1969 #define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2) 1970 #define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3) 1971 // ----------------------------------------------------------------------------- 1972 // Field : PADS_BANK0_GPIO24_PUE 1973 // Description : Pull up enable 1974 #define PADS_BANK0_GPIO24_PUE_RESET _u(0x0) 1975 #define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008) 1976 #define PADS_BANK0_GPIO24_PUE_MSB _u(3) 1977 #define PADS_BANK0_GPIO24_PUE_LSB _u(3) 1978 #define PADS_BANK0_GPIO24_PUE_ACCESS "RW" 1979 // ----------------------------------------------------------------------------- 1980 // Field : PADS_BANK0_GPIO24_PDE 1981 // Description : Pull down enable 1982 #define PADS_BANK0_GPIO24_PDE_RESET _u(0x1) 1983 #define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004) 1984 #define PADS_BANK0_GPIO24_PDE_MSB _u(2) 1985 #define PADS_BANK0_GPIO24_PDE_LSB _u(2) 1986 #define PADS_BANK0_GPIO24_PDE_ACCESS "RW" 1987 // ----------------------------------------------------------------------------- 1988 // Field : PADS_BANK0_GPIO24_SCHMITT 1989 // Description : Enable schmitt trigger 1990 #define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1) 1991 #define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002) 1992 #define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1) 1993 #define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1) 1994 #define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW" 1995 // ----------------------------------------------------------------------------- 1996 // Field : PADS_BANK0_GPIO24_SLEWFAST 1997 // Description : Slew rate control. 1 = Fast, 0 = Slow 1998 #define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0) 1999 #define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001) 2000 #define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0) 2001 #define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0) 2002 #define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW" 2003 // ============================================================================= 2004 // Register : PADS_BANK0_GPIO25 2005 #define PADS_BANK0_GPIO25_OFFSET _u(0x00000068) 2006 #define PADS_BANK0_GPIO25_BITS _u(0x000001ff) 2007 #define PADS_BANK0_GPIO25_RESET _u(0x00000116) 2008 // ----------------------------------------------------------------------------- 2009 // Field : PADS_BANK0_GPIO25_ISO 2010 // Description : Pad isolation control. Remove this once the pad is configured 2011 // by software. 2012 #define PADS_BANK0_GPIO25_ISO_RESET _u(0x1) 2013 #define PADS_BANK0_GPIO25_ISO_BITS _u(0x00000100) 2014 #define PADS_BANK0_GPIO25_ISO_MSB _u(8) 2015 #define PADS_BANK0_GPIO25_ISO_LSB _u(8) 2016 #define PADS_BANK0_GPIO25_ISO_ACCESS "RW" 2017 // ----------------------------------------------------------------------------- 2018 // Field : PADS_BANK0_GPIO25_OD 2019 // Description : Output disable. Has priority over output enable from 2020 // peripherals 2021 #define PADS_BANK0_GPIO25_OD_RESET _u(0x0) 2022 #define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080) 2023 #define PADS_BANK0_GPIO25_OD_MSB _u(7) 2024 #define PADS_BANK0_GPIO25_OD_LSB _u(7) 2025 #define PADS_BANK0_GPIO25_OD_ACCESS "RW" 2026 // ----------------------------------------------------------------------------- 2027 // Field : PADS_BANK0_GPIO25_IE 2028 // Description : Input enable 2029 #define PADS_BANK0_GPIO25_IE_RESET _u(0x0) 2030 #define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040) 2031 #define PADS_BANK0_GPIO25_IE_MSB _u(6) 2032 #define PADS_BANK0_GPIO25_IE_LSB _u(6) 2033 #define PADS_BANK0_GPIO25_IE_ACCESS "RW" 2034 // ----------------------------------------------------------------------------- 2035 // Field : PADS_BANK0_GPIO25_DRIVE 2036 // Description : Drive strength. 2037 // 0x0 -> 2mA 2038 // 0x1 -> 4mA 2039 // 0x2 -> 8mA 2040 // 0x3 -> 12mA 2041 #define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1) 2042 #define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030) 2043 #define PADS_BANK0_GPIO25_DRIVE_MSB _u(5) 2044 #define PADS_BANK0_GPIO25_DRIVE_LSB _u(4) 2045 #define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW" 2046 #define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0) 2047 #define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1) 2048 #define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2) 2049 #define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3) 2050 // ----------------------------------------------------------------------------- 2051 // Field : PADS_BANK0_GPIO25_PUE 2052 // Description : Pull up enable 2053 #define PADS_BANK0_GPIO25_PUE_RESET _u(0x0) 2054 #define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008) 2055 #define PADS_BANK0_GPIO25_PUE_MSB _u(3) 2056 #define PADS_BANK0_GPIO25_PUE_LSB _u(3) 2057 #define PADS_BANK0_GPIO25_PUE_ACCESS "RW" 2058 // ----------------------------------------------------------------------------- 2059 // Field : PADS_BANK0_GPIO25_PDE 2060 // Description : Pull down enable 2061 #define PADS_BANK0_GPIO25_PDE_RESET _u(0x1) 2062 #define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004) 2063 #define PADS_BANK0_GPIO25_PDE_MSB _u(2) 2064 #define PADS_BANK0_GPIO25_PDE_LSB _u(2) 2065 #define PADS_BANK0_GPIO25_PDE_ACCESS "RW" 2066 // ----------------------------------------------------------------------------- 2067 // Field : PADS_BANK0_GPIO25_SCHMITT 2068 // Description : Enable schmitt trigger 2069 #define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1) 2070 #define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002) 2071 #define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1) 2072 #define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1) 2073 #define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW" 2074 // ----------------------------------------------------------------------------- 2075 // Field : PADS_BANK0_GPIO25_SLEWFAST 2076 // Description : Slew rate control. 1 = Fast, 0 = Slow 2077 #define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0) 2078 #define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001) 2079 #define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0) 2080 #define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0) 2081 #define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW" 2082 // ============================================================================= 2083 // Register : PADS_BANK0_GPIO26 2084 #define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c) 2085 #define PADS_BANK0_GPIO26_BITS _u(0x000001ff) 2086 #define PADS_BANK0_GPIO26_RESET _u(0x00000116) 2087 // ----------------------------------------------------------------------------- 2088 // Field : PADS_BANK0_GPIO26_ISO 2089 // Description : Pad isolation control. Remove this once the pad is configured 2090 // by software. 2091 #define PADS_BANK0_GPIO26_ISO_RESET _u(0x1) 2092 #define PADS_BANK0_GPIO26_ISO_BITS _u(0x00000100) 2093 #define PADS_BANK0_GPIO26_ISO_MSB _u(8) 2094 #define PADS_BANK0_GPIO26_ISO_LSB _u(8) 2095 #define PADS_BANK0_GPIO26_ISO_ACCESS "RW" 2096 // ----------------------------------------------------------------------------- 2097 // Field : PADS_BANK0_GPIO26_OD 2098 // Description : Output disable. Has priority over output enable from 2099 // peripherals 2100 #define PADS_BANK0_GPIO26_OD_RESET _u(0x0) 2101 #define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080) 2102 #define PADS_BANK0_GPIO26_OD_MSB _u(7) 2103 #define PADS_BANK0_GPIO26_OD_LSB _u(7) 2104 #define PADS_BANK0_GPIO26_OD_ACCESS "RW" 2105 // ----------------------------------------------------------------------------- 2106 // Field : PADS_BANK0_GPIO26_IE 2107 // Description : Input enable 2108 #define PADS_BANK0_GPIO26_IE_RESET _u(0x0) 2109 #define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040) 2110 #define PADS_BANK0_GPIO26_IE_MSB _u(6) 2111 #define PADS_BANK0_GPIO26_IE_LSB _u(6) 2112 #define PADS_BANK0_GPIO26_IE_ACCESS "RW" 2113 // ----------------------------------------------------------------------------- 2114 // Field : PADS_BANK0_GPIO26_DRIVE 2115 // Description : Drive strength. 2116 // 0x0 -> 2mA 2117 // 0x1 -> 4mA 2118 // 0x2 -> 8mA 2119 // 0x3 -> 12mA 2120 #define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1) 2121 #define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030) 2122 #define PADS_BANK0_GPIO26_DRIVE_MSB _u(5) 2123 #define PADS_BANK0_GPIO26_DRIVE_LSB _u(4) 2124 #define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW" 2125 #define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0) 2126 #define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1) 2127 #define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2) 2128 #define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3) 2129 // ----------------------------------------------------------------------------- 2130 // Field : PADS_BANK0_GPIO26_PUE 2131 // Description : Pull up enable 2132 #define PADS_BANK0_GPIO26_PUE_RESET _u(0x0) 2133 #define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008) 2134 #define PADS_BANK0_GPIO26_PUE_MSB _u(3) 2135 #define PADS_BANK0_GPIO26_PUE_LSB _u(3) 2136 #define PADS_BANK0_GPIO26_PUE_ACCESS "RW" 2137 // ----------------------------------------------------------------------------- 2138 // Field : PADS_BANK0_GPIO26_PDE 2139 // Description : Pull down enable 2140 #define PADS_BANK0_GPIO26_PDE_RESET _u(0x1) 2141 #define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004) 2142 #define PADS_BANK0_GPIO26_PDE_MSB _u(2) 2143 #define PADS_BANK0_GPIO26_PDE_LSB _u(2) 2144 #define PADS_BANK0_GPIO26_PDE_ACCESS "RW" 2145 // ----------------------------------------------------------------------------- 2146 // Field : PADS_BANK0_GPIO26_SCHMITT 2147 // Description : Enable schmitt trigger 2148 #define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1) 2149 #define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002) 2150 #define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1) 2151 #define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1) 2152 #define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW" 2153 // ----------------------------------------------------------------------------- 2154 // Field : PADS_BANK0_GPIO26_SLEWFAST 2155 // Description : Slew rate control. 1 = Fast, 0 = Slow 2156 #define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0) 2157 #define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001) 2158 #define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0) 2159 #define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0) 2160 #define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW" 2161 // ============================================================================= 2162 // Register : PADS_BANK0_GPIO27 2163 #define PADS_BANK0_GPIO27_OFFSET _u(0x00000070) 2164 #define PADS_BANK0_GPIO27_BITS _u(0x000001ff) 2165 #define PADS_BANK0_GPIO27_RESET _u(0x00000116) 2166 // ----------------------------------------------------------------------------- 2167 // Field : PADS_BANK0_GPIO27_ISO 2168 // Description : Pad isolation control. Remove this once the pad is configured 2169 // by software. 2170 #define PADS_BANK0_GPIO27_ISO_RESET _u(0x1) 2171 #define PADS_BANK0_GPIO27_ISO_BITS _u(0x00000100) 2172 #define PADS_BANK0_GPIO27_ISO_MSB _u(8) 2173 #define PADS_BANK0_GPIO27_ISO_LSB _u(8) 2174 #define PADS_BANK0_GPIO27_ISO_ACCESS "RW" 2175 // ----------------------------------------------------------------------------- 2176 // Field : PADS_BANK0_GPIO27_OD 2177 // Description : Output disable. Has priority over output enable from 2178 // peripherals 2179 #define PADS_BANK0_GPIO27_OD_RESET _u(0x0) 2180 #define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080) 2181 #define PADS_BANK0_GPIO27_OD_MSB _u(7) 2182 #define PADS_BANK0_GPIO27_OD_LSB _u(7) 2183 #define PADS_BANK0_GPIO27_OD_ACCESS "RW" 2184 // ----------------------------------------------------------------------------- 2185 // Field : PADS_BANK0_GPIO27_IE 2186 // Description : Input enable 2187 #define PADS_BANK0_GPIO27_IE_RESET _u(0x0) 2188 #define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040) 2189 #define PADS_BANK0_GPIO27_IE_MSB _u(6) 2190 #define PADS_BANK0_GPIO27_IE_LSB _u(6) 2191 #define PADS_BANK0_GPIO27_IE_ACCESS "RW" 2192 // ----------------------------------------------------------------------------- 2193 // Field : PADS_BANK0_GPIO27_DRIVE 2194 // Description : Drive strength. 2195 // 0x0 -> 2mA 2196 // 0x1 -> 4mA 2197 // 0x2 -> 8mA 2198 // 0x3 -> 12mA 2199 #define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1) 2200 #define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030) 2201 #define PADS_BANK0_GPIO27_DRIVE_MSB _u(5) 2202 #define PADS_BANK0_GPIO27_DRIVE_LSB _u(4) 2203 #define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW" 2204 #define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0) 2205 #define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1) 2206 #define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2) 2207 #define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3) 2208 // ----------------------------------------------------------------------------- 2209 // Field : PADS_BANK0_GPIO27_PUE 2210 // Description : Pull up enable 2211 #define PADS_BANK0_GPIO27_PUE_RESET _u(0x0) 2212 #define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008) 2213 #define PADS_BANK0_GPIO27_PUE_MSB _u(3) 2214 #define PADS_BANK0_GPIO27_PUE_LSB _u(3) 2215 #define PADS_BANK0_GPIO27_PUE_ACCESS "RW" 2216 // ----------------------------------------------------------------------------- 2217 // Field : PADS_BANK0_GPIO27_PDE 2218 // Description : Pull down enable 2219 #define PADS_BANK0_GPIO27_PDE_RESET _u(0x1) 2220 #define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004) 2221 #define PADS_BANK0_GPIO27_PDE_MSB _u(2) 2222 #define PADS_BANK0_GPIO27_PDE_LSB _u(2) 2223 #define PADS_BANK0_GPIO27_PDE_ACCESS "RW" 2224 // ----------------------------------------------------------------------------- 2225 // Field : PADS_BANK0_GPIO27_SCHMITT 2226 // Description : Enable schmitt trigger 2227 #define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1) 2228 #define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002) 2229 #define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1) 2230 #define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1) 2231 #define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW" 2232 // ----------------------------------------------------------------------------- 2233 // Field : PADS_BANK0_GPIO27_SLEWFAST 2234 // Description : Slew rate control. 1 = Fast, 0 = Slow 2235 #define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0) 2236 #define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001) 2237 #define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0) 2238 #define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0) 2239 #define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW" 2240 // ============================================================================= 2241 // Register : PADS_BANK0_GPIO28 2242 #define PADS_BANK0_GPIO28_OFFSET _u(0x00000074) 2243 #define PADS_BANK0_GPIO28_BITS _u(0x000001ff) 2244 #define PADS_BANK0_GPIO28_RESET _u(0x00000116) 2245 // ----------------------------------------------------------------------------- 2246 // Field : PADS_BANK0_GPIO28_ISO 2247 // Description : Pad isolation control. Remove this once the pad is configured 2248 // by software. 2249 #define PADS_BANK0_GPIO28_ISO_RESET _u(0x1) 2250 #define PADS_BANK0_GPIO28_ISO_BITS _u(0x00000100) 2251 #define PADS_BANK0_GPIO28_ISO_MSB _u(8) 2252 #define PADS_BANK0_GPIO28_ISO_LSB _u(8) 2253 #define PADS_BANK0_GPIO28_ISO_ACCESS "RW" 2254 // ----------------------------------------------------------------------------- 2255 // Field : PADS_BANK0_GPIO28_OD 2256 // Description : Output disable. Has priority over output enable from 2257 // peripherals 2258 #define PADS_BANK0_GPIO28_OD_RESET _u(0x0) 2259 #define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080) 2260 #define PADS_BANK0_GPIO28_OD_MSB _u(7) 2261 #define PADS_BANK0_GPIO28_OD_LSB _u(7) 2262 #define PADS_BANK0_GPIO28_OD_ACCESS "RW" 2263 // ----------------------------------------------------------------------------- 2264 // Field : PADS_BANK0_GPIO28_IE 2265 // Description : Input enable 2266 #define PADS_BANK0_GPIO28_IE_RESET _u(0x0) 2267 #define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040) 2268 #define PADS_BANK0_GPIO28_IE_MSB _u(6) 2269 #define PADS_BANK0_GPIO28_IE_LSB _u(6) 2270 #define PADS_BANK0_GPIO28_IE_ACCESS "RW" 2271 // ----------------------------------------------------------------------------- 2272 // Field : PADS_BANK0_GPIO28_DRIVE 2273 // Description : Drive strength. 2274 // 0x0 -> 2mA 2275 // 0x1 -> 4mA 2276 // 0x2 -> 8mA 2277 // 0x3 -> 12mA 2278 #define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1) 2279 #define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030) 2280 #define PADS_BANK0_GPIO28_DRIVE_MSB _u(5) 2281 #define PADS_BANK0_GPIO28_DRIVE_LSB _u(4) 2282 #define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW" 2283 #define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0) 2284 #define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1) 2285 #define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2) 2286 #define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3) 2287 // ----------------------------------------------------------------------------- 2288 // Field : PADS_BANK0_GPIO28_PUE 2289 // Description : Pull up enable 2290 #define PADS_BANK0_GPIO28_PUE_RESET _u(0x0) 2291 #define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008) 2292 #define PADS_BANK0_GPIO28_PUE_MSB _u(3) 2293 #define PADS_BANK0_GPIO28_PUE_LSB _u(3) 2294 #define PADS_BANK0_GPIO28_PUE_ACCESS "RW" 2295 // ----------------------------------------------------------------------------- 2296 // Field : PADS_BANK0_GPIO28_PDE 2297 // Description : Pull down enable 2298 #define PADS_BANK0_GPIO28_PDE_RESET _u(0x1) 2299 #define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004) 2300 #define PADS_BANK0_GPIO28_PDE_MSB _u(2) 2301 #define PADS_BANK0_GPIO28_PDE_LSB _u(2) 2302 #define PADS_BANK0_GPIO28_PDE_ACCESS "RW" 2303 // ----------------------------------------------------------------------------- 2304 // Field : PADS_BANK0_GPIO28_SCHMITT 2305 // Description : Enable schmitt trigger 2306 #define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1) 2307 #define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002) 2308 #define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1) 2309 #define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1) 2310 #define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW" 2311 // ----------------------------------------------------------------------------- 2312 // Field : PADS_BANK0_GPIO28_SLEWFAST 2313 // Description : Slew rate control. 1 = Fast, 0 = Slow 2314 #define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0) 2315 #define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001) 2316 #define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0) 2317 #define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0) 2318 #define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW" 2319 // ============================================================================= 2320 // Register : PADS_BANK0_GPIO29 2321 #define PADS_BANK0_GPIO29_OFFSET _u(0x00000078) 2322 #define PADS_BANK0_GPIO29_BITS _u(0x000001ff) 2323 #define PADS_BANK0_GPIO29_RESET _u(0x00000116) 2324 // ----------------------------------------------------------------------------- 2325 // Field : PADS_BANK0_GPIO29_ISO 2326 // Description : Pad isolation control. Remove this once the pad is configured 2327 // by software. 2328 #define PADS_BANK0_GPIO29_ISO_RESET _u(0x1) 2329 #define PADS_BANK0_GPIO29_ISO_BITS _u(0x00000100) 2330 #define PADS_BANK0_GPIO29_ISO_MSB _u(8) 2331 #define PADS_BANK0_GPIO29_ISO_LSB _u(8) 2332 #define PADS_BANK0_GPIO29_ISO_ACCESS "RW" 2333 // ----------------------------------------------------------------------------- 2334 // Field : PADS_BANK0_GPIO29_OD 2335 // Description : Output disable. Has priority over output enable from 2336 // peripherals 2337 #define PADS_BANK0_GPIO29_OD_RESET _u(0x0) 2338 #define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080) 2339 #define PADS_BANK0_GPIO29_OD_MSB _u(7) 2340 #define PADS_BANK0_GPIO29_OD_LSB _u(7) 2341 #define PADS_BANK0_GPIO29_OD_ACCESS "RW" 2342 // ----------------------------------------------------------------------------- 2343 // Field : PADS_BANK0_GPIO29_IE 2344 // Description : Input enable 2345 #define PADS_BANK0_GPIO29_IE_RESET _u(0x0) 2346 #define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040) 2347 #define PADS_BANK0_GPIO29_IE_MSB _u(6) 2348 #define PADS_BANK0_GPIO29_IE_LSB _u(6) 2349 #define PADS_BANK0_GPIO29_IE_ACCESS "RW" 2350 // ----------------------------------------------------------------------------- 2351 // Field : PADS_BANK0_GPIO29_DRIVE 2352 // Description : Drive strength. 2353 // 0x0 -> 2mA 2354 // 0x1 -> 4mA 2355 // 0x2 -> 8mA 2356 // 0x3 -> 12mA 2357 #define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1) 2358 #define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030) 2359 #define PADS_BANK0_GPIO29_DRIVE_MSB _u(5) 2360 #define PADS_BANK0_GPIO29_DRIVE_LSB _u(4) 2361 #define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW" 2362 #define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0) 2363 #define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1) 2364 #define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2) 2365 #define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3) 2366 // ----------------------------------------------------------------------------- 2367 // Field : PADS_BANK0_GPIO29_PUE 2368 // Description : Pull up enable 2369 #define PADS_BANK0_GPIO29_PUE_RESET _u(0x0) 2370 #define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008) 2371 #define PADS_BANK0_GPIO29_PUE_MSB _u(3) 2372 #define PADS_BANK0_GPIO29_PUE_LSB _u(3) 2373 #define PADS_BANK0_GPIO29_PUE_ACCESS "RW" 2374 // ----------------------------------------------------------------------------- 2375 // Field : PADS_BANK0_GPIO29_PDE 2376 // Description : Pull down enable 2377 #define PADS_BANK0_GPIO29_PDE_RESET _u(0x1) 2378 #define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004) 2379 #define PADS_BANK0_GPIO29_PDE_MSB _u(2) 2380 #define PADS_BANK0_GPIO29_PDE_LSB _u(2) 2381 #define PADS_BANK0_GPIO29_PDE_ACCESS "RW" 2382 // ----------------------------------------------------------------------------- 2383 // Field : PADS_BANK0_GPIO29_SCHMITT 2384 // Description : Enable schmitt trigger 2385 #define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1) 2386 #define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002) 2387 #define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1) 2388 #define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1) 2389 #define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW" 2390 // ----------------------------------------------------------------------------- 2391 // Field : PADS_BANK0_GPIO29_SLEWFAST 2392 // Description : Slew rate control. 1 = Fast, 0 = Slow 2393 #define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0) 2394 #define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001) 2395 #define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0) 2396 #define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0) 2397 #define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW" 2398 // ============================================================================= 2399 // Register : PADS_BANK0_GPIO30 2400 #define PADS_BANK0_GPIO30_OFFSET _u(0x0000007c) 2401 #define PADS_BANK0_GPIO30_BITS _u(0x000001ff) 2402 #define PADS_BANK0_GPIO30_RESET _u(0x00000116) 2403 // ----------------------------------------------------------------------------- 2404 // Field : PADS_BANK0_GPIO30_ISO 2405 // Description : Pad isolation control. Remove this once the pad is configured 2406 // by software. 2407 #define PADS_BANK0_GPIO30_ISO_RESET _u(0x1) 2408 #define PADS_BANK0_GPIO30_ISO_BITS _u(0x00000100) 2409 #define PADS_BANK0_GPIO30_ISO_MSB _u(8) 2410 #define PADS_BANK0_GPIO30_ISO_LSB _u(8) 2411 #define PADS_BANK0_GPIO30_ISO_ACCESS "RW" 2412 // ----------------------------------------------------------------------------- 2413 // Field : PADS_BANK0_GPIO30_OD 2414 // Description : Output disable. Has priority over output enable from 2415 // peripherals 2416 #define PADS_BANK0_GPIO30_OD_RESET _u(0x0) 2417 #define PADS_BANK0_GPIO30_OD_BITS _u(0x00000080) 2418 #define PADS_BANK0_GPIO30_OD_MSB _u(7) 2419 #define PADS_BANK0_GPIO30_OD_LSB _u(7) 2420 #define PADS_BANK0_GPIO30_OD_ACCESS "RW" 2421 // ----------------------------------------------------------------------------- 2422 // Field : PADS_BANK0_GPIO30_IE 2423 // Description : Input enable 2424 #define PADS_BANK0_GPIO30_IE_RESET _u(0x0) 2425 #define PADS_BANK0_GPIO30_IE_BITS _u(0x00000040) 2426 #define PADS_BANK0_GPIO30_IE_MSB _u(6) 2427 #define PADS_BANK0_GPIO30_IE_LSB _u(6) 2428 #define PADS_BANK0_GPIO30_IE_ACCESS "RW" 2429 // ----------------------------------------------------------------------------- 2430 // Field : PADS_BANK0_GPIO30_DRIVE 2431 // Description : Drive strength. 2432 // 0x0 -> 2mA 2433 // 0x1 -> 4mA 2434 // 0x2 -> 8mA 2435 // 0x3 -> 12mA 2436 #define PADS_BANK0_GPIO30_DRIVE_RESET _u(0x1) 2437 #define PADS_BANK0_GPIO30_DRIVE_BITS _u(0x00000030) 2438 #define PADS_BANK0_GPIO30_DRIVE_MSB _u(5) 2439 #define PADS_BANK0_GPIO30_DRIVE_LSB _u(4) 2440 #define PADS_BANK0_GPIO30_DRIVE_ACCESS "RW" 2441 #define PADS_BANK0_GPIO30_DRIVE_VALUE_2MA _u(0x0) 2442 #define PADS_BANK0_GPIO30_DRIVE_VALUE_4MA _u(0x1) 2443 #define PADS_BANK0_GPIO30_DRIVE_VALUE_8MA _u(0x2) 2444 #define PADS_BANK0_GPIO30_DRIVE_VALUE_12MA _u(0x3) 2445 // ----------------------------------------------------------------------------- 2446 // Field : PADS_BANK0_GPIO30_PUE 2447 // Description : Pull up enable 2448 #define PADS_BANK0_GPIO30_PUE_RESET _u(0x0) 2449 #define PADS_BANK0_GPIO30_PUE_BITS _u(0x00000008) 2450 #define PADS_BANK0_GPIO30_PUE_MSB _u(3) 2451 #define PADS_BANK0_GPIO30_PUE_LSB _u(3) 2452 #define PADS_BANK0_GPIO30_PUE_ACCESS "RW" 2453 // ----------------------------------------------------------------------------- 2454 // Field : PADS_BANK0_GPIO30_PDE 2455 // Description : Pull down enable 2456 #define PADS_BANK0_GPIO30_PDE_RESET _u(0x1) 2457 #define PADS_BANK0_GPIO30_PDE_BITS _u(0x00000004) 2458 #define PADS_BANK0_GPIO30_PDE_MSB _u(2) 2459 #define PADS_BANK0_GPIO30_PDE_LSB _u(2) 2460 #define PADS_BANK0_GPIO30_PDE_ACCESS "RW" 2461 // ----------------------------------------------------------------------------- 2462 // Field : PADS_BANK0_GPIO30_SCHMITT 2463 // Description : Enable schmitt trigger 2464 #define PADS_BANK0_GPIO30_SCHMITT_RESET _u(0x1) 2465 #define PADS_BANK0_GPIO30_SCHMITT_BITS _u(0x00000002) 2466 #define PADS_BANK0_GPIO30_SCHMITT_MSB _u(1) 2467 #define PADS_BANK0_GPIO30_SCHMITT_LSB _u(1) 2468 #define PADS_BANK0_GPIO30_SCHMITT_ACCESS "RW" 2469 // ----------------------------------------------------------------------------- 2470 // Field : PADS_BANK0_GPIO30_SLEWFAST 2471 // Description : Slew rate control. 1 = Fast, 0 = Slow 2472 #define PADS_BANK0_GPIO30_SLEWFAST_RESET _u(0x0) 2473 #define PADS_BANK0_GPIO30_SLEWFAST_BITS _u(0x00000001) 2474 #define PADS_BANK0_GPIO30_SLEWFAST_MSB _u(0) 2475 #define PADS_BANK0_GPIO30_SLEWFAST_LSB _u(0) 2476 #define PADS_BANK0_GPIO30_SLEWFAST_ACCESS "RW" 2477 // ============================================================================= 2478 // Register : PADS_BANK0_GPIO31 2479 #define PADS_BANK0_GPIO31_OFFSET _u(0x00000080) 2480 #define PADS_BANK0_GPIO31_BITS _u(0x000001ff) 2481 #define PADS_BANK0_GPIO31_RESET _u(0x00000116) 2482 // ----------------------------------------------------------------------------- 2483 // Field : PADS_BANK0_GPIO31_ISO 2484 // Description : Pad isolation control. Remove this once the pad is configured 2485 // by software. 2486 #define PADS_BANK0_GPIO31_ISO_RESET _u(0x1) 2487 #define PADS_BANK0_GPIO31_ISO_BITS _u(0x00000100) 2488 #define PADS_BANK0_GPIO31_ISO_MSB _u(8) 2489 #define PADS_BANK0_GPIO31_ISO_LSB _u(8) 2490 #define PADS_BANK0_GPIO31_ISO_ACCESS "RW" 2491 // ----------------------------------------------------------------------------- 2492 // Field : PADS_BANK0_GPIO31_OD 2493 // Description : Output disable. Has priority over output enable from 2494 // peripherals 2495 #define PADS_BANK0_GPIO31_OD_RESET _u(0x0) 2496 #define PADS_BANK0_GPIO31_OD_BITS _u(0x00000080) 2497 #define PADS_BANK0_GPIO31_OD_MSB _u(7) 2498 #define PADS_BANK0_GPIO31_OD_LSB _u(7) 2499 #define PADS_BANK0_GPIO31_OD_ACCESS "RW" 2500 // ----------------------------------------------------------------------------- 2501 // Field : PADS_BANK0_GPIO31_IE 2502 // Description : Input enable 2503 #define PADS_BANK0_GPIO31_IE_RESET _u(0x0) 2504 #define PADS_BANK0_GPIO31_IE_BITS _u(0x00000040) 2505 #define PADS_BANK0_GPIO31_IE_MSB _u(6) 2506 #define PADS_BANK0_GPIO31_IE_LSB _u(6) 2507 #define PADS_BANK0_GPIO31_IE_ACCESS "RW" 2508 // ----------------------------------------------------------------------------- 2509 // Field : PADS_BANK0_GPIO31_DRIVE 2510 // Description : Drive strength. 2511 // 0x0 -> 2mA 2512 // 0x1 -> 4mA 2513 // 0x2 -> 8mA 2514 // 0x3 -> 12mA 2515 #define PADS_BANK0_GPIO31_DRIVE_RESET _u(0x1) 2516 #define PADS_BANK0_GPIO31_DRIVE_BITS _u(0x00000030) 2517 #define PADS_BANK0_GPIO31_DRIVE_MSB _u(5) 2518 #define PADS_BANK0_GPIO31_DRIVE_LSB _u(4) 2519 #define PADS_BANK0_GPIO31_DRIVE_ACCESS "RW" 2520 #define PADS_BANK0_GPIO31_DRIVE_VALUE_2MA _u(0x0) 2521 #define PADS_BANK0_GPIO31_DRIVE_VALUE_4MA _u(0x1) 2522 #define PADS_BANK0_GPIO31_DRIVE_VALUE_8MA _u(0x2) 2523 #define PADS_BANK0_GPIO31_DRIVE_VALUE_12MA _u(0x3) 2524 // ----------------------------------------------------------------------------- 2525 // Field : PADS_BANK0_GPIO31_PUE 2526 // Description : Pull up enable 2527 #define PADS_BANK0_GPIO31_PUE_RESET _u(0x0) 2528 #define PADS_BANK0_GPIO31_PUE_BITS _u(0x00000008) 2529 #define PADS_BANK0_GPIO31_PUE_MSB _u(3) 2530 #define PADS_BANK0_GPIO31_PUE_LSB _u(3) 2531 #define PADS_BANK0_GPIO31_PUE_ACCESS "RW" 2532 // ----------------------------------------------------------------------------- 2533 // Field : PADS_BANK0_GPIO31_PDE 2534 // Description : Pull down enable 2535 #define PADS_BANK0_GPIO31_PDE_RESET _u(0x1) 2536 #define PADS_BANK0_GPIO31_PDE_BITS _u(0x00000004) 2537 #define PADS_BANK0_GPIO31_PDE_MSB _u(2) 2538 #define PADS_BANK0_GPIO31_PDE_LSB _u(2) 2539 #define PADS_BANK0_GPIO31_PDE_ACCESS "RW" 2540 // ----------------------------------------------------------------------------- 2541 // Field : PADS_BANK0_GPIO31_SCHMITT 2542 // Description : Enable schmitt trigger 2543 #define PADS_BANK0_GPIO31_SCHMITT_RESET _u(0x1) 2544 #define PADS_BANK0_GPIO31_SCHMITT_BITS _u(0x00000002) 2545 #define PADS_BANK0_GPIO31_SCHMITT_MSB _u(1) 2546 #define PADS_BANK0_GPIO31_SCHMITT_LSB _u(1) 2547 #define PADS_BANK0_GPIO31_SCHMITT_ACCESS "RW" 2548 // ----------------------------------------------------------------------------- 2549 // Field : PADS_BANK0_GPIO31_SLEWFAST 2550 // Description : Slew rate control. 1 = Fast, 0 = Slow 2551 #define PADS_BANK0_GPIO31_SLEWFAST_RESET _u(0x0) 2552 #define PADS_BANK0_GPIO31_SLEWFAST_BITS _u(0x00000001) 2553 #define PADS_BANK0_GPIO31_SLEWFAST_MSB _u(0) 2554 #define PADS_BANK0_GPIO31_SLEWFAST_LSB _u(0) 2555 #define PADS_BANK0_GPIO31_SLEWFAST_ACCESS "RW" 2556 // ============================================================================= 2557 // Register : PADS_BANK0_GPIO32 2558 #define PADS_BANK0_GPIO32_OFFSET _u(0x00000084) 2559 #define PADS_BANK0_GPIO32_BITS _u(0x000001ff) 2560 #define PADS_BANK0_GPIO32_RESET _u(0x00000116) 2561 // ----------------------------------------------------------------------------- 2562 // Field : PADS_BANK0_GPIO32_ISO 2563 // Description : Pad isolation control. Remove this once the pad is configured 2564 // by software. 2565 #define PADS_BANK0_GPIO32_ISO_RESET _u(0x1) 2566 #define PADS_BANK0_GPIO32_ISO_BITS _u(0x00000100) 2567 #define PADS_BANK0_GPIO32_ISO_MSB _u(8) 2568 #define PADS_BANK0_GPIO32_ISO_LSB _u(8) 2569 #define PADS_BANK0_GPIO32_ISO_ACCESS "RW" 2570 // ----------------------------------------------------------------------------- 2571 // Field : PADS_BANK0_GPIO32_OD 2572 // Description : Output disable. Has priority over output enable from 2573 // peripherals 2574 #define PADS_BANK0_GPIO32_OD_RESET _u(0x0) 2575 #define PADS_BANK0_GPIO32_OD_BITS _u(0x00000080) 2576 #define PADS_BANK0_GPIO32_OD_MSB _u(7) 2577 #define PADS_BANK0_GPIO32_OD_LSB _u(7) 2578 #define PADS_BANK0_GPIO32_OD_ACCESS "RW" 2579 // ----------------------------------------------------------------------------- 2580 // Field : PADS_BANK0_GPIO32_IE 2581 // Description : Input enable 2582 #define PADS_BANK0_GPIO32_IE_RESET _u(0x0) 2583 #define PADS_BANK0_GPIO32_IE_BITS _u(0x00000040) 2584 #define PADS_BANK0_GPIO32_IE_MSB _u(6) 2585 #define PADS_BANK0_GPIO32_IE_LSB _u(6) 2586 #define PADS_BANK0_GPIO32_IE_ACCESS "RW" 2587 // ----------------------------------------------------------------------------- 2588 // Field : PADS_BANK0_GPIO32_DRIVE 2589 // Description : Drive strength. 2590 // 0x0 -> 2mA 2591 // 0x1 -> 4mA 2592 // 0x2 -> 8mA 2593 // 0x3 -> 12mA 2594 #define PADS_BANK0_GPIO32_DRIVE_RESET _u(0x1) 2595 #define PADS_BANK0_GPIO32_DRIVE_BITS _u(0x00000030) 2596 #define PADS_BANK0_GPIO32_DRIVE_MSB _u(5) 2597 #define PADS_BANK0_GPIO32_DRIVE_LSB _u(4) 2598 #define PADS_BANK0_GPIO32_DRIVE_ACCESS "RW" 2599 #define PADS_BANK0_GPIO32_DRIVE_VALUE_2MA _u(0x0) 2600 #define PADS_BANK0_GPIO32_DRIVE_VALUE_4MA _u(0x1) 2601 #define PADS_BANK0_GPIO32_DRIVE_VALUE_8MA _u(0x2) 2602 #define PADS_BANK0_GPIO32_DRIVE_VALUE_12MA _u(0x3) 2603 // ----------------------------------------------------------------------------- 2604 // Field : PADS_BANK0_GPIO32_PUE 2605 // Description : Pull up enable 2606 #define PADS_BANK0_GPIO32_PUE_RESET _u(0x0) 2607 #define PADS_BANK0_GPIO32_PUE_BITS _u(0x00000008) 2608 #define PADS_BANK0_GPIO32_PUE_MSB _u(3) 2609 #define PADS_BANK0_GPIO32_PUE_LSB _u(3) 2610 #define PADS_BANK0_GPIO32_PUE_ACCESS "RW" 2611 // ----------------------------------------------------------------------------- 2612 // Field : PADS_BANK0_GPIO32_PDE 2613 // Description : Pull down enable 2614 #define PADS_BANK0_GPIO32_PDE_RESET _u(0x1) 2615 #define PADS_BANK0_GPIO32_PDE_BITS _u(0x00000004) 2616 #define PADS_BANK0_GPIO32_PDE_MSB _u(2) 2617 #define PADS_BANK0_GPIO32_PDE_LSB _u(2) 2618 #define PADS_BANK0_GPIO32_PDE_ACCESS "RW" 2619 // ----------------------------------------------------------------------------- 2620 // Field : PADS_BANK0_GPIO32_SCHMITT 2621 // Description : Enable schmitt trigger 2622 #define PADS_BANK0_GPIO32_SCHMITT_RESET _u(0x1) 2623 #define PADS_BANK0_GPIO32_SCHMITT_BITS _u(0x00000002) 2624 #define PADS_BANK0_GPIO32_SCHMITT_MSB _u(1) 2625 #define PADS_BANK0_GPIO32_SCHMITT_LSB _u(1) 2626 #define PADS_BANK0_GPIO32_SCHMITT_ACCESS "RW" 2627 // ----------------------------------------------------------------------------- 2628 // Field : PADS_BANK0_GPIO32_SLEWFAST 2629 // Description : Slew rate control. 1 = Fast, 0 = Slow 2630 #define PADS_BANK0_GPIO32_SLEWFAST_RESET _u(0x0) 2631 #define PADS_BANK0_GPIO32_SLEWFAST_BITS _u(0x00000001) 2632 #define PADS_BANK0_GPIO32_SLEWFAST_MSB _u(0) 2633 #define PADS_BANK0_GPIO32_SLEWFAST_LSB _u(0) 2634 #define PADS_BANK0_GPIO32_SLEWFAST_ACCESS "RW" 2635 // ============================================================================= 2636 // Register : PADS_BANK0_GPIO33 2637 #define PADS_BANK0_GPIO33_OFFSET _u(0x00000088) 2638 #define PADS_BANK0_GPIO33_BITS _u(0x000001ff) 2639 #define PADS_BANK0_GPIO33_RESET _u(0x00000116) 2640 // ----------------------------------------------------------------------------- 2641 // Field : PADS_BANK0_GPIO33_ISO 2642 // Description : Pad isolation control. Remove this once the pad is configured 2643 // by software. 2644 #define PADS_BANK0_GPIO33_ISO_RESET _u(0x1) 2645 #define PADS_BANK0_GPIO33_ISO_BITS _u(0x00000100) 2646 #define PADS_BANK0_GPIO33_ISO_MSB _u(8) 2647 #define PADS_BANK0_GPIO33_ISO_LSB _u(8) 2648 #define PADS_BANK0_GPIO33_ISO_ACCESS "RW" 2649 // ----------------------------------------------------------------------------- 2650 // Field : PADS_BANK0_GPIO33_OD 2651 // Description : Output disable. Has priority over output enable from 2652 // peripherals 2653 #define PADS_BANK0_GPIO33_OD_RESET _u(0x0) 2654 #define PADS_BANK0_GPIO33_OD_BITS _u(0x00000080) 2655 #define PADS_BANK0_GPIO33_OD_MSB _u(7) 2656 #define PADS_BANK0_GPIO33_OD_LSB _u(7) 2657 #define PADS_BANK0_GPIO33_OD_ACCESS "RW" 2658 // ----------------------------------------------------------------------------- 2659 // Field : PADS_BANK0_GPIO33_IE 2660 // Description : Input enable 2661 #define PADS_BANK0_GPIO33_IE_RESET _u(0x0) 2662 #define PADS_BANK0_GPIO33_IE_BITS _u(0x00000040) 2663 #define PADS_BANK0_GPIO33_IE_MSB _u(6) 2664 #define PADS_BANK0_GPIO33_IE_LSB _u(6) 2665 #define PADS_BANK0_GPIO33_IE_ACCESS "RW" 2666 // ----------------------------------------------------------------------------- 2667 // Field : PADS_BANK0_GPIO33_DRIVE 2668 // Description : Drive strength. 2669 // 0x0 -> 2mA 2670 // 0x1 -> 4mA 2671 // 0x2 -> 8mA 2672 // 0x3 -> 12mA 2673 #define PADS_BANK0_GPIO33_DRIVE_RESET _u(0x1) 2674 #define PADS_BANK0_GPIO33_DRIVE_BITS _u(0x00000030) 2675 #define PADS_BANK0_GPIO33_DRIVE_MSB _u(5) 2676 #define PADS_BANK0_GPIO33_DRIVE_LSB _u(4) 2677 #define PADS_BANK0_GPIO33_DRIVE_ACCESS "RW" 2678 #define PADS_BANK0_GPIO33_DRIVE_VALUE_2MA _u(0x0) 2679 #define PADS_BANK0_GPIO33_DRIVE_VALUE_4MA _u(0x1) 2680 #define PADS_BANK0_GPIO33_DRIVE_VALUE_8MA _u(0x2) 2681 #define PADS_BANK0_GPIO33_DRIVE_VALUE_12MA _u(0x3) 2682 // ----------------------------------------------------------------------------- 2683 // Field : PADS_BANK0_GPIO33_PUE 2684 // Description : Pull up enable 2685 #define PADS_BANK0_GPIO33_PUE_RESET _u(0x0) 2686 #define PADS_BANK0_GPIO33_PUE_BITS _u(0x00000008) 2687 #define PADS_BANK0_GPIO33_PUE_MSB _u(3) 2688 #define PADS_BANK0_GPIO33_PUE_LSB _u(3) 2689 #define PADS_BANK0_GPIO33_PUE_ACCESS "RW" 2690 // ----------------------------------------------------------------------------- 2691 // Field : PADS_BANK0_GPIO33_PDE 2692 // Description : Pull down enable 2693 #define PADS_BANK0_GPIO33_PDE_RESET _u(0x1) 2694 #define PADS_BANK0_GPIO33_PDE_BITS _u(0x00000004) 2695 #define PADS_BANK0_GPIO33_PDE_MSB _u(2) 2696 #define PADS_BANK0_GPIO33_PDE_LSB _u(2) 2697 #define PADS_BANK0_GPIO33_PDE_ACCESS "RW" 2698 // ----------------------------------------------------------------------------- 2699 // Field : PADS_BANK0_GPIO33_SCHMITT 2700 // Description : Enable schmitt trigger 2701 #define PADS_BANK0_GPIO33_SCHMITT_RESET _u(0x1) 2702 #define PADS_BANK0_GPIO33_SCHMITT_BITS _u(0x00000002) 2703 #define PADS_BANK0_GPIO33_SCHMITT_MSB _u(1) 2704 #define PADS_BANK0_GPIO33_SCHMITT_LSB _u(1) 2705 #define PADS_BANK0_GPIO33_SCHMITT_ACCESS "RW" 2706 // ----------------------------------------------------------------------------- 2707 // Field : PADS_BANK0_GPIO33_SLEWFAST 2708 // Description : Slew rate control. 1 = Fast, 0 = Slow 2709 #define PADS_BANK0_GPIO33_SLEWFAST_RESET _u(0x0) 2710 #define PADS_BANK0_GPIO33_SLEWFAST_BITS _u(0x00000001) 2711 #define PADS_BANK0_GPIO33_SLEWFAST_MSB _u(0) 2712 #define PADS_BANK0_GPIO33_SLEWFAST_LSB _u(0) 2713 #define PADS_BANK0_GPIO33_SLEWFAST_ACCESS "RW" 2714 // ============================================================================= 2715 // Register : PADS_BANK0_GPIO34 2716 #define PADS_BANK0_GPIO34_OFFSET _u(0x0000008c) 2717 #define PADS_BANK0_GPIO34_BITS _u(0x000001ff) 2718 #define PADS_BANK0_GPIO34_RESET _u(0x00000116) 2719 // ----------------------------------------------------------------------------- 2720 // Field : PADS_BANK0_GPIO34_ISO 2721 // Description : Pad isolation control. Remove this once the pad is configured 2722 // by software. 2723 #define PADS_BANK0_GPIO34_ISO_RESET _u(0x1) 2724 #define PADS_BANK0_GPIO34_ISO_BITS _u(0x00000100) 2725 #define PADS_BANK0_GPIO34_ISO_MSB _u(8) 2726 #define PADS_BANK0_GPIO34_ISO_LSB _u(8) 2727 #define PADS_BANK0_GPIO34_ISO_ACCESS "RW" 2728 // ----------------------------------------------------------------------------- 2729 // Field : PADS_BANK0_GPIO34_OD 2730 // Description : Output disable. Has priority over output enable from 2731 // peripherals 2732 #define PADS_BANK0_GPIO34_OD_RESET _u(0x0) 2733 #define PADS_BANK0_GPIO34_OD_BITS _u(0x00000080) 2734 #define PADS_BANK0_GPIO34_OD_MSB _u(7) 2735 #define PADS_BANK0_GPIO34_OD_LSB _u(7) 2736 #define PADS_BANK0_GPIO34_OD_ACCESS "RW" 2737 // ----------------------------------------------------------------------------- 2738 // Field : PADS_BANK0_GPIO34_IE 2739 // Description : Input enable 2740 #define PADS_BANK0_GPIO34_IE_RESET _u(0x0) 2741 #define PADS_BANK0_GPIO34_IE_BITS _u(0x00000040) 2742 #define PADS_BANK0_GPIO34_IE_MSB _u(6) 2743 #define PADS_BANK0_GPIO34_IE_LSB _u(6) 2744 #define PADS_BANK0_GPIO34_IE_ACCESS "RW" 2745 // ----------------------------------------------------------------------------- 2746 // Field : PADS_BANK0_GPIO34_DRIVE 2747 // Description : Drive strength. 2748 // 0x0 -> 2mA 2749 // 0x1 -> 4mA 2750 // 0x2 -> 8mA 2751 // 0x3 -> 12mA 2752 #define PADS_BANK0_GPIO34_DRIVE_RESET _u(0x1) 2753 #define PADS_BANK0_GPIO34_DRIVE_BITS _u(0x00000030) 2754 #define PADS_BANK0_GPIO34_DRIVE_MSB _u(5) 2755 #define PADS_BANK0_GPIO34_DRIVE_LSB _u(4) 2756 #define PADS_BANK0_GPIO34_DRIVE_ACCESS "RW" 2757 #define PADS_BANK0_GPIO34_DRIVE_VALUE_2MA _u(0x0) 2758 #define PADS_BANK0_GPIO34_DRIVE_VALUE_4MA _u(0x1) 2759 #define PADS_BANK0_GPIO34_DRIVE_VALUE_8MA _u(0x2) 2760 #define PADS_BANK0_GPIO34_DRIVE_VALUE_12MA _u(0x3) 2761 // ----------------------------------------------------------------------------- 2762 // Field : PADS_BANK0_GPIO34_PUE 2763 // Description : Pull up enable 2764 #define PADS_BANK0_GPIO34_PUE_RESET _u(0x0) 2765 #define PADS_BANK0_GPIO34_PUE_BITS _u(0x00000008) 2766 #define PADS_BANK0_GPIO34_PUE_MSB _u(3) 2767 #define PADS_BANK0_GPIO34_PUE_LSB _u(3) 2768 #define PADS_BANK0_GPIO34_PUE_ACCESS "RW" 2769 // ----------------------------------------------------------------------------- 2770 // Field : PADS_BANK0_GPIO34_PDE 2771 // Description : Pull down enable 2772 #define PADS_BANK0_GPIO34_PDE_RESET _u(0x1) 2773 #define PADS_BANK0_GPIO34_PDE_BITS _u(0x00000004) 2774 #define PADS_BANK0_GPIO34_PDE_MSB _u(2) 2775 #define PADS_BANK0_GPIO34_PDE_LSB _u(2) 2776 #define PADS_BANK0_GPIO34_PDE_ACCESS "RW" 2777 // ----------------------------------------------------------------------------- 2778 // Field : PADS_BANK0_GPIO34_SCHMITT 2779 // Description : Enable schmitt trigger 2780 #define PADS_BANK0_GPIO34_SCHMITT_RESET _u(0x1) 2781 #define PADS_BANK0_GPIO34_SCHMITT_BITS _u(0x00000002) 2782 #define PADS_BANK0_GPIO34_SCHMITT_MSB _u(1) 2783 #define PADS_BANK0_GPIO34_SCHMITT_LSB _u(1) 2784 #define PADS_BANK0_GPIO34_SCHMITT_ACCESS "RW" 2785 // ----------------------------------------------------------------------------- 2786 // Field : PADS_BANK0_GPIO34_SLEWFAST 2787 // Description : Slew rate control. 1 = Fast, 0 = Slow 2788 #define PADS_BANK0_GPIO34_SLEWFAST_RESET _u(0x0) 2789 #define PADS_BANK0_GPIO34_SLEWFAST_BITS _u(0x00000001) 2790 #define PADS_BANK0_GPIO34_SLEWFAST_MSB _u(0) 2791 #define PADS_BANK0_GPIO34_SLEWFAST_LSB _u(0) 2792 #define PADS_BANK0_GPIO34_SLEWFAST_ACCESS "RW" 2793 // ============================================================================= 2794 // Register : PADS_BANK0_GPIO35 2795 #define PADS_BANK0_GPIO35_OFFSET _u(0x00000090) 2796 #define PADS_BANK0_GPIO35_BITS _u(0x000001ff) 2797 #define PADS_BANK0_GPIO35_RESET _u(0x00000116) 2798 // ----------------------------------------------------------------------------- 2799 // Field : PADS_BANK0_GPIO35_ISO 2800 // Description : Pad isolation control. Remove this once the pad is configured 2801 // by software. 2802 #define PADS_BANK0_GPIO35_ISO_RESET _u(0x1) 2803 #define PADS_BANK0_GPIO35_ISO_BITS _u(0x00000100) 2804 #define PADS_BANK0_GPIO35_ISO_MSB _u(8) 2805 #define PADS_BANK0_GPIO35_ISO_LSB _u(8) 2806 #define PADS_BANK0_GPIO35_ISO_ACCESS "RW" 2807 // ----------------------------------------------------------------------------- 2808 // Field : PADS_BANK0_GPIO35_OD 2809 // Description : Output disable. Has priority over output enable from 2810 // peripherals 2811 #define PADS_BANK0_GPIO35_OD_RESET _u(0x0) 2812 #define PADS_BANK0_GPIO35_OD_BITS _u(0x00000080) 2813 #define PADS_BANK0_GPIO35_OD_MSB _u(7) 2814 #define PADS_BANK0_GPIO35_OD_LSB _u(7) 2815 #define PADS_BANK0_GPIO35_OD_ACCESS "RW" 2816 // ----------------------------------------------------------------------------- 2817 // Field : PADS_BANK0_GPIO35_IE 2818 // Description : Input enable 2819 #define PADS_BANK0_GPIO35_IE_RESET _u(0x0) 2820 #define PADS_BANK0_GPIO35_IE_BITS _u(0x00000040) 2821 #define PADS_BANK0_GPIO35_IE_MSB _u(6) 2822 #define PADS_BANK0_GPIO35_IE_LSB _u(6) 2823 #define PADS_BANK0_GPIO35_IE_ACCESS "RW" 2824 // ----------------------------------------------------------------------------- 2825 // Field : PADS_BANK0_GPIO35_DRIVE 2826 // Description : Drive strength. 2827 // 0x0 -> 2mA 2828 // 0x1 -> 4mA 2829 // 0x2 -> 8mA 2830 // 0x3 -> 12mA 2831 #define PADS_BANK0_GPIO35_DRIVE_RESET _u(0x1) 2832 #define PADS_BANK0_GPIO35_DRIVE_BITS _u(0x00000030) 2833 #define PADS_BANK0_GPIO35_DRIVE_MSB _u(5) 2834 #define PADS_BANK0_GPIO35_DRIVE_LSB _u(4) 2835 #define PADS_BANK0_GPIO35_DRIVE_ACCESS "RW" 2836 #define PADS_BANK0_GPIO35_DRIVE_VALUE_2MA _u(0x0) 2837 #define PADS_BANK0_GPIO35_DRIVE_VALUE_4MA _u(0x1) 2838 #define PADS_BANK0_GPIO35_DRIVE_VALUE_8MA _u(0x2) 2839 #define PADS_BANK0_GPIO35_DRIVE_VALUE_12MA _u(0x3) 2840 // ----------------------------------------------------------------------------- 2841 // Field : PADS_BANK0_GPIO35_PUE 2842 // Description : Pull up enable 2843 #define PADS_BANK0_GPIO35_PUE_RESET _u(0x0) 2844 #define PADS_BANK0_GPIO35_PUE_BITS _u(0x00000008) 2845 #define PADS_BANK0_GPIO35_PUE_MSB _u(3) 2846 #define PADS_BANK0_GPIO35_PUE_LSB _u(3) 2847 #define PADS_BANK0_GPIO35_PUE_ACCESS "RW" 2848 // ----------------------------------------------------------------------------- 2849 // Field : PADS_BANK0_GPIO35_PDE 2850 // Description : Pull down enable 2851 #define PADS_BANK0_GPIO35_PDE_RESET _u(0x1) 2852 #define PADS_BANK0_GPIO35_PDE_BITS _u(0x00000004) 2853 #define PADS_BANK0_GPIO35_PDE_MSB _u(2) 2854 #define PADS_BANK0_GPIO35_PDE_LSB _u(2) 2855 #define PADS_BANK0_GPIO35_PDE_ACCESS "RW" 2856 // ----------------------------------------------------------------------------- 2857 // Field : PADS_BANK0_GPIO35_SCHMITT 2858 // Description : Enable schmitt trigger 2859 #define PADS_BANK0_GPIO35_SCHMITT_RESET _u(0x1) 2860 #define PADS_BANK0_GPIO35_SCHMITT_BITS _u(0x00000002) 2861 #define PADS_BANK0_GPIO35_SCHMITT_MSB _u(1) 2862 #define PADS_BANK0_GPIO35_SCHMITT_LSB _u(1) 2863 #define PADS_BANK0_GPIO35_SCHMITT_ACCESS "RW" 2864 // ----------------------------------------------------------------------------- 2865 // Field : PADS_BANK0_GPIO35_SLEWFAST 2866 // Description : Slew rate control. 1 = Fast, 0 = Slow 2867 #define PADS_BANK0_GPIO35_SLEWFAST_RESET _u(0x0) 2868 #define PADS_BANK0_GPIO35_SLEWFAST_BITS _u(0x00000001) 2869 #define PADS_BANK0_GPIO35_SLEWFAST_MSB _u(0) 2870 #define PADS_BANK0_GPIO35_SLEWFAST_LSB _u(0) 2871 #define PADS_BANK0_GPIO35_SLEWFAST_ACCESS "RW" 2872 // ============================================================================= 2873 // Register : PADS_BANK0_GPIO36 2874 #define PADS_BANK0_GPIO36_OFFSET _u(0x00000094) 2875 #define PADS_BANK0_GPIO36_BITS _u(0x000001ff) 2876 #define PADS_BANK0_GPIO36_RESET _u(0x00000116) 2877 // ----------------------------------------------------------------------------- 2878 // Field : PADS_BANK0_GPIO36_ISO 2879 // Description : Pad isolation control. Remove this once the pad is configured 2880 // by software. 2881 #define PADS_BANK0_GPIO36_ISO_RESET _u(0x1) 2882 #define PADS_BANK0_GPIO36_ISO_BITS _u(0x00000100) 2883 #define PADS_BANK0_GPIO36_ISO_MSB _u(8) 2884 #define PADS_BANK0_GPIO36_ISO_LSB _u(8) 2885 #define PADS_BANK0_GPIO36_ISO_ACCESS "RW" 2886 // ----------------------------------------------------------------------------- 2887 // Field : PADS_BANK0_GPIO36_OD 2888 // Description : Output disable. Has priority over output enable from 2889 // peripherals 2890 #define PADS_BANK0_GPIO36_OD_RESET _u(0x0) 2891 #define PADS_BANK0_GPIO36_OD_BITS _u(0x00000080) 2892 #define PADS_BANK0_GPIO36_OD_MSB _u(7) 2893 #define PADS_BANK0_GPIO36_OD_LSB _u(7) 2894 #define PADS_BANK0_GPIO36_OD_ACCESS "RW" 2895 // ----------------------------------------------------------------------------- 2896 // Field : PADS_BANK0_GPIO36_IE 2897 // Description : Input enable 2898 #define PADS_BANK0_GPIO36_IE_RESET _u(0x0) 2899 #define PADS_BANK0_GPIO36_IE_BITS _u(0x00000040) 2900 #define PADS_BANK0_GPIO36_IE_MSB _u(6) 2901 #define PADS_BANK0_GPIO36_IE_LSB _u(6) 2902 #define PADS_BANK0_GPIO36_IE_ACCESS "RW" 2903 // ----------------------------------------------------------------------------- 2904 // Field : PADS_BANK0_GPIO36_DRIVE 2905 // Description : Drive strength. 2906 // 0x0 -> 2mA 2907 // 0x1 -> 4mA 2908 // 0x2 -> 8mA 2909 // 0x3 -> 12mA 2910 #define PADS_BANK0_GPIO36_DRIVE_RESET _u(0x1) 2911 #define PADS_BANK0_GPIO36_DRIVE_BITS _u(0x00000030) 2912 #define PADS_BANK0_GPIO36_DRIVE_MSB _u(5) 2913 #define PADS_BANK0_GPIO36_DRIVE_LSB _u(4) 2914 #define PADS_BANK0_GPIO36_DRIVE_ACCESS "RW" 2915 #define PADS_BANK0_GPIO36_DRIVE_VALUE_2MA _u(0x0) 2916 #define PADS_BANK0_GPIO36_DRIVE_VALUE_4MA _u(0x1) 2917 #define PADS_BANK0_GPIO36_DRIVE_VALUE_8MA _u(0x2) 2918 #define PADS_BANK0_GPIO36_DRIVE_VALUE_12MA _u(0x3) 2919 // ----------------------------------------------------------------------------- 2920 // Field : PADS_BANK0_GPIO36_PUE 2921 // Description : Pull up enable 2922 #define PADS_BANK0_GPIO36_PUE_RESET _u(0x0) 2923 #define PADS_BANK0_GPIO36_PUE_BITS _u(0x00000008) 2924 #define PADS_BANK0_GPIO36_PUE_MSB _u(3) 2925 #define PADS_BANK0_GPIO36_PUE_LSB _u(3) 2926 #define PADS_BANK0_GPIO36_PUE_ACCESS "RW" 2927 // ----------------------------------------------------------------------------- 2928 // Field : PADS_BANK0_GPIO36_PDE 2929 // Description : Pull down enable 2930 #define PADS_BANK0_GPIO36_PDE_RESET _u(0x1) 2931 #define PADS_BANK0_GPIO36_PDE_BITS _u(0x00000004) 2932 #define PADS_BANK0_GPIO36_PDE_MSB _u(2) 2933 #define PADS_BANK0_GPIO36_PDE_LSB _u(2) 2934 #define PADS_BANK0_GPIO36_PDE_ACCESS "RW" 2935 // ----------------------------------------------------------------------------- 2936 // Field : PADS_BANK0_GPIO36_SCHMITT 2937 // Description : Enable schmitt trigger 2938 #define PADS_BANK0_GPIO36_SCHMITT_RESET _u(0x1) 2939 #define PADS_BANK0_GPIO36_SCHMITT_BITS _u(0x00000002) 2940 #define PADS_BANK0_GPIO36_SCHMITT_MSB _u(1) 2941 #define PADS_BANK0_GPIO36_SCHMITT_LSB _u(1) 2942 #define PADS_BANK0_GPIO36_SCHMITT_ACCESS "RW" 2943 // ----------------------------------------------------------------------------- 2944 // Field : PADS_BANK0_GPIO36_SLEWFAST 2945 // Description : Slew rate control. 1 = Fast, 0 = Slow 2946 #define PADS_BANK0_GPIO36_SLEWFAST_RESET _u(0x0) 2947 #define PADS_BANK0_GPIO36_SLEWFAST_BITS _u(0x00000001) 2948 #define PADS_BANK0_GPIO36_SLEWFAST_MSB _u(0) 2949 #define PADS_BANK0_GPIO36_SLEWFAST_LSB _u(0) 2950 #define PADS_BANK0_GPIO36_SLEWFAST_ACCESS "RW" 2951 // ============================================================================= 2952 // Register : PADS_BANK0_GPIO37 2953 #define PADS_BANK0_GPIO37_OFFSET _u(0x00000098) 2954 #define PADS_BANK0_GPIO37_BITS _u(0x000001ff) 2955 #define PADS_BANK0_GPIO37_RESET _u(0x00000116) 2956 // ----------------------------------------------------------------------------- 2957 // Field : PADS_BANK0_GPIO37_ISO 2958 // Description : Pad isolation control. Remove this once the pad is configured 2959 // by software. 2960 #define PADS_BANK0_GPIO37_ISO_RESET _u(0x1) 2961 #define PADS_BANK0_GPIO37_ISO_BITS _u(0x00000100) 2962 #define PADS_BANK0_GPIO37_ISO_MSB _u(8) 2963 #define PADS_BANK0_GPIO37_ISO_LSB _u(8) 2964 #define PADS_BANK0_GPIO37_ISO_ACCESS "RW" 2965 // ----------------------------------------------------------------------------- 2966 // Field : PADS_BANK0_GPIO37_OD 2967 // Description : Output disable. Has priority over output enable from 2968 // peripherals 2969 #define PADS_BANK0_GPIO37_OD_RESET _u(0x0) 2970 #define PADS_BANK0_GPIO37_OD_BITS _u(0x00000080) 2971 #define PADS_BANK0_GPIO37_OD_MSB _u(7) 2972 #define PADS_BANK0_GPIO37_OD_LSB _u(7) 2973 #define PADS_BANK0_GPIO37_OD_ACCESS "RW" 2974 // ----------------------------------------------------------------------------- 2975 // Field : PADS_BANK0_GPIO37_IE 2976 // Description : Input enable 2977 #define PADS_BANK0_GPIO37_IE_RESET _u(0x0) 2978 #define PADS_BANK0_GPIO37_IE_BITS _u(0x00000040) 2979 #define PADS_BANK0_GPIO37_IE_MSB _u(6) 2980 #define PADS_BANK0_GPIO37_IE_LSB _u(6) 2981 #define PADS_BANK0_GPIO37_IE_ACCESS "RW" 2982 // ----------------------------------------------------------------------------- 2983 // Field : PADS_BANK0_GPIO37_DRIVE 2984 // Description : Drive strength. 2985 // 0x0 -> 2mA 2986 // 0x1 -> 4mA 2987 // 0x2 -> 8mA 2988 // 0x3 -> 12mA 2989 #define PADS_BANK0_GPIO37_DRIVE_RESET _u(0x1) 2990 #define PADS_BANK0_GPIO37_DRIVE_BITS _u(0x00000030) 2991 #define PADS_BANK0_GPIO37_DRIVE_MSB _u(5) 2992 #define PADS_BANK0_GPIO37_DRIVE_LSB _u(4) 2993 #define PADS_BANK0_GPIO37_DRIVE_ACCESS "RW" 2994 #define PADS_BANK0_GPIO37_DRIVE_VALUE_2MA _u(0x0) 2995 #define PADS_BANK0_GPIO37_DRIVE_VALUE_4MA _u(0x1) 2996 #define PADS_BANK0_GPIO37_DRIVE_VALUE_8MA _u(0x2) 2997 #define PADS_BANK0_GPIO37_DRIVE_VALUE_12MA _u(0x3) 2998 // ----------------------------------------------------------------------------- 2999 // Field : PADS_BANK0_GPIO37_PUE 3000 // Description : Pull up enable 3001 #define PADS_BANK0_GPIO37_PUE_RESET _u(0x0) 3002 #define PADS_BANK0_GPIO37_PUE_BITS _u(0x00000008) 3003 #define PADS_BANK0_GPIO37_PUE_MSB _u(3) 3004 #define PADS_BANK0_GPIO37_PUE_LSB _u(3) 3005 #define PADS_BANK0_GPIO37_PUE_ACCESS "RW" 3006 // ----------------------------------------------------------------------------- 3007 // Field : PADS_BANK0_GPIO37_PDE 3008 // Description : Pull down enable 3009 #define PADS_BANK0_GPIO37_PDE_RESET _u(0x1) 3010 #define PADS_BANK0_GPIO37_PDE_BITS _u(0x00000004) 3011 #define PADS_BANK0_GPIO37_PDE_MSB _u(2) 3012 #define PADS_BANK0_GPIO37_PDE_LSB _u(2) 3013 #define PADS_BANK0_GPIO37_PDE_ACCESS "RW" 3014 // ----------------------------------------------------------------------------- 3015 // Field : PADS_BANK0_GPIO37_SCHMITT 3016 // Description : Enable schmitt trigger 3017 #define PADS_BANK0_GPIO37_SCHMITT_RESET _u(0x1) 3018 #define PADS_BANK0_GPIO37_SCHMITT_BITS _u(0x00000002) 3019 #define PADS_BANK0_GPIO37_SCHMITT_MSB _u(1) 3020 #define PADS_BANK0_GPIO37_SCHMITT_LSB _u(1) 3021 #define PADS_BANK0_GPIO37_SCHMITT_ACCESS "RW" 3022 // ----------------------------------------------------------------------------- 3023 // Field : PADS_BANK0_GPIO37_SLEWFAST 3024 // Description : Slew rate control. 1 = Fast, 0 = Slow 3025 #define PADS_BANK0_GPIO37_SLEWFAST_RESET _u(0x0) 3026 #define PADS_BANK0_GPIO37_SLEWFAST_BITS _u(0x00000001) 3027 #define PADS_BANK0_GPIO37_SLEWFAST_MSB _u(0) 3028 #define PADS_BANK0_GPIO37_SLEWFAST_LSB _u(0) 3029 #define PADS_BANK0_GPIO37_SLEWFAST_ACCESS "RW" 3030 // ============================================================================= 3031 // Register : PADS_BANK0_GPIO38 3032 #define PADS_BANK0_GPIO38_OFFSET _u(0x0000009c) 3033 #define PADS_BANK0_GPIO38_BITS _u(0x000001ff) 3034 #define PADS_BANK0_GPIO38_RESET _u(0x00000116) 3035 // ----------------------------------------------------------------------------- 3036 // Field : PADS_BANK0_GPIO38_ISO 3037 // Description : Pad isolation control. Remove this once the pad is configured 3038 // by software. 3039 #define PADS_BANK0_GPIO38_ISO_RESET _u(0x1) 3040 #define PADS_BANK0_GPIO38_ISO_BITS _u(0x00000100) 3041 #define PADS_BANK0_GPIO38_ISO_MSB _u(8) 3042 #define PADS_BANK0_GPIO38_ISO_LSB _u(8) 3043 #define PADS_BANK0_GPIO38_ISO_ACCESS "RW" 3044 // ----------------------------------------------------------------------------- 3045 // Field : PADS_BANK0_GPIO38_OD 3046 // Description : Output disable. Has priority over output enable from 3047 // peripherals 3048 #define PADS_BANK0_GPIO38_OD_RESET _u(0x0) 3049 #define PADS_BANK0_GPIO38_OD_BITS _u(0x00000080) 3050 #define PADS_BANK0_GPIO38_OD_MSB _u(7) 3051 #define PADS_BANK0_GPIO38_OD_LSB _u(7) 3052 #define PADS_BANK0_GPIO38_OD_ACCESS "RW" 3053 // ----------------------------------------------------------------------------- 3054 // Field : PADS_BANK0_GPIO38_IE 3055 // Description : Input enable 3056 #define PADS_BANK0_GPIO38_IE_RESET _u(0x0) 3057 #define PADS_BANK0_GPIO38_IE_BITS _u(0x00000040) 3058 #define PADS_BANK0_GPIO38_IE_MSB _u(6) 3059 #define PADS_BANK0_GPIO38_IE_LSB _u(6) 3060 #define PADS_BANK0_GPIO38_IE_ACCESS "RW" 3061 // ----------------------------------------------------------------------------- 3062 // Field : PADS_BANK0_GPIO38_DRIVE 3063 // Description : Drive strength. 3064 // 0x0 -> 2mA 3065 // 0x1 -> 4mA 3066 // 0x2 -> 8mA 3067 // 0x3 -> 12mA 3068 #define PADS_BANK0_GPIO38_DRIVE_RESET _u(0x1) 3069 #define PADS_BANK0_GPIO38_DRIVE_BITS _u(0x00000030) 3070 #define PADS_BANK0_GPIO38_DRIVE_MSB _u(5) 3071 #define PADS_BANK0_GPIO38_DRIVE_LSB _u(4) 3072 #define PADS_BANK0_GPIO38_DRIVE_ACCESS "RW" 3073 #define PADS_BANK0_GPIO38_DRIVE_VALUE_2MA _u(0x0) 3074 #define PADS_BANK0_GPIO38_DRIVE_VALUE_4MA _u(0x1) 3075 #define PADS_BANK0_GPIO38_DRIVE_VALUE_8MA _u(0x2) 3076 #define PADS_BANK0_GPIO38_DRIVE_VALUE_12MA _u(0x3) 3077 // ----------------------------------------------------------------------------- 3078 // Field : PADS_BANK0_GPIO38_PUE 3079 // Description : Pull up enable 3080 #define PADS_BANK0_GPIO38_PUE_RESET _u(0x0) 3081 #define PADS_BANK0_GPIO38_PUE_BITS _u(0x00000008) 3082 #define PADS_BANK0_GPIO38_PUE_MSB _u(3) 3083 #define PADS_BANK0_GPIO38_PUE_LSB _u(3) 3084 #define PADS_BANK0_GPIO38_PUE_ACCESS "RW" 3085 // ----------------------------------------------------------------------------- 3086 // Field : PADS_BANK0_GPIO38_PDE 3087 // Description : Pull down enable 3088 #define PADS_BANK0_GPIO38_PDE_RESET _u(0x1) 3089 #define PADS_BANK0_GPIO38_PDE_BITS _u(0x00000004) 3090 #define PADS_BANK0_GPIO38_PDE_MSB _u(2) 3091 #define PADS_BANK0_GPIO38_PDE_LSB _u(2) 3092 #define PADS_BANK0_GPIO38_PDE_ACCESS "RW" 3093 // ----------------------------------------------------------------------------- 3094 // Field : PADS_BANK0_GPIO38_SCHMITT 3095 // Description : Enable schmitt trigger 3096 #define PADS_BANK0_GPIO38_SCHMITT_RESET _u(0x1) 3097 #define PADS_BANK0_GPIO38_SCHMITT_BITS _u(0x00000002) 3098 #define PADS_BANK0_GPIO38_SCHMITT_MSB _u(1) 3099 #define PADS_BANK0_GPIO38_SCHMITT_LSB _u(1) 3100 #define PADS_BANK0_GPIO38_SCHMITT_ACCESS "RW" 3101 // ----------------------------------------------------------------------------- 3102 // Field : PADS_BANK0_GPIO38_SLEWFAST 3103 // Description : Slew rate control. 1 = Fast, 0 = Slow 3104 #define PADS_BANK0_GPIO38_SLEWFAST_RESET _u(0x0) 3105 #define PADS_BANK0_GPIO38_SLEWFAST_BITS _u(0x00000001) 3106 #define PADS_BANK0_GPIO38_SLEWFAST_MSB _u(0) 3107 #define PADS_BANK0_GPIO38_SLEWFAST_LSB _u(0) 3108 #define PADS_BANK0_GPIO38_SLEWFAST_ACCESS "RW" 3109 // ============================================================================= 3110 // Register : PADS_BANK0_GPIO39 3111 #define PADS_BANK0_GPIO39_OFFSET _u(0x000000a0) 3112 #define PADS_BANK0_GPIO39_BITS _u(0x000001ff) 3113 #define PADS_BANK0_GPIO39_RESET _u(0x00000116) 3114 // ----------------------------------------------------------------------------- 3115 // Field : PADS_BANK0_GPIO39_ISO 3116 // Description : Pad isolation control. Remove this once the pad is configured 3117 // by software. 3118 #define PADS_BANK0_GPIO39_ISO_RESET _u(0x1) 3119 #define PADS_BANK0_GPIO39_ISO_BITS _u(0x00000100) 3120 #define PADS_BANK0_GPIO39_ISO_MSB _u(8) 3121 #define PADS_BANK0_GPIO39_ISO_LSB _u(8) 3122 #define PADS_BANK0_GPIO39_ISO_ACCESS "RW" 3123 // ----------------------------------------------------------------------------- 3124 // Field : PADS_BANK0_GPIO39_OD 3125 // Description : Output disable. Has priority over output enable from 3126 // peripherals 3127 #define PADS_BANK0_GPIO39_OD_RESET _u(0x0) 3128 #define PADS_BANK0_GPIO39_OD_BITS _u(0x00000080) 3129 #define PADS_BANK0_GPIO39_OD_MSB _u(7) 3130 #define PADS_BANK0_GPIO39_OD_LSB _u(7) 3131 #define PADS_BANK0_GPIO39_OD_ACCESS "RW" 3132 // ----------------------------------------------------------------------------- 3133 // Field : PADS_BANK0_GPIO39_IE 3134 // Description : Input enable 3135 #define PADS_BANK0_GPIO39_IE_RESET _u(0x0) 3136 #define PADS_BANK0_GPIO39_IE_BITS _u(0x00000040) 3137 #define PADS_BANK0_GPIO39_IE_MSB _u(6) 3138 #define PADS_BANK0_GPIO39_IE_LSB _u(6) 3139 #define PADS_BANK0_GPIO39_IE_ACCESS "RW" 3140 // ----------------------------------------------------------------------------- 3141 // Field : PADS_BANK0_GPIO39_DRIVE 3142 // Description : Drive strength. 3143 // 0x0 -> 2mA 3144 // 0x1 -> 4mA 3145 // 0x2 -> 8mA 3146 // 0x3 -> 12mA 3147 #define PADS_BANK0_GPIO39_DRIVE_RESET _u(0x1) 3148 #define PADS_BANK0_GPIO39_DRIVE_BITS _u(0x00000030) 3149 #define PADS_BANK0_GPIO39_DRIVE_MSB _u(5) 3150 #define PADS_BANK0_GPIO39_DRIVE_LSB _u(4) 3151 #define PADS_BANK0_GPIO39_DRIVE_ACCESS "RW" 3152 #define PADS_BANK0_GPIO39_DRIVE_VALUE_2MA _u(0x0) 3153 #define PADS_BANK0_GPIO39_DRIVE_VALUE_4MA _u(0x1) 3154 #define PADS_BANK0_GPIO39_DRIVE_VALUE_8MA _u(0x2) 3155 #define PADS_BANK0_GPIO39_DRIVE_VALUE_12MA _u(0x3) 3156 // ----------------------------------------------------------------------------- 3157 // Field : PADS_BANK0_GPIO39_PUE 3158 // Description : Pull up enable 3159 #define PADS_BANK0_GPIO39_PUE_RESET _u(0x0) 3160 #define PADS_BANK0_GPIO39_PUE_BITS _u(0x00000008) 3161 #define PADS_BANK0_GPIO39_PUE_MSB _u(3) 3162 #define PADS_BANK0_GPIO39_PUE_LSB _u(3) 3163 #define PADS_BANK0_GPIO39_PUE_ACCESS "RW" 3164 // ----------------------------------------------------------------------------- 3165 // Field : PADS_BANK0_GPIO39_PDE 3166 // Description : Pull down enable 3167 #define PADS_BANK0_GPIO39_PDE_RESET _u(0x1) 3168 #define PADS_BANK0_GPIO39_PDE_BITS _u(0x00000004) 3169 #define PADS_BANK0_GPIO39_PDE_MSB _u(2) 3170 #define PADS_BANK0_GPIO39_PDE_LSB _u(2) 3171 #define PADS_BANK0_GPIO39_PDE_ACCESS "RW" 3172 // ----------------------------------------------------------------------------- 3173 // Field : PADS_BANK0_GPIO39_SCHMITT 3174 // Description : Enable schmitt trigger 3175 #define PADS_BANK0_GPIO39_SCHMITT_RESET _u(0x1) 3176 #define PADS_BANK0_GPIO39_SCHMITT_BITS _u(0x00000002) 3177 #define PADS_BANK0_GPIO39_SCHMITT_MSB _u(1) 3178 #define PADS_BANK0_GPIO39_SCHMITT_LSB _u(1) 3179 #define PADS_BANK0_GPIO39_SCHMITT_ACCESS "RW" 3180 // ----------------------------------------------------------------------------- 3181 // Field : PADS_BANK0_GPIO39_SLEWFAST 3182 // Description : Slew rate control. 1 = Fast, 0 = Slow 3183 #define PADS_BANK0_GPIO39_SLEWFAST_RESET _u(0x0) 3184 #define PADS_BANK0_GPIO39_SLEWFAST_BITS _u(0x00000001) 3185 #define PADS_BANK0_GPIO39_SLEWFAST_MSB _u(0) 3186 #define PADS_BANK0_GPIO39_SLEWFAST_LSB _u(0) 3187 #define PADS_BANK0_GPIO39_SLEWFAST_ACCESS "RW" 3188 // ============================================================================= 3189 // Register : PADS_BANK0_GPIO40 3190 #define PADS_BANK0_GPIO40_OFFSET _u(0x000000a4) 3191 #define PADS_BANK0_GPIO40_BITS _u(0x000001ff) 3192 #define PADS_BANK0_GPIO40_RESET _u(0x00000116) 3193 // ----------------------------------------------------------------------------- 3194 // Field : PADS_BANK0_GPIO40_ISO 3195 // Description : Pad isolation control. Remove this once the pad is configured 3196 // by software. 3197 #define PADS_BANK0_GPIO40_ISO_RESET _u(0x1) 3198 #define PADS_BANK0_GPIO40_ISO_BITS _u(0x00000100) 3199 #define PADS_BANK0_GPIO40_ISO_MSB _u(8) 3200 #define PADS_BANK0_GPIO40_ISO_LSB _u(8) 3201 #define PADS_BANK0_GPIO40_ISO_ACCESS "RW" 3202 // ----------------------------------------------------------------------------- 3203 // Field : PADS_BANK0_GPIO40_OD 3204 // Description : Output disable. Has priority over output enable from 3205 // peripherals 3206 #define PADS_BANK0_GPIO40_OD_RESET _u(0x0) 3207 #define PADS_BANK0_GPIO40_OD_BITS _u(0x00000080) 3208 #define PADS_BANK0_GPIO40_OD_MSB _u(7) 3209 #define PADS_BANK0_GPIO40_OD_LSB _u(7) 3210 #define PADS_BANK0_GPIO40_OD_ACCESS "RW" 3211 // ----------------------------------------------------------------------------- 3212 // Field : PADS_BANK0_GPIO40_IE 3213 // Description : Input enable 3214 #define PADS_BANK0_GPIO40_IE_RESET _u(0x0) 3215 #define PADS_BANK0_GPIO40_IE_BITS _u(0x00000040) 3216 #define PADS_BANK0_GPIO40_IE_MSB _u(6) 3217 #define PADS_BANK0_GPIO40_IE_LSB _u(6) 3218 #define PADS_BANK0_GPIO40_IE_ACCESS "RW" 3219 // ----------------------------------------------------------------------------- 3220 // Field : PADS_BANK0_GPIO40_DRIVE 3221 // Description : Drive strength. 3222 // 0x0 -> 2mA 3223 // 0x1 -> 4mA 3224 // 0x2 -> 8mA 3225 // 0x3 -> 12mA 3226 #define PADS_BANK0_GPIO40_DRIVE_RESET _u(0x1) 3227 #define PADS_BANK0_GPIO40_DRIVE_BITS _u(0x00000030) 3228 #define PADS_BANK0_GPIO40_DRIVE_MSB _u(5) 3229 #define PADS_BANK0_GPIO40_DRIVE_LSB _u(4) 3230 #define PADS_BANK0_GPIO40_DRIVE_ACCESS "RW" 3231 #define PADS_BANK0_GPIO40_DRIVE_VALUE_2MA _u(0x0) 3232 #define PADS_BANK0_GPIO40_DRIVE_VALUE_4MA _u(0x1) 3233 #define PADS_BANK0_GPIO40_DRIVE_VALUE_8MA _u(0x2) 3234 #define PADS_BANK0_GPIO40_DRIVE_VALUE_12MA _u(0x3) 3235 // ----------------------------------------------------------------------------- 3236 // Field : PADS_BANK0_GPIO40_PUE 3237 // Description : Pull up enable 3238 #define PADS_BANK0_GPIO40_PUE_RESET _u(0x0) 3239 #define PADS_BANK0_GPIO40_PUE_BITS _u(0x00000008) 3240 #define PADS_BANK0_GPIO40_PUE_MSB _u(3) 3241 #define PADS_BANK0_GPIO40_PUE_LSB _u(3) 3242 #define PADS_BANK0_GPIO40_PUE_ACCESS "RW" 3243 // ----------------------------------------------------------------------------- 3244 // Field : PADS_BANK0_GPIO40_PDE 3245 // Description : Pull down enable 3246 #define PADS_BANK0_GPIO40_PDE_RESET _u(0x1) 3247 #define PADS_BANK0_GPIO40_PDE_BITS _u(0x00000004) 3248 #define PADS_BANK0_GPIO40_PDE_MSB _u(2) 3249 #define PADS_BANK0_GPIO40_PDE_LSB _u(2) 3250 #define PADS_BANK0_GPIO40_PDE_ACCESS "RW" 3251 // ----------------------------------------------------------------------------- 3252 // Field : PADS_BANK0_GPIO40_SCHMITT 3253 // Description : Enable schmitt trigger 3254 #define PADS_BANK0_GPIO40_SCHMITT_RESET _u(0x1) 3255 #define PADS_BANK0_GPIO40_SCHMITT_BITS _u(0x00000002) 3256 #define PADS_BANK0_GPIO40_SCHMITT_MSB _u(1) 3257 #define PADS_BANK0_GPIO40_SCHMITT_LSB _u(1) 3258 #define PADS_BANK0_GPIO40_SCHMITT_ACCESS "RW" 3259 // ----------------------------------------------------------------------------- 3260 // Field : PADS_BANK0_GPIO40_SLEWFAST 3261 // Description : Slew rate control. 1 = Fast, 0 = Slow 3262 #define PADS_BANK0_GPIO40_SLEWFAST_RESET _u(0x0) 3263 #define PADS_BANK0_GPIO40_SLEWFAST_BITS _u(0x00000001) 3264 #define PADS_BANK0_GPIO40_SLEWFAST_MSB _u(0) 3265 #define PADS_BANK0_GPIO40_SLEWFAST_LSB _u(0) 3266 #define PADS_BANK0_GPIO40_SLEWFAST_ACCESS "RW" 3267 // ============================================================================= 3268 // Register : PADS_BANK0_GPIO41 3269 #define PADS_BANK0_GPIO41_OFFSET _u(0x000000a8) 3270 #define PADS_BANK0_GPIO41_BITS _u(0x000001ff) 3271 #define PADS_BANK0_GPIO41_RESET _u(0x00000116) 3272 // ----------------------------------------------------------------------------- 3273 // Field : PADS_BANK0_GPIO41_ISO 3274 // Description : Pad isolation control. Remove this once the pad is configured 3275 // by software. 3276 #define PADS_BANK0_GPIO41_ISO_RESET _u(0x1) 3277 #define PADS_BANK0_GPIO41_ISO_BITS _u(0x00000100) 3278 #define PADS_BANK0_GPIO41_ISO_MSB _u(8) 3279 #define PADS_BANK0_GPIO41_ISO_LSB _u(8) 3280 #define PADS_BANK0_GPIO41_ISO_ACCESS "RW" 3281 // ----------------------------------------------------------------------------- 3282 // Field : PADS_BANK0_GPIO41_OD 3283 // Description : Output disable. Has priority over output enable from 3284 // peripherals 3285 #define PADS_BANK0_GPIO41_OD_RESET _u(0x0) 3286 #define PADS_BANK0_GPIO41_OD_BITS _u(0x00000080) 3287 #define PADS_BANK0_GPIO41_OD_MSB _u(7) 3288 #define PADS_BANK0_GPIO41_OD_LSB _u(7) 3289 #define PADS_BANK0_GPIO41_OD_ACCESS "RW" 3290 // ----------------------------------------------------------------------------- 3291 // Field : PADS_BANK0_GPIO41_IE 3292 // Description : Input enable 3293 #define PADS_BANK0_GPIO41_IE_RESET _u(0x0) 3294 #define PADS_BANK0_GPIO41_IE_BITS _u(0x00000040) 3295 #define PADS_BANK0_GPIO41_IE_MSB _u(6) 3296 #define PADS_BANK0_GPIO41_IE_LSB _u(6) 3297 #define PADS_BANK0_GPIO41_IE_ACCESS "RW" 3298 // ----------------------------------------------------------------------------- 3299 // Field : PADS_BANK0_GPIO41_DRIVE 3300 // Description : Drive strength. 3301 // 0x0 -> 2mA 3302 // 0x1 -> 4mA 3303 // 0x2 -> 8mA 3304 // 0x3 -> 12mA 3305 #define PADS_BANK0_GPIO41_DRIVE_RESET _u(0x1) 3306 #define PADS_BANK0_GPIO41_DRIVE_BITS _u(0x00000030) 3307 #define PADS_BANK0_GPIO41_DRIVE_MSB _u(5) 3308 #define PADS_BANK0_GPIO41_DRIVE_LSB _u(4) 3309 #define PADS_BANK0_GPIO41_DRIVE_ACCESS "RW" 3310 #define PADS_BANK0_GPIO41_DRIVE_VALUE_2MA _u(0x0) 3311 #define PADS_BANK0_GPIO41_DRIVE_VALUE_4MA _u(0x1) 3312 #define PADS_BANK0_GPIO41_DRIVE_VALUE_8MA _u(0x2) 3313 #define PADS_BANK0_GPIO41_DRIVE_VALUE_12MA _u(0x3) 3314 // ----------------------------------------------------------------------------- 3315 // Field : PADS_BANK0_GPIO41_PUE 3316 // Description : Pull up enable 3317 #define PADS_BANK0_GPIO41_PUE_RESET _u(0x0) 3318 #define PADS_BANK0_GPIO41_PUE_BITS _u(0x00000008) 3319 #define PADS_BANK0_GPIO41_PUE_MSB _u(3) 3320 #define PADS_BANK0_GPIO41_PUE_LSB _u(3) 3321 #define PADS_BANK0_GPIO41_PUE_ACCESS "RW" 3322 // ----------------------------------------------------------------------------- 3323 // Field : PADS_BANK0_GPIO41_PDE 3324 // Description : Pull down enable 3325 #define PADS_BANK0_GPIO41_PDE_RESET _u(0x1) 3326 #define PADS_BANK0_GPIO41_PDE_BITS _u(0x00000004) 3327 #define PADS_BANK0_GPIO41_PDE_MSB _u(2) 3328 #define PADS_BANK0_GPIO41_PDE_LSB _u(2) 3329 #define PADS_BANK0_GPIO41_PDE_ACCESS "RW" 3330 // ----------------------------------------------------------------------------- 3331 // Field : PADS_BANK0_GPIO41_SCHMITT 3332 // Description : Enable schmitt trigger 3333 #define PADS_BANK0_GPIO41_SCHMITT_RESET _u(0x1) 3334 #define PADS_BANK0_GPIO41_SCHMITT_BITS _u(0x00000002) 3335 #define PADS_BANK0_GPIO41_SCHMITT_MSB _u(1) 3336 #define PADS_BANK0_GPIO41_SCHMITT_LSB _u(1) 3337 #define PADS_BANK0_GPIO41_SCHMITT_ACCESS "RW" 3338 // ----------------------------------------------------------------------------- 3339 // Field : PADS_BANK0_GPIO41_SLEWFAST 3340 // Description : Slew rate control. 1 = Fast, 0 = Slow 3341 #define PADS_BANK0_GPIO41_SLEWFAST_RESET _u(0x0) 3342 #define PADS_BANK0_GPIO41_SLEWFAST_BITS _u(0x00000001) 3343 #define PADS_BANK0_GPIO41_SLEWFAST_MSB _u(0) 3344 #define PADS_BANK0_GPIO41_SLEWFAST_LSB _u(0) 3345 #define PADS_BANK0_GPIO41_SLEWFAST_ACCESS "RW" 3346 // ============================================================================= 3347 // Register : PADS_BANK0_GPIO42 3348 #define PADS_BANK0_GPIO42_OFFSET _u(0x000000ac) 3349 #define PADS_BANK0_GPIO42_BITS _u(0x000001ff) 3350 #define PADS_BANK0_GPIO42_RESET _u(0x00000116) 3351 // ----------------------------------------------------------------------------- 3352 // Field : PADS_BANK0_GPIO42_ISO 3353 // Description : Pad isolation control. Remove this once the pad is configured 3354 // by software. 3355 #define PADS_BANK0_GPIO42_ISO_RESET _u(0x1) 3356 #define PADS_BANK0_GPIO42_ISO_BITS _u(0x00000100) 3357 #define PADS_BANK0_GPIO42_ISO_MSB _u(8) 3358 #define PADS_BANK0_GPIO42_ISO_LSB _u(8) 3359 #define PADS_BANK0_GPIO42_ISO_ACCESS "RW" 3360 // ----------------------------------------------------------------------------- 3361 // Field : PADS_BANK0_GPIO42_OD 3362 // Description : Output disable. Has priority over output enable from 3363 // peripherals 3364 #define PADS_BANK0_GPIO42_OD_RESET _u(0x0) 3365 #define PADS_BANK0_GPIO42_OD_BITS _u(0x00000080) 3366 #define PADS_BANK0_GPIO42_OD_MSB _u(7) 3367 #define PADS_BANK0_GPIO42_OD_LSB _u(7) 3368 #define PADS_BANK0_GPIO42_OD_ACCESS "RW" 3369 // ----------------------------------------------------------------------------- 3370 // Field : PADS_BANK0_GPIO42_IE 3371 // Description : Input enable 3372 #define PADS_BANK0_GPIO42_IE_RESET _u(0x0) 3373 #define PADS_BANK0_GPIO42_IE_BITS _u(0x00000040) 3374 #define PADS_BANK0_GPIO42_IE_MSB _u(6) 3375 #define PADS_BANK0_GPIO42_IE_LSB _u(6) 3376 #define PADS_BANK0_GPIO42_IE_ACCESS "RW" 3377 // ----------------------------------------------------------------------------- 3378 // Field : PADS_BANK0_GPIO42_DRIVE 3379 // Description : Drive strength. 3380 // 0x0 -> 2mA 3381 // 0x1 -> 4mA 3382 // 0x2 -> 8mA 3383 // 0x3 -> 12mA 3384 #define PADS_BANK0_GPIO42_DRIVE_RESET _u(0x1) 3385 #define PADS_BANK0_GPIO42_DRIVE_BITS _u(0x00000030) 3386 #define PADS_BANK0_GPIO42_DRIVE_MSB _u(5) 3387 #define PADS_BANK0_GPIO42_DRIVE_LSB _u(4) 3388 #define PADS_BANK0_GPIO42_DRIVE_ACCESS "RW" 3389 #define PADS_BANK0_GPIO42_DRIVE_VALUE_2MA _u(0x0) 3390 #define PADS_BANK0_GPIO42_DRIVE_VALUE_4MA _u(0x1) 3391 #define PADS_BANK0_GPIO42_DRIVE_VALUE_8MA _u(0x2) 3392 #define PADS_BANK0_GPIO42_DRIVE_VALUE_12MA _u(0x3) 3393 // ----------------------------------------------------------------------------- 3394 // Field : PADS_BANK0_GPIO42_PUE 3395 // Description : Pull up enable 3396 #define PADS_BANK0_GPIO42_PUE_RESET _u(0x0) 3397 #define PADS_BANK0_GPIO42_PUE_BITS _u(0x00000008) 3398 #define PADS_BANK0_GPIO42_PUE_MSB _u(3) 3399 #define PADS_BANK0_GPIO42_PUE_LSB _u(3) 3400 #define PADS_BANK0_GPIO42_PUE_ACCESS "RW" 3401 // ----------------------------------------------------------------------------- 3402 // Field : PADS_BANK0_GPIO42_PDE 3403 // Description : Pull down enable 3404 #define PADS_BANK0_GPIO42_PDE_RESET _u(0x1) 3405 #define PADS_BANK0_GPIO42_PDE_BITS _u(0x00000004) 3406 #define PADS_BANK0_GPIO42_PDE_MSB _u(2) 3407 #define PADS_BANK0_GPIO42_PDE_LSB _u(2) 3408 #define PADS_BANK0_GPIO42_PDE_ACCESS "RW" 3409 // ----------------------------------------------------------------------------- 3410 // Field : PADS_BANK0_GPIO42_SCHMITT 3411 // Description : Enable schmitt trigger 3412 #define PADS_BANK0_GPIO42_SCHMITT_RESET _u(0x1) 3413 #define PADS_BANK0_GPIO42_SCHMITT_BITS _u(0x00000002) 3414 #define PADS_BANK0_GPIO42_SCHMITT_MSB _u(1) 3415 #define PADS_BANK0_GPIO42_SCHMITT_LSB _u(1) 3416 #define PADS_BANK0_GPIO42_SCHMITT_ACCESS "RW" 3417 // ----------------------------------------------------------------------------- 3418 // Field : PADS_BANK0_GPIO42_SLEWFAST 3419 // Description : Slew rate control. 1 = Fast, 0 = Slow 3420 #define PADS_BANK0_GPIO42_SLEWFAST_RESET _u(0x0) 3421 #define PADS_BANK0_GPIO42_SLEWFAST_BITS _u(0x00000001) 3422 #define PADS_BANK0_GPIO42_SLEWFAST_MSB _u(0) 3423 #define PADS_BANK0_GPIO42_SLEWFAST_LSB _u(0) 3424 #define PADS_BANK0_GPIO42_SLEWFAST_ACCESS "RW" 3425 // ============================================================================= 3426 // Register : PADS_BANK0_GPIO43 3427 #define PADS_BANK0_GPIO43_OFFSET _u(0x000000b0) 3428 #define PADS_BANK0_GPIO43_BITS _u(0x000001ff) 3429 #define PADS_BANK0_GPIO43_RESET _u(0x00000116) 3430 // ----------------------------------------------------------------------------- 3431 // Field : PADS_BANK0_GPIO43_ISO 3432 // Description : Pad isolation control. Remove this once the pad is configured 3433 // by software. 3434 #define PADS_BANK0_GPIO43_ISO_RESET _u(0x1) 3435 #define PADS_BANK0_GPIO43_ISO_BITS _u(0x00000100) 3436 #define PADS_BANK0_GPIO43_ISO_MSB _u(8) 3437 #define PADS_BANK0_GPIO43_ISO_LSB _u(8) 3438 #define PADS_BANK0_GPIO43_ISO_ACCESS "RW" 3439 // ----------------------------------------------------------------------------- 3440 // Field : PADS_BANK0_GPIO43_OD 3441 // Description : Output disable. Has priority over output enable from 3442 // peripherals 3443 #define PADS_BANK0_GPIO43_OD_RESET _u(0x0) 3444 #define PADS_BANK0_GPIO43_OD_BITS _u(0x00000080) 3445 #define PADS_BANK0_GPIO43_OD_MSB _u(7) 3446 #define PADS_BANK0_GPIO43_OD_LSB _u(7) 3447 #define PADS_BANK0_GPIO43_OD_ACCESS "RW" 3448 // ----------------------------------------------------------------------------- 3449 // Field : PADS_BANK0_GPIO43_IE 3450 // Description : Input enable 3451 #define PADS_BANK0_GPIO43_IE_RESET _u(0x0) 3452 #define PADS_BANK0_GPIO43_IE_BITS _u(0x00000040) 3453 #define PADS_BANK0_GPIO43_IE_MSB _u(6) 3454 #define PADS_BANK0_GPIO43_IE_LSB _u(6) 3455 #define PADS_BANK0_GPIO43_IE_ACCESS "RW" 3456 // ----------------------------------------------------------------------------- 3457 // Field : PADS_BANK0_GPIO43_DRIVE 3458 // Description : Drive strength. 3459 // 0x0 -> 2mA 3460 // 0x1 -> 4mA 3461 // 0x2 -> 8mA 3462 // 0x3 -> 12mA 3463 #define PADS_BANK0_GPIO43_DRIVE_RESET _u(0x1) 3464 #define PADS_BANK0_GPIO43_DRIVE_BITS _u(0x00000030) 3465 #define PADS_BANK0_GPIO43_DRIVE_MSB _u(5) 3466 #define PADS_BANK0_GPIO43_DRIVE_LSB _u(4) 3467 #define PADS_BANK0_GPIO43_DRIVE_ACCESS "RW" 3468 #define PADS_BANK0_GPIO43_DRIVE_VALUE_2MA _u(0x0) 3469 #define PADS_BANK0_GPIO43_DRIVE_VALUE_4MA _u(0x1) 3470 #define PADS_BANK0_GPIO43_DRIVE_VALUE_8MA _u(0x2) 3471 #define PADS_BANK0_GPIO43_DRIVE_VALUE_12MA _u(0x3) 3472 // ----------------------------------------------------------------------------- 3473 // Field : PADS_BANK0_GPIO43_PUE 3474 // Description : Pull up enable 3475 #define PADS_BANK0_GPIO43_PUE_RESET _u(0x0) 3476 #define PADS_BANK0_GPIO43_PUE_BITS _u(0x00000008) 3477 #define PADS_BANK0_GPIO43_PUE_MSB _u(3) 3478 #define PADS_BANK0_GPIO43_PUE_LSB _u(3) 3479 #define PADS_BANK0_GPIO43_PUE_ACCESS "RW" 3480 // ----------------------------------------------------------------------------- 3481 // Field : PADS_BANK0_GPIO43_PDE 3482 // Description : Pull down enable 3483 #define PADS_BANK0_GPIO43_PDE_RESET _u(0x1) 3484 #define PADS_BANK0_GPIO43_PDE_BITS _u(0x00000004) 3485 #define PADS_BANK0_GPIO43_PDE_MSB _u(2) 3486 #define PADS_BANK0_GPIO43_PDE_LSB _u(2) 3487 #define PADS_BANK0_GPIO43_PDE_ACCESS "RW" 3488 // ----------------------------------------------------------------------------- 3489 // Field : PADS_BANK0_GPIO43_SCHMITT 3490 // Description : Enable schmitt trigger 3491 #define PADS_BANK0_GPIO43_SCHMITT_RESET _u(0x1) 3492 #define PADS_BANK0_GPIO43_SCHMITT_BITS _u(0x00000002) 3493 #define PADS_BANK0_GPIO43_SCHMITT_MSB _u(1) 3494 #define PADS_BANK0_GPIO43_SCHMITT_LSB _u(1) 3495 #define PADS_BANK0_GPIO43_SCHMITT_ACCESS "RW" 3496 // ----------------------------------------------------------------------------- 3497 // Field : PADS_BANK0_GPIO43_SLEWFAST 3498 // Description : Slew rate control. 1 = Fast, 0 = Slow 3499 #define PADS_BANK0_GPIO43_SLEWFAST_RESET _u(0x0) 3500 #define PADS_BANK0_GPIO43_SLEWFAST_BITS _u(0x00000001) 3501 #define PADS_BANK0_GPIO43_SLEWFAST_MSB _u(0) 3502 #define PADS_BANK0_GPIO43_SLEWFAST_LSB _u(0) 3503 #define PADS_BANK0_GPIO43_SLEWFAST_ACCESS "RW" 3504 // ============================================================================= 3505 // Register : PADS_BANK0_GPIO44 3506 #define PADS_BANK0_GPIO44_OFFSET _u(0x000000b4) 3507 #define PADS_BANK0_GPIO44_BITS _u(0x000001ff) 3508 #define PADS_BANK0_GPIO44_RESET _u(0x00000116) 3509 // ----------------------------------------------------------------------------- 3510 // Field : PADS_BANK0_GPIO44_ISO 3511 // Description : Pad isolation control. Remove this once the pad is configured 3512 // by software. 3513 #define PADS_BANK0_GPIO44_ISO_RESET _u(0x1) 3514 #define PADS_BANK0_GPIO44_ISO_BITS _u(0x00000100) 3515 #define PADS_BANK0_GPIO44_ISO_MSB _u(8) 3516 #define PADS_BANK0_GPIO44_ISO_LSB _u(8) 3517 #define PADS_BANK0_GPIO44_ISO_ACCESS "RW" 3518 // ----------------------------------------------------------------------------- 3519 // Field : PADS_BANK0_GPIO44_OD 3520 // Description : Output disable. Has priority over output enable from 3521 // peripherals 3522 #define PADS_BANK0_GPIO44_OD_RESET _u(0x0) 3523 #define PADS_BANK0_GPIO44_OD_BITS _u(0x00000080) 3524 #define PADS_BANK0_GPIO44_OD_MSB _u(7) 3525 #define PADS_BANK0_GPIO44_OD_LSB _u(7) 3526 #define PADS_BANK0_GPIO44_OD_ACCESS "RW" 3527 // ----------------------------------------------------------------------------- 3528 // Field : PADS_BANK0_GPIO44_IE 3529 // Description : Input enable 3530 #define PADS_BANK0_GPIO44_IE_RESET _u(0x0) 3531 #define PADS_BANK0_GPIO44_IE_BITS _u(0x00000040) 3532 #define PADS_BANK0_GPIO44_IE_MSB _u(6) 3533 #define PADS_BANK0_GPIO44_IE_LSB _u(6) 3534 #define PADS_BANK0_GPIO44_IE_ACCESS "RW" 3535 // ----------------------------------------------------------------------------- 3536 // Field : PADS_BANK0_GPIO44_DRIVE 3537 // Description : Drive strength. 3538 // 0x0 -> 2mA 3539 // 0x1 -> 4mA 3540 // 0x2 -> 8mA 3541 // 0x3 -> 12mA 3542 #define PADS_BANK0_GPIO44_DRIVE_RESET _u(0x1) 3543 #define PADS_BANK0_GPIO44_DRIVE_BITS _u(0x00000030) 3544 #define PADS_BANK0_GPIO44_DRIVE_MSB _u(5) 3545 #define PADS_BANK0_GPIO44_DRIVE_LSB _u(4) 3546 #define PADS_BANK0_GPIO44_DRIVE_ACCESS "RW" 3547 #define PADS_BANK0_GPIO44_DRIVE_VALUE_2MA _u(0x0) 3548 #define PADS_BANK0_GPIO44_DRIVE_VALUE_4MA _u(0x1) 3549 #define PADS_BANK0_GPIO44_DRIVE_VALUE_8MA _u(0x2) 3550 #define PADS_BANK0_GPIO44_DRIVE_VALUE_12MA _u(0x3) 3551 // ----------------------------------------------------------------------------- 3552 // Field : PADS_BANK0_GPIO44_PUE 3553 // Description : Pull up enable 3554 #define PADS_BANK0_GPIO44_PUE_RESET _u(0x0) 3555 #define PADS_BANK0_GPIO44_PUE_BITS _u(0x00000008) 3556 #define PADS_BANK0_GPIO44_PUE_MSB _u(3) 3557 #define PADS_BANK0_GPIO44_PUE_LSB _u(3) 3558 #define PADS_BANK0_GPIO44_PUE_ACCESS "RW" 3559 // ----------------------------------------------------------------------------- 3560 // Field : PADS_BANK0_GPIO44_PDE 3561 // Description : Pull down enable 3562 #define PADS_BANK0_GPIO44_PDE_RESET _u(0x1) 3563 #define PADS_BANK0_GPIO44_PDE_BITS _u(0x00000004) 3564 #define PADS_BANK0_GPIO44_PDE_MSB _u(2) 3565 #define PADS_BANK0_GPIO44_PDE_LSB _u(2) 3566 #define PADS_BANK0_GPIO44_PDE_ACCESS "RW" 3567 // ----------------------------------------------------------------------------- 3568 // Field : PADS_BANK0_GPIO44_SCHMITT 3569 // Description : Enable schmitt trigger 3570 #define PADS_BANK0_GPIO44_SCHMITT_RESET _u(0x1) 3571 #define PADS_BANK0_GPIO44_SCHMITT_BITS _u(0x00000002) 3572 #define PADS_BANK0_GPIO44_SCHMITT_MSB _u(1) 3573 #define PADS_BANK0_GPIO44_SCHMITT_LSB _u(1) 3574 #define PADS_BANK0_GPIO44_SCHMITT_ACCESS "RW" 3575 // ----------------------------------------------------------------------------- 3576 // Field : PADS_BANK0_GPIO44_SLEWFAST 3577 // Description : Slew rate control. 1 = Fast, 0 = Slow 3578 #define PADS_BANK0_GPIO44_SLEWFAST_RESET _u(0x0) 3579 #define PADS_BANK0_GPIO44_SLEWFAST_BITS _u(0x00000001) 3580 #define PADS_BANK0_GPIO44_SLEWFAST_MSB _u(0) 3581 #define PADS_BANK0_GPIO44_SLEWFAST_LSB _u(0) 3582 #define PADS_BANK0_GPIO44_SLEWFAST_ACCESS "RW" 3583 // ============================================================================= 3584 // Register : PADS_BANK0_GPIO45 3585 #define PADS_BANK0_GPIO45_OFFSET _u(0x000000b8) 3586 #define PADS_BANK0_GPIO45_BITS _u(0x000001ff) 3587 #define PADS_BANK0_GPIO45_RESET _u(0x00000116) 3588 // ----------------------------------------------------------------------------- 3589 // Field : PADS_BANK0_GPIO45_ISO 3590 // Description : Pad isolation control. Remove this once the pad is configured 3591 // by software. 3592 #define PADS_BANK0_GPIO45_ISO_RESET _u(0x1) 3593 #define PADS_BANK0_GPIO45_ISO_BITS _u(0x00000100) 3594 #define PADS_BANK0_GPIO45_ISO_MSB _u(8) 3595 #define PADS_BANK0_GPIO45_ISO_LSB _u(8) 3596 #define PADS_BANK0_GPIO45_ISO_ACCESS "RW" 3597 // ----------------------------------------------------------------------------- 3598 // Field : PADS_BANK0_GPIO45_OD 3599 // Description : Output disable. Has priority over output enable from 3600 // peripherals 3601 #define PADS_BANK0_GPIO45_OD_RESET _u(0x0) 3602 #define PADS_BANK0_GPIO45_OD_BITS _u(0x00000080) 3603 #define PADS_BANK0_GPIO45_OD_MSB _u(7) 3604 #define PADS_BANK0_GPIO45_OD_LSB _u(7) 3605 #define PADS_BANK0_GPIO45_OD_ACCESS "RW" 3606 // ----------------------------------------------------------------------------- 3607 // Field : PADS_BANK0_GPIO45_IE 3608 // Description : Input enable 3609 #define PADS_BANK0_GPIO45_IE_RESET _u(0x0) 3610 #define PADS_BANK0_GPIO45_IE_BITS _u(0x00000040) 3611 #define PADS_BANK0_GPIO45_IE_MSB _u(6) 3612 #define PADS_BANK0_GPIO45_IE_LSB _u(6) 3613 #define PADS_BANK0_GPIO45_IE_ACCESS "RW" 3614 // ----------------------------------------------------------------------------- 3615 // Field : PADS_BANK0_GPIO45_DRIVE 3616 // Description : Drive strength. 3617 // 0x0 -> 2mA 3618 // 0x1 -> 4mA 3619 // 0x2 -> 8mA 3620 // 0x3 -> 12mA 3621 #define PADS_BANK0_GPIO45_DRIVE_RESET _u(0x1) 3622 #define PADS_BANK0_GPIO45_DRIVE_BITS _u(0x00000030) 3623 #define PADS_BANK0_GPIO45_DRIVE_MSB _u(5) 3624 #define PADS_BANK0_GPIO45_DRIVE_LSB _u(4) 3625 #define PADS_BANK0_GPIO45_DRIVE_ACCESS "RW" 3626 #define PADS_BANK0_GPIO45_DRIVE_VALUE_2MA _u(0x0) 3627 #define PADS_BANK0_GPIO45_DRIVE_VALUE_4MA _u(0x1) 3628 #define PADS_BANK0_GPIO45_DRIVE_VALUE_8MA _u(0x2) 3629 #define PADS_BANK0_GPIO45_DRIVE_VALUE_12MA _u(0x3) 3630 // ----------------------------------------------------------------------------- 3631 // Field : PADS_BANK0_GPIO45_PUE 3632 // Description : Pull up enable 3633 #define PADS_BANK0_GPIO45_PUE_RESET _u(0x0) 3634 #define PADS_BANK0_GPIO45_PUE_BITS _u(0x00000008) 3635 #define PADS_BANK0_GPIO45_PUE_MSB _u(3) 3636 #define PADS_BANK0_GPIO45_PUE_LSB _u(3) 3637 #define PADS_BANK0_GPIO45_PUE_ACCESS "RW" 3638 // ----------------------------------------------------------------------------- 3639 // Field : PADS_BANK0_GPIO45_PDE 3640 // Description : Pull down enable 3641 #define PADS_BANK0_GPIO45_PDE_RESET _u(0x1) 3642 #define PADS_BANK0_GPIO45_PDE_BITS _u(0x00000004) 3643 #define PADS_BANK0_GPIO45_PDE_MSB _u(2) 3644 #define PADS_BANK0_GPIO45_PDE_LSB _u(2) 3645 #define PADS_BANK0_GPIO45_PDE_ACCESS "RW" 3646 // ----------------------------------------------------------------------------- 3647 // Field : PADS_BANK0_GPIO45_SCHMITT 3648 // Description : Enable schmitt trigger 3649 #define PADS_BANK0_GPIO45_SCHMITT_RESET _u(0x1) 3650 #define PADS_BANK0_GPIO45_SCHMITT_BITS _u(0x00000002) 3651 #define PADS_BANK0_GPIO45_SCHMITT_MSB _u(1) 3652 #define PADS_BANK0_GPIO45_SCHMITT_LSB _u(1) 3653 #define PADS_BANK0_GPIO45_SCHMITT_ACCESS "RW" 3654 // ----------------------------------------------------------------------------- 3655 // Field : PADS_BANK0_GPIO45_SLEWFAST 3656 // Description : Slew rate control. 1 = Fast, 0 = Slow 3657 #define PADS_BANK0_GPIO45_SLEWFAST_RESET _u(0x0) 3658 #define PADS_BANK0_GPIO45_SLEWFAST_BITS _u(0x00000001) 3659 #define PADS_BANK0_GPIO45_SLEWFAST_MSB _u(0) 3660 #define PADS_BANK0_GPIO45_SLEWFAST_LSB _u(0) 3661 #define PADS_BANK0_GPIO45_SLEWFAST_ACCESS "RW" 3662 // ============================================================================= 3663 // Register : PADS_BANK0_GPIO46 3664 #define PADS_BANK0_GPIO46_OFFSET _u(0x000000bc) 3665 #define PADS_BANK0_GPIO46_BITS _u(0x000001ff) 3666 #define PADS_BANK0_GPIO46_RESET _u(0x00000116) 3667 // ----------------------------------------------------------------------------- 3668 // Field : PADS_BANK0_GPIO46_ISO 3669 // Description : Pad isolation control. Remove this once the pad is configured 3670 // by software. 3671 #define PADS_BANK0_GPIO46_ISO_RESET _u(0x1) 3672 #define PADS_BANK0_GPIO46_ISO_BITS _u(0x00000100) 3673 #define PADS_BANK0_GPIO46_ISO_MSB _u(8) 3674 #define PADS_BANK0_GPIO46_ISO_LSB _u(8) 3675 #define PADS_BANK0_GPIO46_ISO_ACCESS "RW" 3676 // ----------------------------------------------------------------------------- 3677 // Field : PADS_BANK0_GPIO46_OD 3678 // Description : Output disable. Has priority over output enable from 3679 // peripherals 3680 #define PADS_BANK0_GPIO46_OD_RESET _u(0x0) 3681 #define PADS_BANK0_GPIO46_OD_BITS _u(0x00000080) 3682 #define PADS_BANK0_GPIO46_OD_MSB _u(7) 3683 #define PADS_BANK0_GPIO46_OD_LSB _u(7) 3684 #define PADS_BANK0_GPIO46_OD_ACCESS "RW" 3685 // ----------------------------------------------------------------------------- 3686 // Field : PADS_BANK0_GPIO46_IE 3687 // Description : Input enable 3688 #define PADS_BANK0_GPIO46_IE_RESET _u(0x0) 3689 #define PADS_BANK0_GPIO46_IE_BITS _u(0x00000040) 3690 #define PADS_BANK0_GPIO46_IE_MSB _u(6) 3691 #define PADS_BANK0_GPIO46_IE_LSB _u(6) 3692 #define PADS_BANK0_GPIO46_IE_ACCESS "RW" 3693 // ----------------------------------------------------------------------------- 3694 // Field : PADS_BANK0_GPIO46_DRIVE 3695 // Description : Drive strength. 3696 // 0x0 -> 2mA 3697 // 0x1 -> 4mA 3698 // 0x2 -> 8mA 3699 // 0x3 -> 12mA 3700 #define PADS_BANK0_GPIO46_DRIVE_RESET _u(0x1) 3701 #define PADS_BANK0_GPIO46_DRIVE_BITS _u(0x00000030) 3702 #define PADS_BANK0_GPIO46_DRIVE_MSB _u(5) 3703 #define PADS_BANK0_GPIO46_DRIVE_LSB _u(4) 3704 #define PADS_BANK0_GPIO46_DRIVE_ACCESS "RW" 3705 #define PADS_BANK0_GPIO46_DRIVE_VALUE_2MA _u(0x0) 3706 #define PADS_BANK0_GPIO46_DRIVE_VALUE_4MA _u(0x1) 3707 #define PADS_BANK0_GPIO46_DRIVE_VALUE_8MA _u(0x2) 3708 #define PADS_BANK0_GPIO46_DRIVE_VALUE_12MA _u(0x3) 3709 // ----------------------------------------------------------------------------- 3710 // Field : PADS_BANK0_GPIO46_PUE 3711 // Description : Pull up enable 3712 #define PADS_BANK0_GPIO46_PUE_RESET _u(0x0) 3713 #define PADS_BANK0_GPIO46_PUE_BITS _u(0x00000008) 3714 #define PADS_BANK0_GPIO46_PUE_MSB _u(3) 3715 #define PADS_BANK0_GPIO46_PUE_LSB _u(3) 3716 #define PADS_BANK0_GPIO46_PUE_ACCESS "RW" 3717 // ----------------------------------------------------------------------------- 3718 // Field : PADS_BANK0_GPIO46_PDE 3719 // Description : Pull down enable 3720 #define PADS_BANK0_GPIO46_PDE_RESET _u(0x1) 3721 #define PADS_BANK0_GPIO46_PDE_BITS _u(0x00000004) 3722 #define PADS_BANK0_GPIO46_PDE_MSB _u(2) 3723 #define PADS_BANK0_GPIO46_PDE_LSB _u(2) 3724 #define PADS_BANK0_GPIO46_PDE_ACCESS "RW" 3725 // ----------------------------------------------------------------------------- 3726 // Field : PADS_BANK0_GPIO46_SCHMITT 3727 // Description : Enable schmitt trigger 3728 #define PADS_BANK0_GPIO46_SCHMITT_RESET _u(0x1) 3729 #define PADS_BANK0_GPIO46_SCHMITT_BITS _u(0x00000002) 3730 #define PADS_BANK0_GPIO46_SCHMITT_MSB _u(1) 3731 #define PADS_BANK0_GPIO46_SCHMITT_LSB _u(1) 3732 #define PADS_BANK0_GPIO46_SCHMITT_ACCESS "RW" 3733 // ----------------------------------------------------------------------------- 3734 // Field : PADS_BANK0_GPIO46_SLEWFAST 3735 // Description : Slew rate control. 1 = Fast, 0 = Slow 3736 #define PADS_BANK0_GPIO46_SLEWFAST_RESET _u(0x0) 3737 #define PADS_BANK0_GPIO46_SLEWFAST_BITS _u(0x00000001) 3738 #define PADS_BANK0_GPIO46_SLEWFAST_MSB _u(0) 3739 #define PADS_BANK0_GPIO46_SLEWFAST_LSB _u(0) 3740 #define PADS_BANK0_GPIO46_SLEWFAST_ACCESS "RW" 3741 // ============================================================================= 3742 // Register : PADS_BANK0_GPIO47 3743 #define PADS_BANK0_GPIO47_OFFSET _u(0x000000c0) 3744 #define PADS_BANK0_GPIO47_BITS _u(0x000001ff) 3745 #define PADS_BANK0_GPIO47_RESET _u(0x00000116) 3746 // ----------------------------------------------------------------------------- 3747 // Field : PADS_BANK0_GPIO47_ISO 3748 // Description : Pad isolation control. Remove this once the pad is configured 3749 // by software. 3750 #define PADS_BANK0_GPIO47_ISO_RESET _u(0x1) 3751 #define PADS_BANK0_GPIO47_ISO_BITS _u(0x00000100) 3752 #define PADS_BANK0_GPIO47_ISO_MSB _u(8) 3753 #define PADS_BANK0_GPIO47_ISO_LSB _u(8) 3754 #define PADS_BANK0_GPIO47_ISO_ACCESS "RW" 3755 // ----------------------------------------------------------------------------- 3756 // Field : PADS_BANK0_GPIO47_OD 3757 // Description : Output disable. Has priority over output enable from 3758 // peripherals 3759 #define PADS_BANK0_GPIO47_OD_RESET _u(0x0) 3760 #define PADS_BANK0_GPIO47_OD_BITS _u(0x00000080) 3761 #define PADS_BANK0_GPIO47_OD_MSB _u(7) 3762 #define PADS_BANK0_GPIO47_OD_LSB _u(7) 3763 #define PADS_BANK0_GPIO47_OD_ACCESS "RW" 3764 // ----------------------------------------------------------------------------- 3765 // Field : PADS_BANK0_GPIO47_IE 3766 // Description : Input enable 3767 #define PADS_BANK0_GPIO47_IE_RESET _u(0x0) 3768 #define PADS_BANK0_GPIO47_IE_BITS _u(0x00000040) 3769 #define PADS_BANK0_GPIO47_IE_MSB _u(6) 3770 #define PADS_BANK0_GPIO47_IE_LSB _u(6) 3771 #define PADS_BANK0_GPIO47_IE_ACCESS "RW" 3772 // ----------------------------------------------------------------------------- 3773 // Field : PADS_BANK0_GPIO47_DRIVE 3774 // Description : Drive strength. 3775 // 0x0 -> 2mA 3776 // 0x1 -> 4mA 3777 // 0x2 -> 8mA 3778 // 0x3 -> 12mA 3779 #define PADS_BANK0_GPIO47_DRIVE_RESET _u(0x1) 3780 #define PADS_BANK0_GPIO47_DRIVE_BITS _u(0x00000030) 3781 #define PADS_BANK0_GPIO47_DRIVE_MSB _u(5) 3782 #define PADS_BANK0_GPIO47_DRIVE_LSB _u(4) 3783 #define PADS_BANK0_GPIO47_DRIVE_ACCESS "RW" 3784 #define PADS_BANK0_GPIO47_DRIVE_VALUE_2MA _u(0x0) 3785 #define PADS_BANK0_GPIO47_DRIVE_VALUE_4MA _u(0x1) 3786 #define PADS_BANK0_GPIO47_DRIVE_VALUE_8MA _u(0x2) 3787 #define PADS_BANK0_GPIO47_DRIVE_VALUE_12MA _u(0x3) 3788 // ----------------------------------------------------------------------------- 3789 // Field : PADS_BANK0_GPIO47_PUE 3790 // Description : Pull up enable 3791 #define PADS_BANK0_GPIO47_PUE_RESET _u(0x0) 3792 #define PADS_BANK0_GPIO47_PUE_BITS _u(0x00000008) 3793 #define PADS_BANK0_GPIO47_PUE_MSB _u(3) 3794 #define PADS_BANK0_GPIO47_PUE_LSB _u(3) 3795 #define PADS_BANK0_GPIO47_PUE_ACCESS "RW" 3796 // ----------------------------------------------------------------------------- 3797 // Field : PADS_BANK0_GPIO47_PDE 3798 // Description : Pull down enable 3799 #define PADS_BANK0_GPIO47_PDE_RESET _u(0x1) 3800 #define PADS_BANK0_GPIO47_PDE_BITS _u(0x00000004) 3801 #define PADS_BANK0_GPIO47_PDE_MSB _u(2) 3802 #define PADS_BANK0_GPIO47_PDE_LSB _u(2) 3803 #define PADS_BANK0_GPIO47_PDE_ACCESS "RW" 3804 // ----------------------------------------------------------------------------- 3805 // Field : PADS_BANK0_GPIO47_SCHMITT 3806 // Description : Enable schmitt trigger 3807 #define PADS_BANK0_GPIO47_SCHMITT_RESET _u(0x1) 3808 #define PADS_BANK0_GPIO47_SCHMITT_BITS _u(0x00000002) 3809 #define PADS_BANK0_GPIO47_SCHMITT_MSB _u(1) 3810 #define PADS_BANK0_GPIO47_SCHMITT_LSB _u(1) 3811 #define PADS_BANK0_GPIO47_SCHMITT_ACCESS "RW" 3812 // ----------------------------------------------------------------------------- 3813 // Field : PADS_BANK0_GPIO47_SLEWFAST 3814 // Description : Slew rate control. 1 = Fast, 0 = Slow 3815 #define PADS_BANK0_GPIO47_SLEWFAST_RESET _u(0x0) 3816 #define PADS_BANK0_GPIO47_SLEWFAST_BITS _u(0x00000001) 3817 #define PADS_BANK0_GPIO47_SLEWFAST_MSB _u(0) 3818 #define PADS_BANK0_GPIO47_SLEWFAST_LSB _u(0) 3819 #define PADS_BANK0_GPIO47_SLEWFAST_ACCESS "RW" 3820 // ============================================================================= 3821 // Register : PADS_BANK0_SWCLK 3822 #define PADS_BANK0_SWCLK_OFFSET _u(0x000000c4) 3823 #define PADS_BANK0_SWCLK_BITS _u(0x000001ff) 3824 #define PADS_BANK0_SWCLK_RESET _u(0x0000005a) 3825 // ----------------------------------------------------------------------------- 3826 // Field : PADS_BANK0_SWCLK_ISO 3827 // Description : Pad isolation control. Remove this once the pad is configured 3828 // by software. 3829 #define PADS_BANK0_SWCLK_ISO_RESET _u(0x0) 3830 #define PADS_BANK0_SWCLK_ISO_BITS _u(0x00000100) 3831 #define PADS_BANK0_SWCLK_ISO_MSB _u(8) 3832 #define PADS_BANK0_SWCLK_ISO_LSB _u(8) 3833 #define PADS_BANK0_SWCLK_ISO_ACCESS "RW" 3834 // ----------------------------------------------------------------------------- 3835 // Field : PADS_BANK0_SWCLK_OD 3836 // Description : Output disable. Has priority over output enable from 3837 // peripherals 3838 #define PADS_BANK0_SWCLK_OD_RESET _u(0x0) 3839 #define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080) 3840 #define PADS_BANK0_SWCLK_OD_MSB _u(7) 3841 #define PADS_BANK0_SWCLK_OD_LSB _u(7) 3842 #define PADS_BANK0_SWCLK_OD_ACCESS "RW" 3843 // ----------------------------------------------------------------------------- 3844 // Field : PADS_BANK0_SWCLK_IE 3845 // Description : Input enable 3846 #define PADS_BANK0_SWCLK_IE_RESET _u(0x1) 3847 #define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040) 3848 #define PADS_BANK0_SWCLK_IE_MSB _u(6) 3849 #define PADS_BANK0_SWCLK_IE_LSB _u(6) 3850 #define PADS_BANK0_SWCLK_IE_ACCESS "RW" 3851 // ----------------------------------------------------------------------------- 3852 // Field : PADS_BANK0_SWCLK_DRIVE 3853 // Description : Drive strength. 3854 // 0x0 -> 2mA 3855 // 0x1 -> 4mA 3856 // 0x2 -> 8mA 3857 // 0x3 -> 12mA 3858 #define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1) 3859 #define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030) 3860 #define PADS_BANK0_SWCLK_DRIVE_MSB _u(5) 3861 #define PADS_BANK0_SWCLK_DRIVE_LSB _u(4) 3862 #define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW" 3863 #define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0) 3864 #define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1) 3865 #define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2) 3866 #define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3) 3867 // ----------------------------------------------------------------------------- 3868 // Field : PADS_BANK0_SWCLK_PUE 3869 // Description : Pull up enable 3870 #define PADS_BANK0_SWCLK_PUE_RESET _u(0x1) 3871 #define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008) 3872 #define PADS_BANK0_SWCLK_PUE_MSB _u(3) 3873 #define PADS_BANK0_SWCLK_PUE_LSB _u(3) 3874 #define PADS_BANK0_SWCLK_PUE_ACCESS "RW" 3875 // ----------------------------------------------------------------------------- 3876 // Field : PADS_BANK0_SWCLK_PDE 3877 // Description : Pull down enable 3878 #define PADS_BANK0_SWCLK_PDE_RESET _u(0x0) 3879 #define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004) 3880 #define PADS_BANK0_SWCLK_PDE_MSB _u(2) 3881 #define PADS_BANK0_SWCLK_PDE_LSB _u(2) 3882 #define PADS_BANK0_SWCLK_PDE_ACCESS "RW" 3883 // ----------------------------------------------------------------------------- 3884 // Field : PADS_BANK0_SWCLK_SCHMITT 3885 // Description : Enable schmitt trigger 3886 #define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1) 3887 #define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002) 3888 #define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1) 3889 #define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1) 3890 #define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW" 3891 // ----------------------------------------------------------------------------- 3892 // Field : PADS_BANK0_SWCLK_SLEWFAST 3893 // Description : Slew rate control. 1 = Fast, 0 = Slow 3894 #define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0) 3895 #define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001) 3896 #define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0) 3897 #define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0) 3898 #define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW" 3899 // ============================================================================= 3900 // Register : PADS_BANK0_SWD 3901 #define PADS_BANK0_SWD_OFFSET _u(0x000000c8) 3902 #define PADS_BANK0_SWD_BITS _u(0x000001ff) 3903 #define PADS_BANK0_SWD_RESET _u(0x0000005a) 3904 // ----------------------------------------------------------------------------- 3905 // Field : PADS_BANK0_SWD_ISO 3906 // Description : Pad isolation control. Remove this once the pad is configured 3907 // by software. 3908 #define PADS_BANK0_SWD_ISO_RESET _u(0x0) 3909 #define PADS_BANK0_SWD_ISO_BITS _u(0x00000100) 3910 #define PADS_BANK0_SWD_ISO_MSB _u(8) 3911 #define PADS_BANK0_SWD_ISO_LSB _u(8) 3912 #define PADS_BANK0_SWD_ISO_ACCESS "RW" 3913 // ----------------------------------------------------------------------------- 3914 // Field : PADS_BANK0_SWD_OD 3915 // Description : Output disable. Has priority over output enable from 3916 // peripherals 3917 #define PADS_BANK0_SWD_OD_RESET _u(0x0) 3918 #define PADS_BANK0_SWD_OD_BITS _u(0x00000080) 3919 #define PADS_BANK0_SWD_OD_MSB _u(7) 3920 #define PADS_BANK0_SWD_OD_LSB _u(7) 3921 #define PADS_BANK0_SWD_OD_ACCESS "RW" 3922 // ----------------------------------------------------------------------------- 3923 // Field : PADS_BANK0_SWD_IE 3924 // Description : Input enable 3925 #define PADS_BANK0_SWD_IE_RESET _u(0x1) 3926 #define PADS_BANK0_SWD_IE_BITS _u(0x00000040) 3927 #define PADS_BANK0_SWD_IE_MSB _u(6) 3928 #define PADS_BANK0_SWD_IE_LSB _u(6) 3929 #define PADS_BANK0_SWD_IE_ACCESS "RW" 3930 // ----------------------------------------------------------------------------- 3931 // Field : PADS_BANK0_SWD_DRIVE 3932 // Description : Drive strength. 3933 // 0x0 -> 2mA 3934 // 0x1 -> 4mA 3935 // 0x2 -> 8mA 3936 // 0x3 -> 12mA 3937 #define PADS_BANK0_SWD_DRIVE_RESET _u(0x1) 3938 #define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030) 3939 #define PADS_BANK0_SWD_DRIVE_MSB _u(5) 3940 #define PADS_BANK0_SWD_DRIVE_LSB _u(4) 3941 #define PADS_BANK0_SWD_DRIVE_ACCESS "RW" 3942 #define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0) 3943 #define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1) 3944 #define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2) 3945 #define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3) 3946 // ----------------------------------------------------------------------------- 3947 // Field : PADS_BANK0_SWD_PUE 3948 // Description : Pull up enable 3949 #define PADS_BANK0_SWD_PUE_RESET _u(0x1) 3950 #define PADS_BANK0_SWD_PUE_BITS _u(0x00000008) 3951 #define PADS_BANK0_SWD_PUE_MSB _u(3) 3952 #define PADS_BANK0_SWD_PUE_LSB _u(3) 3953 #define PADS_BANK0_SWD_PUE_ACCESS "RW" 3954 // ----------------------------------------------------------------------------- 3955 // Field : PADS_BANK0_SWD_PDE 3956 // Description : Pull down enable 3957 #define PADS_BANK0_SWD_PDE_RESET _u(0x0) 3958 #define PADS_BANK0_SWD_PDE_BITS _u(0x00000004) 3959 #define PADS_BANK0_SWD_PDE_MSB _u(2) 3960 #define PADS_BANK0_SWD_PDE_LSB _u(2) 3961 #define PADS_BANK0_SWD_PDE_ACCESS "RW" 3962 // ----------------------------------------------------------------------------- 3963 // Field : PADS_BANK0_SWD_SCHMITT 3964 // Description : Enable schmitt trigger 3965 #define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1) 3966 #define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002) 3967 #define PADS_BANK0_SWD_SCHMITT_MSB _u(1) 3968 #define PADS_BANK0_SWD_SCHMITT_LSB _u(1) 3969 #define PADS_BANK0_SWD_SCHMITT_ACCESS "RW" 3970 // ----------------------------------------------------------------------------- 3971 // Field : PADS_BANK0_SWD_SLEWFAST 3972 // Description : Slew rate control. 1 = Fast, 0 = Slow 3973 #define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0) 3974 #define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001) 3975 #define PADS_BANK0_SWD_SLEWFAST_MSB _u(0) 3976 #define PADS_BANK0_SWD_SLEWFAST_LSB _u(0) 3977 #define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW" 3978 // ============================================================================= 3979 #endif // _HARDWARE_REGS_PADS_BANK0_H 3980 3981
